1 Mesa 17.0.2 Release Notes / March 20, 2017
2 ==========================================
4 Mesa 17.0.2 is a bug fix release which fixes bugs found since the 17.0.1
7 Mesa 17.0.2 implements the OpenGL 4.5 API, but the version reported by
8 glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
9 glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being
10 used. Some drivers don't support all the features required in OpenGL
11 4.5. OpenGL 4.5 is **only** available if requested at context creation
12 because compatibility contexts are not supported.
19 2e0f41e7974ba7a36ca32bbeaf8ebcd65c8fd4d2dc9872f04d4becbd5e7a8cb5 mesa-17.0.2.tar.gz
20 f8f191f909e01e65de38d5bdea5fb057f21649a3aed20948be02348e77a689d4 mesa-17.0.2.tar.xz
30 - `Bug 68504 <https://bugs.freedesktop.org/show_bug.cgi?id=68504>`__ -
31 9.2-rc1 workaround for clover build failure on ppc/altivec: cannot
32 convert 'bool' to '__vector(4) \__bool int' in return
33 - `Bug 97988 <https://bugs.freedesktop.org/show_bug.cgi?id=97988>`__ -
34 [radeonsi] playing back videos with VDPAU exhibits
35 deinterlacing/anti-aliasing issues not visible with VA-API
36 - `Bug 99484 <https://bugs.freedesktop.org/show_bug.cgi?id=99484>`__ -
37 Crusader Kings 2 - Loading bars, siege bars, morale bars, etc. do not
39 - `Bug 99715 <https://bugs.freedesktop.org/show_bug.cgi?id=99715>`__ -
40 Don't print: "Note: Buggy applications may crash, if they do please
42 - `Bug 100049 <https://bugs.freedesktop.org/show_bug.cgi?id=100049>`__
43 - "ralloc: Make sure ralloc() allocations match malloc()'s
44 alignment." causes seg fault in 32bit build
51 - radv: Emit pending flushes before executing a secondary command
53 - radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer
54 - radv/ac: Fix shared memory offset calculation
56 Bas Nieuwenhuizen (3):
58 - radv: Disable HTILE for textures with multiple layers/levels.
59 - radv: Emit cache flushes before CP DMA.
60 - Revert "radv: Emit cache flushes before CP DMA."
64 - radv: drop Z24 support.
65 - radv: disable mip point pre clamping.
66 - radv: setup llvm target data layout
70 - docs: add sha256 checksums for 17.0.1
71 - cherry-ignore: add the swizzle blorp_clear fix
72 - i965: move brw_define.h ifndef guard to the top
73 - Update version to 17.0.2
77 - radv: fix the dynamic buffer index in vkCmdBindDescriptorSets
78 - radv/ac: fix multiple descriptor sets with dynamic buffers
82 - glapi: fix typo in count_scale
86 - nvc0: take extra pushbuf space into account for pushbuf_space calls
87 - nvc0: increase alignment to 256 for texture buffers on fermi
91 - vulkan/wsi: Improve the DRI3 error message
95 - radv: Fix using more than 4 bound descriptor sets
99 - anv/blorp/clear_subpass: Only set surface clear color for fast clears
100 - anv: Accurately advertise dynamic descriptor limits
101 - anv: Stall before fast-clear operations
102 - anv: Properly handle destroying NULL devices and instances
103 - anv/blorp: Turn off AUX after doing a CCS_D resolve
104 - anv/blorp: Only set a clear color for resolves if fast-cleared
105 - nir/intrinsics: Make load_barycentric_input take a 2-component coor
109 - ralloc: Make sure ralloc() allocations match malloc()'s alignment.
113 - egl: Ensure ResetNotificationStrategy matches for shared contexts.
117 - st/mesa: reset sample_mask, min_sample, and render_condition for PBO
119 - st/mesa: set blend state for PBO readbacks
120 - radeonsi: mark all bound shader buffer ranges as initialized
124 - clover: Work around build failure with AltiVec.
128 - anv/pass: Avoid accessing attachment array out of bounds
129 - anv/image: Remove extra dependency on HiZ-specific variable
133 - st/glsl_to_tgsi: avoid iterating past the head of the instruction
135 - st/mesa: inform the driver of framebuffer changes before compute
140 - mesa: Avoid read of uninitialized variable
142 Samuel Iglesias Gonsálvez (5):
144 - i965/fs: mark last DF uniform array element as 64 bit live one
145 - i965/fs: detect different bit size accesses to uniforms to push them
147 - i965/fs: fix indirect load DF uniforms on BSW/BXT
148 - i965/fs: fix source type when emitting MOV_INDIRECT to read ICP
150 - i965/fs: emit MOV_INDIRECT with the source with the right register
155 - radeonsi: disable sinking common instructions down to the end block