2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
11 DRAM_INIT_FILE : string := "";
12 DRAM_INIT_SIZE : natural := 0
16 architecture behave of dram_tb is
17 signal clk, rst: std_logic;
18 signal clk_in, soc_rst : std_ulogic;
21 constant clk_period : time := 10 ns;
24 signal wb_in : wishbone_master_out;
25 signal wb_out : wishbone_slave_out;
26 signal wb_ctrl_in : wb_io_master_out;
28 subtype addr_t is std_ulogic_vector(wb_in.adr'left downto 0);
29 subtype data_t is std_ulogic_vector(wb_in.dat'left downto 0);
30 subtype sel_t is std_ulogic_vector(wb_in.sel'left downto 0);
33 signal acks : integer := 0;
34 signal reset_acks : std_ulogic;
37 signal rd_ready : std_ulogic := '0';
38 signal rd_valid : std_ulogic;
39 signal rd_data : data_t;
42 dram: entity work.litedram_wrapper
47 DRAM_PORT_WIDTH => 128,
48 PAYLOAD_FILE => DRAM_INIT_FILE,
49 PAYLOAD_SIZE => DRAM_INIT_SIZE
55 system_reset => soc_rst,
56 core_alt_reset => open,
61 wb_ctrl_in => wb_ctrl_in,
63 wb_ctrl_is_csr => '0',
64 wb_ctrl_is_init => '0',
89 wait for clk_period/2;
91 wait for clk_period/2;
97 wait for 10*clk_period;
102 wb_ctrl_in.cyc <= '0';
103 wb_ctrl_in.stb <= '0';
105 -- Read data receive queue
106 data_queue: entity work.sync_fifo
109 WIDTH => rd_data'length
113 reset => soc_rst or reset_acks,
114 rd_ready => rd_ready,
115 rd_valid => rd_valid,
118 wr_valid => wb_out.ack,
119 wr_data => wb_out.dat
122 recv_acks: process(clk)
124 if rising_edge(clk) then
125 if rst = '1' or reset_acks = '1' then
127 elsif wb_out.ack = '1' then
129 -- report "WB ACK ! DATA=" & to_hstring(wb_out.dat);
135 procedure wb_write(addr: addr_t; data: data_t; sel: sel_t) is
144 wait until rising_edge(clk);
145 if wb_out.stall = '0' then
152 procedure wb_read(addr: addr_t) is
160 wait until rising_edge(clk);
161 if wb_out.stall = '0' then
168 procedure wait_acks(count: integer) is
170 wait until acks = count;
171 wait until rising_edge(clk);
174 procedure clr_acks is
177 wait until rising_edge(clk);
181 procedure read_data(data: out data_t) is
183 assert rd_valid = '1' report "No data to read" severity failure;
185 wait until rising_edge(clk);
190 function add_off(a: addr_t; off: integer) return addr_t is
192 return addr_t(unsigned(a) + off);
195 function make_pattern(num : integer) return data_t is
197 variable t,b : integer;
199 for i in 0 to (data_t'length/8)-1 loop
202 r(t downto b) := std_ulogic_vector(to_unsigned(num+1, 8));
207 procedure check_data(p: data_t) is
211 assert d = p report "bad data, want " & to_hstring(p) &
212 " got " & to_hstring(d) severity failure;
215 variable a : addr_t := (others => '0');
216 variable d : data_t := (others => '0');
217 variable d1 : data_t := (others => '0');
221 wait until rising_edge(clk_in);
222 wait until rising_edge(clk_in);
223 wait until rising_edge(clk_in);
224 wait until rising_edge(clk_in);
225 wait until rising_edge(clk_in);
227 wait until rising_edge(clk_in);
228 wait until soc_rst = '0';
229 wait until rising_edge(clk);
231 report "Simple write miss...";
233 wb_write(a, x"0123456789abcdef", x"ff");
236 report "Simple read miss...";
241 assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure;
243 report "Simple read hit...";
248 assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure;
250 report "Back to back 4 stores 4 reads on hit...";
253 wb_write(add_off(a, i*8), make_pattern(i), x"ff");
256 wb_read(add_off(a, i*8));
263 check_data(make_pattern(i-4));
267 report "Back to back 4 stores 4 reads on miss...";
271 wb_write(add_off(a, i*8), make_pattern(i), x"ff");
274 wb_read(add_off(a, i*8));
281 check_data(make_pattern(i-4));
285 report "Back to back interleaved 4 stores 4 reads on hit...";
289 wb_write(add_off(a, i*8), make_pattern(i), x"ff");
290 wb_read(add_off(a, i*8));
295 check_data(make_pattern(i));
298 report "Pre-fill a line";
301 wb_write(add_off(a, 0), x"1111111100000000", x"ff");
302 wb_write(add_off(a, 8), x"3333333322222222", x"ff");
303 wb_write(add_off(a, 16), x"5555555544444444", x"ff");
304 wb_write(add_off(a, 24), x"7777777766666666", x"ff");
305 wb_write(add_off(a, 32), x"9999999988888888", x"ff");
306 wb_write(add_off(a, 40), x"bbbbbbbbaaaaaaaa", x"ff");
307 wb_write(add_off(a, 48), x"ddddddddcccccccc", x"ff");
308 wb_write(add_off(a, 56), x"ffffffffeeeeeeee", x"ff");
309 wb_write(add_off(a, 64), x"1111111100000000", x"ff");
310 wb_write(add_off(a, 72), x"3333333322222222", x"ff");
311 wb_write(add_off(a, 80), x"5555555544444444", x"ff");
312 wb_write(add_off(a, 88), x"7777777766666666", x"ff");
313 wb_write(add_off(a, 96), x"9999999988888888", x"ff");
314 wb_write(add_off(a,104), x"bbbbbbbbaaaaaaaa", x"ff");
315 wb_write(add_off(a,112), x"ddddddddcccccccc", x"ff");
316 wb_write(add_off(a,120), x"ffffffffeeeeeeee", x"ff");
319 report "Scattered from middle of line...";
321 wb_read(add_off(a,24));
322 wb_read(add_off(a,32));
323 wb_read(add_off(a, 0));
324 wb_read(add_off(a,16));
327 assert d = x"7777777766666666" report "bad data (24), got " & to_hstring(d) severity failure;
329 assert d = x"9999999988888888" report "bad data (32), got " & to_hstring(d) severity failure;
331 assert d = x"1111111100000000" report "bad data (0), got " & to_hstring(d) severity failure;
333 assert d = x"5555555544444444" report "bad data (16), got " & to_hstring(d) severity failure;