2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
11 DRAM_INIT_FILE : string := "";
12 DRAM_INIT_SIZE : natural := 0
16 architecture behave of dram_tb is
17 signal clk, rst: std_logic;
18 signal clk_in, soc_rst : std_ulogic;
21 constant clk_period : time := 10 ns;
24 signal wb_in : wishbone_master_out;
25 signal wb_out : wishbone_slave_out;
26 signal wb_ctrl_in : wb_io_master_out;
28 subtype addr_t is std_ulogic_vector(wb_in.adr'left downto 0);
29 subtype data_t is std_ulogic_vector(wb_in.dat'left downto 0);
30 subtype sel_t is std_ulogic_vector(wb_in.sel'left downto 0);
33 signal acks : integer := 0;
34 signal reset_acks : std_ulogic;
37 signal rd_ready : std_ulogic := '0';
38 signal rd_valid : std_ulogic;
39 signal rd_data : data_t;
42 dram: entity work.litedram_wrapper
48 DRAM_PORT_WIDTH => 128,
49 PAYLOAD_FILE => DRAM_INIT_FILE,
50 PAYLOAD_SIZE => DRAM_INIT_SIZE
56 system_reset => soc_rst,
57 core_alt_reset => open,
62 wb_ctrl_in => wb_ctrl_in,
64 wb_ctrl_is_csr => '0',
65 wb_ctrl_is_init => '0',
90 wait for clk_period/2;
92 wait for clk_period/2;
98 wait for 10*clk_period;
103 wb_ctrl_in.cyc <= '0';
104 wb_ctrl_in.stb <= '0';
106 -- Read data receive queue
107 data_queue: entity work.sync_fifo
110 WIDTH => rd_data'length
114 reset => soc_rst or reset_acks,
115 rd_ready => rd_ready,
116 rd_valid => rd_valid,
119 wr_valid => wb_out.ack,
120 wr_data => wb_out.dat
123 recv_acks: process(clk)
125 if rising_edge(clk) then
126 if rst = '1' or reset_acks = '1' then
128 elsif wb_out.ack = '1' then
130 -- report "WB ACK ! DATA=" & to_hstring(wb_out.dat);
136 procedure wb_write(addr: addr_t; data: data_t; sel: sel_t) is
145 wait until rising_edge(clk);
146 if wb_out.stall = '0' then
153 procedure wb_read(addr: addr_t) is
161 wait until rising_edge(clk);
162 if wb_out.stall = '0' then
169 procedure wait_acks(count: integer) is
171 wait until acks = count;
172 wait until rising_edge(clk);
175 procedure clr_acks is
178 wait until rising_edge(clk);
182 procedure read_data(data: out data_t) is
184 assert rd_valid = '1' report "No data to read" severity failure;
186 wait until rising_edge(clk);
191 function add_off(a: addr_t; off: integer) return addr_t is
193 return addr_t(unsigned(a) + off);
196 function make_pattern(num : integer) return data_t is
198 variable t,b : integer;
200 for i in 0 to (data_t'length/8)-1 loop
203 r(t downto b) := std_ulogic_vector(to_unsigned(num+1, 8));
208 procedure check_data(p: data_t) is
212 assert d = p report "bad data, want " & to_hstring(p) &
213 " got " & to_hstring(d) severity failure;
216 variable a : addr_t := (others => '0');
217 variable d : data_t := (others => '0');
218 variable d1 : data_t := (others => '0');
222 wait until rising_edge(clk_in);
223 wait until rising_edge(clk_in);
224 wait until rising_edge(clk_in);
225 wait until rising_edge(clk_in);
226 wait until rising_edge(clk_in);
228 wait until rising_edge(clk_in);
229 wait until soc_rst = '0';
230 wait until rising_edge(clk);
232 report "Simple write miss...";
234 wb_write(a, x"0123456789abcdef", x"ff");
237 report "Simple read miss...";
242 assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure;
244 report "Simple read hit...";
249 assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure;
251 report "Back to back 4 stores 4 reads on hit...";
254 wb_write(add_off(a, i*8), make_pattern(i), x"ff");
257 wb_read(add_off(a, i*8));
264 check_data(make_pattern(i-4));
268 report "Back to back 4 stores 4 reads on miss...";
272 wb_write(add_off(a, i*8), make_pattern(i), x"ff");
275 wb_read(add_off(a, i*8));
282 check_data(make_pattern(i-4));
286 report "Back to back interleaved 4 stores 4 reads on hit...";
290 wb_write(add_off(a, i*8), make_pattern(i), x"ff");
291 wb_read(add_off(a, i*8));
296 check_data(make_pattern(i));
299 report "Pre-fill a line";
302 wb_write(add_off(a, 0), x"1111111100000000", x"ff");
303 wb_write(add_off(a, 8), x"3333333322222222", x"ff");
304 wb_write(add_off(a, 16), x"5555555544444444", x"ff");
305 wb_write(add_off(a, 24), x"7777777766666666", x"ff");
306 wb_write(add_off(a, 32), x"9999999988888888", x"ff");
307 wb_write(add_off(a, 40), x"bbbbbbbbaaaaaaaa", x"ff");
308 wb_write(add_off(a, 48), x"ddddddddcccccccc", x"ff");
309 wb_write(add_off(a, 56), x"ffffffffeeeeeeee", x"ff");
310 wb_write(add_off(a, 64), x"1111111100000000", x"ff");
311 wb_write(add_off(a, 72), x"3333333322222222", x"ff");
312 wb_write(add_off(a, 80), x"5555555544444444", x"ff");
313 wb_write(add_off(a, 88), x"7777777766666666", x"ff");
314 wb_write(add_off(a, 96), x"9999999988888888", x"ff");
315 wb_write(add_off(a,104), x"bbbbbbbbaaaaaaaa", x"ff");
316 wb_write(add_off(a,112), x"ddddddddcccccccc", x"ff");
317 wb_write(add_off(a,120), x"ffffffffeeeeeeee", x"ff");
320 report "Scattered from middle of line...";
322 wb_read(add_off(a,24));
323 wb_read(add_off(a,32));
324 wb_read(add_off(a, 0));
325 wb_read(add_off(a,16));
328 assert d = x"7777777766666666" report "bad data (24), got " & to_hstring(d) severity failure;
330 assert d = x"9999999988888888" report "bad data (32), got " & to_hstring(d) severity failure;
332 assert d = x"1111111100000000" report "bad data (0), got " & to_hstring(d) severity failure;
334 assert d = x"5555555544444444" report "bad data (16), got " & to_hstring(d) severity failure;