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  38 From: "Immanuel, Yehowshua U" <yimmanuel3@gatech.edu>
  39 To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
  40 Thread-Topic: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA
  41  and RISC-V
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  43 Date: Wed, 18 Mar 2020 18:23:46 +0000
  44 Message-ID: <5B1D9989-4E2D-4113-A4AD-0BD030AFFACA@gatech.edu>
  45 References: <bug-186-13@http.bugs.libre-riscv.org/>
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  86 Subject: Re: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA
  87  and RISC-V
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