1 #ifndef _ENV_VIRTUAL_SINGLE_CORE_H
2 #define _ENV_VIRTUAL_SINGLE_CORE_H
4 //-----------------------------------------------------------------------
6 //-----------------------------------------------------------------------
12 #define RVTEST_RV64UF \
17 #define RVTEST_RV64UV \
20 #define RVTEST_CODE_BEGIN \
27 //-----------------------------------------------------------------------
29 //-----------------------------------------------------------------------
31 #define RVTEST_CODE_END \
33 //-----------------------------------------------------------------------
35 //-----------------------------------------------------------------------
37 #define RVTEST_PASS li a0, 1; syscall;
38 #define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
40 //-----------------------------------------------------------------------
42 //-----------------------------------------------------------------------
44 #define RVTEST_DATA_BEGIN
45 #define RVTEST_DATA_END
47 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
48 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
50 //-----------------------------------------------------------------------
51 // Supervisor mode definitions and macros
52 //-----------------------------------------------------------------------
55 #include "../hwacha_xcpt.h"
57 #define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
58 #define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
59 #define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
60 #define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
61 #define dword_bit_pf(dw) ((dw >> 36) & 0x1)
64 asm volatile ("fence" ::: "memory"); })
66 #define vxcptkill() ({ \
67 asm volatile ("vxcptkill"); })
69 #define vxcpthold() ({ \
70 asm volatile ("vxcpthold"); })
72 #define venqcmd(bits, pf) ({ \
73 asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
75 #define venqimm1(bits, pf) ({ \
76 asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
78 #define venqimm2(bits, pf) ({ \
79 asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
81 #define venqcnt(bits, pf) ({ \
82 asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
84 #define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
85 #define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
88 #define PGSIZE (1 << PGSHIFT)
90 #define SIZEOF_TRAPFRAME_T 20784
94 static inline void vsetcfg(long cfg
)
96 asm volatile ("vsetcfg %0" : : "r"(cfg
));
99 static inline void vsetvl(long vl
)
102 asm volatile ("vsetvl %0,%1" : "=r"(__tmp
) : "r"(vl
));
105 static inline long vgetcfg()
108 asm volatile ("vgetcfg %0" : "=r"(cfg
) :);
112 static inline long vgetvl()
115 asm volatile ("vgetvl %0" : "=r"(vl
) :);
118 static inline long vxcptaux()
121 asm volatile ("vxcptaux %0" : "=r"(aux
) :);
125 static inline void vxcptrestore(long* mem
)
127 asm volatile("vxcptrestore %0" : : "r"(mem
) : "memory");
130 static inline void vxcptevac(long* mem
)
132 asm volatile ("vxcptevac %0" : : "r"(mem
));
135 typedef unsigned long pte_t
;
136 #define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
137 #define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
138 #define VPN_BITS (PTIDXBITS * LEVELS)
139 #define VA_BITS (VPN_BITS + PGSHIFT)
140 #define PTES_PER_PT (PGSIZE/sizeof(pte_t))