examples/anlogic/demo.v

   1 module demo (
   2     input wire CLK_IN,
   3     output wire R_LED
   4 );
   5     parameter time1 = 30'd12_000_000;
   6     reg led_state;
   7     reg [29:0] count;
   8
   9     always @(posedge CLK_IN)begin
  10         if(count == time1)begin
  11             count<= 30'd0;
  12             led_state <= ~led_state;
  13         end
  14         else
  15             count <= count + 1'b1;
  16     end
  17     assign R_LED = led_state;
  18 endmodule