examples/basic/fsm.py

   1 from migen import *
   2 from migen.fhdl import verilog
   3
   4 class Example(Module):
   5     def __init__(self):
   6         self.s = Signal()
   7         self.counter = Signal(8)
   8         x = Array(Signal(name="a") for i in range(7))
   9
  10         myfsm = FSM()
  11         self.submodules += myfsm
  12
  13         myfsm.act("FOO",
  14             self.s.eq(1),
  15             NextState("BAR")
  16         )
  17         myfsm.act("BAR",
  18             self.s.eq(0),
  19             NextValue(self.counter, self.counter + 1),
  20             NextValue(x[self.counter], 89),
  21             NextState("FOO")
  22         )
  23
  24         self.be = myfsm.before_entering("FOO")
  25         self.ae = myfsm.after_entering("FOO")
  26         self.bl = myfsm.before_leaving("FOO")
  27         self.al = myfsm.after_leaving("FOO")
  28
  29 if __name__ == "__main__":
  30     example = Example()
  31     print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))