fcabecc14d385a958d20e95155d369d58764fa9d
4 from migen
.fhdl
.verilog
import convert
7 # Create a parent module with two instances of a child module.
8 # Bind input ports to first module and output ports to second,
9 # and create internal signals to connect the first module to the
11 class ParentModule(Module
):
13 self
.inputs
= [Signal(x
+1, name
="input{}".format(x
)) for x
in range(4)]
14 self
.trans
= [Signal(x
+1) for x
in range(4)]
15 self
.outputs
= [Signal(x
+1, name
="output{}".format(x
)) for x
in range(4)]
16 self
.io
= set(self
.inputs
) |
set(self
.outputs
)
17 i
= Instance("ChildModule",
18 i_master_clk
=ClockSignal(),
19 i_master_rst
=ResetSignal(),
20 i_input0
=self
.inputs
[0],
21 i_input1
=self
.inputs
[1],
22 i_input2
=self
.inputs
[2],
23 i_input3
=self
.inputs
[3],
24 o_output0
=self
.trans
[0],
25 o_output1
=self
.trans
[1],
26 o_output2
=self
.trans
[2],
27 o_output3
=self
.trans
[3]
29 j
= Instance("ChildModule",
30 i_master_clk
=ClockSignal(),
31 i_master_rst
=ResetSignal(),
32 i_input0
=self
.trans
[0],
33 i_input1
=self
.trans
[1],
34 i_input2
=self
.trans
[2],
35 i_input3
=self
.trans
[3],
36 o_output0
=self
.outputs
[0],
37 o_output1
=self
.outputs
[1],
38 o_output2
=self
.outputs
[2],
39 o_output3
=self
.outputs
[3]
44 class ChildModule(Module
):
46 self
.inputs
= [Signal(x
+1, name_override
="input{}".format(x
)) for x
in range(4)]
47 self
.outputs
= [Signal(x
+1, name_override
="output{}".format(x
)) for x
in range(4)]
50 self
.sync
.master
+= self
.outputs
[x
].eq(self
.inputs
[x
])
51 self
.io
= self
.io
.union(self
.inputs
)
52 self
.io
= self
.io
.union(self
.outputs
)
55 # Generate RTL for the parent module and the submodule, run through
56 # icarus for a syntax check
57 def test_instance_module():
59 convert(sub
, sub
.io
, name
="ChildModule").write("ChildModule.v")
62 convert(im
, im
.io
, name
="ParentModule").write("ParentModule.v")
64 subprocess
.check_call(["iverilog", "-W", "all",
65 "ParentModule.v", "ChildModule.v"])
67 if __name__
== "__main__":
68 test_instance_module()