examples/basic/local_cd.py

   1 from migen import *
   2 from migen.fhdl import verilog
   3 from migen.genlib.divider import Divider
   4
   5
   6 class CDM(Module):
   7     def __init__(self):
   8         self.submodules.divider = Divider(5)
   9         self.clock_domains.cd_sys = ClockDomain(reset_less=True)
  10
  11
  12 class MultiMod(Module):
  13     def __init__(self):
  14         self.submodules.foo = CDM()
  15         self.submodules.bar = CDM()
  16
  17 if __name__ == "__main__":
  18     mm = MultiMod()
  19     print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))