examples/basic_sim.py

   1 from migen.fhdl.structure import *
   2 from migen.sim.generic import Simulator
   3 from migen.sim.icarus import Runner
   4
   5 # Our simple counter, which increments at every cycle
   6 # and prints its current value in simulation.
   7 class Counter:
   8         def __init__(self):
   9                 self.count = Signal(BV(4))
  10
  11         # This function will be called at every cycle.
  12         def do_simulation(self, s):
  13                 # Simply read the count signal and print it.
  14                 # The output is:
  15                 # Count: 0
  16                 # Count: 1
  17                 # Count: 2
  18                 # ...
  19                 print("Count: " + str(s.rd(self.count)))
  20
  21         def get_fragment(self):
  22                 # At each cycle, increase the value of the count signal.
  23                 # We do it with convertible/synthesizable FHDL code.
  24                 sync = [self.count.eq(self.count + 1)]
  25                 # List our simulation function in the fragment.
  26                 sim = [self.do_simulation]
  27                 return Fragment(sync=sync, sim=sim)
  28
  29 def main():
  30         dut = Counter()
  31         # Use the Icarus Verilog runner.
  32         # We do not specify a top-level object, and use the default.
  33         sim = Simulator(dut.get_fragment(), Runner())
  34         # Since we do not use sim.interrupt, limit the simulation
  35         # to some number of cycles.
  36         sim.run(20)
  37
  38 main()