examples/cmos/counter_tb.v

   1 module counter_tb;
   2
   3   /* Make a reset pulse and specify dump file */
   4   reg reset = 0;
   5   initial begin
   6      $dumpfile("counter_tb.vcd");
   7      $dumpvars(0,counter_tb);
   8
   9      # 0 reset = 1;
  10      # 4 reset = 0;
  11      # 36 reset = 1;
  12      # 4  reset = 0;
  13      # 6 $finish;
  14   end
  15
  16   /* Make enable with period of 8 and 6,7 low */
  17   reg en = 1;
  18   always begin
  19     en = 1;
  20     #6;
  21     en = 0;
  22     #2;
  23   end
  24
  25   /* Make a regular pulsing clock. */
  26   reg clk = 0;
  27   always #1 clk = !clk;
  28
  29   /* UUT */
  30   wire [2:0] count;
  31   counter c1 (clk, reset, en, count);
  32
  33 endmodule