examples/crg.py

   1 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2
   3 from nmigen import *
   4
   5 __ALL__ = ["ECPIX5CRG"]
   6
   7 class PLL(Elaboratable):
   8     def __init__(self, clkin, clksel=Signal(shape=2, reset=2), clkout1=Signal(), clkout2=Signal(), clkout3=Signal(), clkout4=Signal(), lock=Signal(), CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=3, CLK2_DIV=24):
   9         self.clkin = clkin
  10         self.clkout1 = clkout1
  11         self.clkout2 = clkout2
  12         self.clkout3 = clkout3
  13         self.clkout4 = clkout4
  14         self.clksel = clksel
  15         self.lock = lock
  16         self.CLKI_DIV = CLKI_DIV
  17         self.CLKFB_DIV = CLKFB_DIV
  18         self.CLKOP_DIV = CLK1_DIV
  19         self.CLKOS_DIV = CLK2_DIV
  20         self.ports = [
  21             self.clkin,
  22             self.clkout1,
  23             self.clkout2,
  24             self.clkout3,
  25             self.clkout4,
  26             self.clksel,
  27             self.lock,
  28         ]
  29
  30     def elaborate(self, platform):
  31         clkfb = Signal()
  32         pll = Instance("EHXPLLL",
  33                        p_OUTDIVIDER_MUXA='DIVA',
  34                        p_OUTDIVIDER_MUXB='DIVB',
  35                        p_CLKOP_ENABLE='ENABLED',
  36                        p_CLKOS_ENABLE='ENABLED',
  37                        p_CLKOS2_ENABLE='DISABLED',
  38                        p_CLKOS3_ENABLE='DISABLED',
  39                        p_CLKOP_DIV=self.CLKOP_DIV,
  40                        p_CLKOS_DIV=self.CLKOS_DIV,
  41                        p_CLKFB_DIV=self.CLKFB_DIV,
  42                        p_CLKI_DIV=self.CLKI_DIV,
  43                        p_FEEDBK_PATH='INT_OP',
  44                        p_CLKOP_TRIM_POL="FALLING",
  45                        p_CLKOP_TRIM_DELAY=0,
  46                        p_CLKOS_TRIM_POL="FALLING",
  47                        p_CLKOS_TRIM_DELAY=0,
  48                        i_CLKI=self.clkin,
  49                        i_RST=0,
  50                        i_STDBY=0,
  51                        i_PHASESEL0=0,
  52                        i_PHASESEL1=0,
  53                        i_PHASEDIR=0,
  54                        i_PHASESTEP=0,
  55                        i_PHASELOADREG=0,
  56                        i_PLLWAKESYNC=0,
  57                        i_ENCLKOP=1,
  58                        i_ENCLKOS=1,
  59                        i_ENCLKOS2=0,
  60                        i_ENCLKOS3=0,
  61                        o_CLKOP=self.clkout1,
  62                        o_CLKOS=self.clkout2,
  63                        o_CLKOS2=self.clkout3,
  64                        o_CLKOS3=self.clkout4,
  65                        o_LOCK=self.lock,
  66                        )
  67         m = Module()
  68         m.submodules += pll
  69         return m
  70
  71
  72 class ECPIX5CRG(Elaboratable):
  73     def __init__(self):
  74         ...
  75
  76     def elaborate(self, platform):
  77         m = Module()
  78
  79         # Get 100Mhz from oscillator
  80         clk100 = platform.request("clk100")
  81         cd_rawclk = ClockDomain("rawclk", local=True, reset_less=True)
  82         m.d.comb += cd_rawclk.clk.eq(clk100)
  83         m.domains += cd_rawclk
  84
  85         # Reset
  86         reset = platform.request(platform.default_rst).i
  87         gsr0 = Signal()
  88         gsr1 = Signal()
  89
  90         m.submodules += [
  91             Instance("FD1S3AX", p_GSR="DISABLED", i_CK=ClockSignal("rawclk"), i_D=~reset, o_Q=gsr0),
  92             Instance("FD1S3AX", p_GSR="DISABLED", i_CK=ClockSignal("rawclk"), i_D=gsr0,   o_Q=gsr1),
  93             Instance("SGSR", i_CLK=ClockSignal("rawclk"), i_GSR=gsr1),
  94         ]
  95
  96         # Power-on delay (655us)
  97         podcnt = Signal(16, reset=2**16-1)
  98         pod_done = Signal()
  99         with m.If(podcnt != 0):
 100             m.d.rawclk += podcnt.eq(podcnt-1)
 101         m.d.rawclk += pod_done.eq(podcnt == 0)
 102
 103         # Generating sync2x (200Mhz) and init (25Mhz) from clk100
 104         cd_sync2x = ClockDomain("sync2x", local=False)
 105         cd_sync2x_unbuf = ClockDomain("sync2x_unbuf", local=False, reset_less=True)
 106         cd_init = ClockDomain("init", local=False)
 107         cd_sync = ClockDomain("sync", local=False)
 108         cd_dramsync = ClockDomain("dramsync", local=False)
 109         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=3, CLK2_DIV=24,
 110             clkout1=ClockSignal("sync2x_unbuf"), clkout2=ClockSignal("init"))
 111         m.submodules += Instance("ECLKSYNCB",
 112                 i_ECLKI = ClockSignal("sync2x_unbuf"),
 113                 i_STOP  = 0,
 114                 o_ECLKO = ClockSignal("sync2x"))
 115         m.domains += cd_sync2x_unbuf
 116         m.domains += cd_sync2x
 117         m.domains += cd_init
 118         m.domains += cd_sync
 119         m.domains += cd_dramsync
 120         m.d.comb += ResetSignal("init").eq(~pll.lock|~pod_done)
 121         m.d.comb += ResetSignal("sync").eq(~pll.lock|~pod_done)
 122         m.d.comb += ResetSignal("dramsync").eq(~pll.lock|~pod_done)
 123
 124         # # Generating sync (100Mhz) from sync2x
 125
 126         m.submodules += Instance("CLKDIVF",
 127             p_DIV="2.0",
 128             i_ALIGNWD=0,
 129             i_CLKI=ClockSignal("sync2x"),
 130             i_RST=0,
 131             o_CDIVX=ClockSignal("sync"))
 132         m.d.comb += ClockSignal("dramsync").eq(ClockSignal("sync"))
 133
 134         return m