hdl.rec: add basic record support.
[nmigen.git] / examples / ctr.py
1 from nmigen import *
2 from nmigen.cli import main, pysim
3
4
5 class Counter:
6 def __init__(self, width):
7 self.v = Signal(width, reset=2**width-1)
8 self.o = Signal()
9
10 def get_fragment(self, platform):
11 m = Module()
12 m.d.sync += self.v.eq(self.v + 1)
13 m.d.comb += self.o.eq(self.v[-1])
14 return m.lower(platform)
15
16
17 ctr = Counter(width=16)
18 if __name__ == "__main__":
19 main(ctr, ports=[ctr.o])