examples/ctrl.py

   1 from nmigen.fhdl import *
   2 from nmigen.back import rtlil, verilog
   3
   4
   5 class ClockDivisor:
   6     def __init__(self, factor):
   7         self.v = Signal(factor, reset=2**factor-1)
   8         self.o = Signal()
   9         self.ce = Signal()
  10
  11     def get_fragment(self, platform):
  12         m = Module()
  13         m.d.sync += self.v.eq(self.v + 1)
  14         m.d.comb += self.o.eq(self.v[-1])
  15         return CEInserter(self.ce)(m.lower(platform))
  16
  17
  18 sync = ClockDomain()
  19 ctr  = ClockDivisor(factor=16)
  20 frag = ctr.get_fragment(platform=None)
  21 # print(rtlil.convert(frag, ports=[sync.clk, ctr.o, ctr.ce], clock_domains={"sync": sync}))
  22 print(verilog.convert(frag, ports=[sync.clk, ctr.o, ctr.ce], clock_domains={"sync": sync}))