4 from nmigen
.build
import *
5 from nmigen
.vendor
.lattice_ecp5
import *
6 from nmigen_boards
.resources
import *
9 __all__
= ["ECPIX5Platform"]
12 class ECPIX5Platform(LatticeECP5Platform
):
13 device
= "LFE5UM5G-85F"
16 default_clk
= "clk100"
20 Resource("rst", 0, PinsN("AB1", dir="i"), Attrs(IO_TYPE
="LVCMOS33")),
21 Resource("clk100", 0, Pins("K23", dir="i"), Clock(100e6
), Attrs(IO_TYPE
="LVCMOS33")),
23 RGBLEDResource(0, r
="U21", g
="W21", b
="T24", attrs
=Attrs(IO_TYPE
="LVCMOS33")),
24 RGBLEDResource(1, r
="T23", g
="R21", b
="T22", attrs
=Attrs(IO_TYPE
="LVCMOS33")),
25 RGBLEDResource(2, r
="P21", g
="R23", b
="P22", attrs
=Attrs(IO_TYPE
="LVCMOS33")),
26 RGBLEDResource(3, r
="K21", g
="K24", b
="M21", attrs
=Attrs(IO_TYPE
="LVCMOS33")),
30 attrs
=Attrs(IO_TYPE
="LVCMOS33", PULLMODE
="UP")
34 cs
="AA2", clk
="AE3", miso
="AE2", mosi
="AD2", wp
="AF2", hold
="AE1",
35 attrs
=Attrs(IO_TYPE
="LVCMOS33")
38 Resource("eth_rgmii", 0,
39 Subsignal("rst", PinsN("C13", dir="o")),
40 Subsignal("mdio", Pins("A13", dir="io")),
41 Subsignal("mdc", Pins("C11", dir="o")),
42 Subsignal("tx_clk", Pins("A12", dir="o")),
43 Subsignal("tx_ctrl", Pins("C9", dir="o")),
44 Subsignal("tx_data", Pins("D8 C8 B8 A8", dir="o")),
45 Subsignal("rx_clk", Pins("E11", dir="i")),
46 Subsignal("rx_ctrl", Pins("A11", dir="i")),
47 Subsignal("rx_data", Pins("B11 A10 B10 A9", dir="i")),
48 Attrs(IO_TYPE
="LVCMOS33")
50 Resource("eth_int", 0, PinsN("B13", dir="i"), Attrs(IO_TYPE
="LVCMOS33")),
53 clk
="P24", cmd
="M24", dat0
="N26", dat1
="N25", dat2
="N23", dat3
="N21", cd
="L22",
55 # clk_fb="P25", cmd_dir="M23", dat0_dir="N24", dat123_dir="P26",
56 attrs
=Attrs(IO_TYPE
="LVCMOS33"),
59 # ERROR: cannot place differential IO at location PIOB
60 # if we choose to use DiffPairs
62 Subsignal("clk", Pins("H3", dir="o")),
63 #Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")),
64 Subsignal("cke", Pins("P1", dir="o")),
65 Subsignal("we_n", Pins("R3", dir="o")),
66 Subsignal("ras_n", Pins("T3", dir="o")),
67 Subsignal("cas_n", Pins("P2", dir="o")),
68 Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")),
69 Subsignal("ba", Pins("U6 N3 N4", dir="o")),
70 #Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")),
71 Subsignal("dqs", Pins("V4 V1", dir="io"), Attrs(IO_TYPE
="SSTL135D_I", TERMINATION
="OFF", DIFFRESISTOR
="100")),
72 Subsignal("dq", Pins("T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2", dir="io")),
73 Subsignal("dm", Pins("J4 H5", dir="o")),
74 Subsignal("odt", Pins("P3", dir="o")),
75 Attrs(IO_TYPE
="SSTL135_I")
79 Subsignal("rst", PinsN("N6", dir="o")),
80 Subsignal("scl", Pins("C17", dir="io")),
81 Subsignal("sda", Pins("E17", dir="io")),
82 Subsignal("pclk", Pins("C1", dir="o")),
83 Subsignal("vsync", Pins("A4", dir="o")),
84 Subsignal("hsync", Pins("B4", dir="o")),
85 Subsignal("de", Pins("A3", dir="o")),
87 Subsignal("b", Pins("AD25 AC26 AB24 AB25 B3 C3 D3 B1 C2 D2 D1 E3", dir="o")),
88 Subsignal("g", Pins("AA23 AA22 AA24 AA25 E1 F2 F1 D17 D16 E16 J6 H6", dir="o")),
89 Subsignal("r", Pins("AD26 AE25 AF25 AE26 E10 D11 D10 C10 D9 E8 H5 J4", dir="o")),
91 Subsignal("mclk", Pins("E19", dir="o")),
92 Subsignal("sck", Pins("D6", dir="o")),
93 Subsignal("ws", Pins("C6", dir="o")),
94 Subsignal("i2s", Pins("A6 B6 A5 C5", dir="o")),
95 Subsignal("int", PinsN("C4", dir="i")),
96 Attrs(IO_TYPE
="LVTTL33")
100 Subsignal("tx", DiffPairs("AD16", "AD17", dir="o")),
101 Subsignal("rx", DiffPairs("AF15", "AF16", dir="i")),
102 Attrs(IO_TYPE
="LVDS")
106 Subsignal("rst", Pins("E23", dir="o")),
107 Subsignal("clk", Pins("H24", dir="i")),
108 Subsignal("dir", Pins("F22", dir="i")),
109 Subsignal("nxt", Pins("F23", dir="i")),
110 Subsignal("stp", Pins("H23", dir="o")),
111 Subsignal("data", Pins("M26 L25 L26 K25 K26 J23 J26 H25", dir="io")),
112 Attrs(IO_TYPE
="LVCMOS33")
115 Resource("usbc_cfg", 0,
116 Subsignal("scl", Pins("D24", dir="io")),
117 Subsignal("sda", Pins("C24", dir="io")),
118 Subsignal("dir", Pins("B23", dir="i")),
119 Subsignal("id", Pins("D23", dir="i")),
120 Subsignal("int", PinsN("B24", dir="i")),
121 Attrs(IO_TYPE
="LVCMOS33")
123 Resource("usbc_mux", 0,
124 Subsignal("en", Pins("C23", dir="oe")),
125 Subsignal("amsel", Pins("B26", dir="oe")),
126 Subsignal("pol", Pins("D26", dir="o")),
127 Subsignal("lna", DiffPairs( "AF9", "AF10", dir="i"), Attrs(IO_TYPE
="LVCMOS18D")),
128 Subsignal("lnb", DiffPairs("AD10", "AD11", dir="o"), Attrs(IO_TYPE
="LVCMOS18D")),
129 Subsignal("lnc", DiffPairs( "AD7", "AD8", dir="o"), Attrs(IO_TYPE
="LVCMOS18D")),
130 Subsignal("lnd", DiffPairs( "AF6", "AF7", dir="i"), Attrs(IO_TYPE
="LVCMOS18D")),
131 Attrs(IO_TYPE
="LVCMOS33")
136 Connector("pmod", 0, "T25 U25 U24 V24 - - T26 U26 V26 W26 - -"),
137 Connector("pmod", 1, "U23 V23 U22 V21 - - W25 W24 W23 W22 - -"),
138 Connector("pmod", 2, "J24 H22 E21 D18 - - K22 J21 H21 D22 - -"),
139 Connector("pmod", 3, " E4 F4 E6 H4 - - F3 D4 D5 F5 - -"),
140 Connector("pmod", 4, "E26 D25 F26 F25 - - A25 A24 C26 C25 - -"),
141 Connector("pmod", 5, "D19 C21 B21 C22 - - D21 A21 A22 A23 - -"),
142 Connector("pmod", 6, "C16 B17 C18 B19 - - A17 A18 A19 C19 - -"),
143 Connector("pmod", 7, "D14 B14 E14 B16 - - C14 A14 A15 A16 - -"),
147 def file_templates(self
):
149 **super().file_templates
,
150 "{{name}}-openocd.cfg": r
"""
152 ftdi_vid_pid 0x0403 0x6010
154 ftdi_layout_init 0xfff8 0xfffb
158 jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
162 def toolchain_program(self
, products
, name
):
163 openocd
= os
.environ
.get("OPENOCD", "openocd")
164 with products
.extract("{}-openocd.cfg".format(name
), "{}.svf".format(name
)) \
165 as (config_filename
, vector_filename
):
166 subprocess
.check_call([openocd
,
167 "-f", config_filename
,
168 "-c", "transport select jtag; init; svf -quiet {}; exit".format(vector_filename
)
172 # if __name__ == "__main__":
173 # from .test.blinky import Blinky
174 # ECPIX5Platform().build(Blinky(), do_program=True)