examples/gowin/testbench.v

   1 module testbench;
   2         reg clk;
   3
   4         initial begin
   5                 #5 clk = 0;
   6                 forever #5 clk = ~clk;
   7         end
   8
   9         wire [15:0] leds;
  10
  11         initial begin
  12                 // $dumpfile("testbench.vcd");
  13                 // $dumpvars(0, testbench);
  14                 $monitor("%b", leds);
  15         end
  16
  17         demo uut (
  18                 .clk  (clk  ),
  19 `ifdef POST_IMPL
  20                 .\leds[0]  (leds[0]),
  21                 .\leds[1]  (leds[1]),
  22                 .\leds[2]  (leds[2]),
  23                 .\leds[3]  (leds[3]),
  24                 .\leds[4]  (leds[4]),
  25                 .\leds[5]  (leds[5]),
  26                 .\leds[6]  (leds[6]),
  27                 .\leds[7]  (leds[7]),
  28                 .\leds[8]  (leds[8]),
  29                 .\leds[9]  (leds[9]),
  30                 .\leds[10] (leds[10]),
  31                 .\leds[11] (leds[11]),
  32                 .\leds[12] (leds[12]),
  33                 .\leds[13] (leds[13]),
  34                 .\leds[14] (leds[14]),
  35                 .\leds[15] (leds[15])
  36 `else
  37                 .leds(leds)
  38 `endif
  39         );
  40 endmodule