3eb7007c5c6a41492c8f835315f3b474dd6f0b54
[yosys.git] / examples / igloo2 / example.v
1 module top (
2 input clk,
3 output LED1,
4 output LED2,
5 output LED3,
6 output LED4,
7 output LED5
8 );
9
10 localparam BITS = 5;
11 localparam LOG2DELAY = 22;
12
13 reg [BITS+LOG2DELAY-1:0] counter = 0;
14 reg [BITS-1:0] outcnt;
15
16 always @(posedge clk) begin
17 counter <= counter + 1;
18 outcnt <= counter >> LOG2DELAY;
19 end
20
21 assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
22 endmodule