examples/igloo2/example.v

   1 module example (
   2         input  clk,
   3         input  SW1,
   4         input  SW2,
   5         output LED1,
   6         output LED2,
   7         output LED3,
   8         output LED4,
   9
  10         output AA, AB, AC, AD,
  11         output AE, AF, AG, CA
  12 );
  13
  14         localparam BITS = 8;
  15         localparam LOG2DELAY = 22;
  16
  17         reg [BITS+LOG2DELAY-1:0] counter = 0;
  18         reg [BITS-1:0] outcnt;
  19
  20         always @(posedge clk) begin
  21                 counter <= counter + SW1 + SW2 + 1;
  22                 outcnt <= counter >> LOG2DELAY;
  23         end
  24
  25         assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
  26
  27         // assign CA = counter[10];
  28         // seg7enc seg7encinst (
  29         //      .seg({AA, AB, AC, AD, AE, AF, AG}),
  30         //      .dat(CA ? outcnt[3:0] : outcnt[7:4])
  31         // );
  32
  33         assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]);
  34         assign CA = outcnt[7];
  35 endmodule
  36
  37 module seg7enc (
  38         input [3:0] dat,
  39         output [6:0] seg
  40 );
  41         reg [6:0] seg_inv;
  42         always @* begin
  43                 seg_inv = 0;
  44                 case (dat)
  45                         4'h0: seg_inv = 7'b 0111111;
  46                         4'h1: seg_inv = 7'b 0000110;
  47                         4'h2: seg_inv = 7'b 1011011;
  48                         4'h3: seg_inv = 7'b 1001111;
  49                         4'h4: seg_inv = 7'b 1100110;
  50                         4'h5: seg_inv = 7'b 1101101;
  51                         4'h6: seg_inv = 7'b 1111101;
  52                         4'h7: seg_inv = 7'b 0000111;
  53                         4'h8: seg_inv = 7'b 1111111;
  54                         4'h9: seg_inv = 7'b 1101111;
  55                         4'hA: seg_inv = 7'b 1110111;
  56                         4'hB: seg_inv = 7'b 1111100;
  57                         4'hC: seg_inv = 7'b 0111001;
  58                         4'hD: seg_inv = 7'b 1011110;
  59                         4'hE: seg_inv = 7'b 1111001;
  60                         4'hF: seg_inv = 7'b 1110001;
  61                 endcase
  62         end
  63         assign seg = ~seg_inv;
  64 endmodule