Improve igloo2 exmaple
[yosys.git] / examples / igloo2 / example.v
1 module example (
2 input clk,
3 input SW1,
4 input SW2,
5 output LED1,
6 output LED2,
7 output LED3,
8 output LED4
9 );
10
11 localparam BITS = 4;
12 localparam LOG2DELAY = 22;
13
14 reg [BITS+LOG2DELAY-1:0] counter = 0;
15 reg [BITS-1:0] outcnt;
16
17 always @(posedge clk) begin
18 counter <= counter + SW1 + SW2 + 1;
19 outcnt <= counter >> LOG2DELAY;
20 end
21
22 assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
23 endmodule