765b0de82f8aca4f10876d5b38d67ae4c4503767
[litex.git] / examples / memory_sim.py
1 from migen.fhdl.structure import *
2 from migen.sim.generic import Simulator
3 from migen.sim.icarus import Runner
4
5 class Mem:
6 def __init__(self):
7 self.a = Signal(BV(12))
8 self.d = Signal(BV(16))
9 p = MemoryPort(self.a, self.d)
10 # Initialize the beginning of the memory with integers
11 # from 0 to 19.
12 self.mem = Memory(16, 2**12, p, init=list(range(20)))
13
14 def do_simulation(self, s):
15 # Read the memory. Use the cycle counter as address.
16 value = s.rd(self.mem, s.cycle_counter)
17 # Print the result. Output is:
18 # 0
19 # 1
20 # 2
21 # ...
22 print(value)
23 # Demonstrate how to interrupt the simulator.
24 if value == 10:
25 s.interrupt = True
26
27 def get_fragment(self):
28 return Fragment(memories=[self.mem], sim=[self.do_simulation])
29
30 def main():
31 dut = Mem()
32 sim = Simulator(dut.get_fragment(), Runner())
33 # No need for a cycle limit here, we use sim.interrupt instead.
34 sim.run()
35
36 main()