1 from nmigen
.fhdl
import *
2 from nmigen
.back
import rtlil
, verilog
6 def __init__(self
, width
):
10 self
.c
= Signal(width
)
11 self
.o
= Signal(width
)
13 def get_fragment(self
, platform
):
15 with m
.Switch(self
.s
):
17 m
.d
.comb
+= self
.o
.eq(self
.a
)
19 m
.d
.comb
+= self
.o
.eq(self
.b
)
21 m
.d
.comb
+= self
.o
.eq(self
.c
)
23 m
.d
.comb
+= self
.o
.eq(0)
24 return m
.lower(platform
)
27 pmux
= ParMux(width
=16)
28 frag
= pmux
.get_fragment(platform
=None)
29 # print(rtlil.convert(frag, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o]))
30 print(verilog
.convert(frag
, ports
=[pmux
.s
, pmux
.a
, pmux
.b
, pmux
.c
, pmux
.o
]))