1 // Whatever the initial content of this memory is at reset, it will never change
2 // see demo3.smtc for assumptions and assertions
4 module demo3(input clk, rst, input [15:0] addr, output reg [31:0] data);
5 reg [31:0] mem [0:2**16-1];
8 always @(posedge clk) begin
10 data <= mem[0] ^ 123456789;
13 mem[addr_q] <= data ^ 123456789;
14 data <= mem[addr] ^ 123456789;