Merge pull request #1130 from YosysHQ/eddie/fix710
[yosys.git] / examples / smtbmc / demo4.v
1 // Demo for "final" smtc constraints
2
3 module demo4(input clk, rst, inv2, input [15:0] in, output reg [15:0] r1, r2);
4 always @(posedge clk) begin
5 if (rst) begin
6 r1 <= in;
7 r2 <= -in;
8 end else begin
9 r1 <= r1 + in;
10 r2 <= inv2 ? -(r2 - in) : (r2 - in);
11 end
12 end
13 endmodule