Merge pull request #1607 from whitequark/simplify-simplify-meminit
[yosys.git] / examples / smtbmc / demo9.v
1 module demo9;
2 (* maximize *) wire[7:0] h = $anyconst;
3 wire [7:0] i = $allconst;
4
5 wire [7:0] t0 = ((i << 8'b00000010) + 8'b00000011);
6 wire trigger = (t0 > h) && (h < 8'b00000100);
7
8 always @* begin
9 assume(trigger == 1'b1);
10 cover(1);
11 end
12 endmodule
13