2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.crhelpers.all;
10 use work.insn_helpers.all;
11 use work.ppc_fx_insns.all;
18 flush_out : out std_ulogic;
19 stall_out : out std_ulogic;
21 e_in : in Decode2ToExecute1Type;
24 f_out : out Execute1ToFetch1Type;
26 e_out : out Execute1ToWritebackType;
28 icache_inval : out std_ulogic;
29 terminate_out : out std_ulogic
33 architecture behaviour of execute1 is
34 type reg_type is record
35 e : Execute1ToWritebackType;
36 lr_update : std_ulogic;
37 next_lr : std_ulogic_vector(63 downto 0);
40 signal r, rin : reg_type;
42 signal ctrl: ctrl_t := (others => (others => '0'));
43 signal ctrl_tmp: ctrl_t := (others => (others => '0'));
45 signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
46 signal rotator_result: std_ulogic_vector(63 downto 0);
47 signal rotator_carry: std_ulogic;
48 signal logical_result: std_ulogic_vector(63 downto 0);
49 signal countzero_result: std_ulogic_vector(63 downto 0);
51 procedure set_carry(e: inout Execute1ToWritebackType;
52 carry32 : in std_ulogic;
53 carry : in std_ulogic) is
55 e.xerc.ca32 := carry32;
57 e.write_xerc_enable := '1';
60 procedure set_ov(e: inout Execute1ToWritebackType;
62 ov32 : in std_ulogic) is
69 e.write_xerc_enable := '1';
72 function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
73 ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
75 return (ca xor msb_r) and not (msb_a xor msb_b);
78 function decode_input_carry(ic : carry_in_t;
79 xerc : xer_common_t) return std_ulogic is
93 rotator_0: entity work.rotator
95 rs => e_in.read_data3,
96 ra => e_in.read_data1,
97 shift => e_in.read_data2(6 downto 0),
99 is_32bit => e_in.is_32bit,
100 right_shift => right_shift,
101 arith => e_in.is_signed,
102 clear_left => rot_clear_left,
103 clear_right => rot_clear_right,
104 result => rotator_result,
105 carry_out => rotator_carry
108 logical_0: entity work.logical
110 rs => e_in.read_data3,
111 rb => e_in.read_data2,
112 op => e_in.insn_type,
113 invert_in => e_in.invert_a,
114 invert_out => e_in.invert_out,
115 result => logical_result
118 countzero_0: entity work.zero_counter
120 rs => e_in.read_data3,
121 count_right => e_in.insn(10),
122 is_32bit => e_in.is_32bit,
123 result => countzero_result
126 execute1_0: process(clk)
128 if rising_edge(clk) then
131 assert not (r.lr_update = '1' and e_in.valid = '1')
132 report "LR update collision with valid in EX1"
134 if r.lr_update = '1' then
135 report "LR update to " & to_hstring(r.next_lr);
140 execute1_1: process(all)
141 variable v : reg_type;
142 variable a_inv : std_ulogic_vector(63 downto 0);
143 variable result : std_ulogic_vector(63 downto 0);
144 variable newcrf : std_ulogic_vector(3 downto 0);
145 variable result_with_carry : std_ulogic_vector(64 downto 0);
146 variable result_en : std_ulogic;
147 variable crnum : crnum_t;
148 variable crbit : integer range 0 to 31;
149 variable scrnum : crnum_t;
150 variable lo, hi : integer;
151 variable sh, mb, me : std_ulogic_vector(5 downto 0);
152 variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
153 variable bo, bi : std_ulogic_vector(4 downto 0);
154 variable bf, bfa : std_ulogic_vector(2 downto 0);
155 variable cr_op : std_ulogic_vector(9 downto 0);
156 variable bt, ba, bb : std_ulogic_vector(4 downto 0);
157 variable btnum, banum, bbnum : integer range 0 to 31;
158 variable crresult : std_ulogic;
159 variable l : std_ulogic;
160 variable next_nia : std_ulogic_vector(63 downto 0);
161 variable carry_32, carry_64 : std_ulogic;
163 result := (others => '0');
164 result_with_carry := (others => '0');
166 newcrf := (others => '0');
169 v.e := Execute1ToWritebackInit;
171 -- XER forwarding. To avoid having to track XER hazards, we
172 -- use the previously latched value.
174 -- If the XER was modified by a multiply or a divide, those are
175 -- single issue, we'll get the up to date value from decode2 from
176 -- the register file.
178 -- If it was modified by an instruction older than the previous
179 -- one in EX1, it will have also hit writeback and will be up
180 -- to date in decode2.
182 -- That leaves us with the case where it was updated by the previous
183 -- instruction in EX1. In that case, we can forward it back here.
185 -- This will break if we allow pipelining of multiply and divide,
186 -- but ideally, those should go via EX1 anyway and run as a state
187 -- machine from here.
189 -- One additional hazard to beware of is an XER:SO modifying instruction
190 -- in EX1 followed immediately by a store conditional. Due to our
191 -- writeback latency, the store will go down the LSU with the previous
192 -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
194 -- We will need to handle that if we ever make stcx. not single issue
196 -- We always pass a valid XER value downto writeback even when
197 -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
198 -- to work for RC instructions.
200 if r.e.write_xerc_enable = '1' then
201 v.e.xerc := r.e.xerc;
203 v.e.xerc := e_in.xerc;
209 -- FIXME: run at 512MHz not core freq
210 ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
212 terminate_out <= '0';
215 f_out <= Execute1ToFetch1TypeInit;
217 -- Next insn adder used in a couple of places
218 next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
220 -- rotator control signals
221 right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
222 rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
223 rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
225 if e_in.valid = '1' then
228 v.e.write_reg := e_in.write_reg;
229 v.e.write_len := x"8";
230 v.e.sign_extend := '0';
232 case_0: case e_in.insn_type is
235 terminate_out <= '1';
240 if e_in.invert_a = '0' then
241 a_inv := e_in.read_data1;
243 a_inv := not e_in.read_data1;
245 result_with_carry := ppc_adde(a_inv, e_in.read_data2,
246 decode_input_carry(e_in.input_carry, v.e.xerc));
247 result := result_with_carry(63 downto 0);
248 carry_32 := result(32) xor a_inv(32) xor e_in.read_data2(32);
249 carry_64 := result_with_carry(64);
250 if e_in.output_carry = '1' then
251 set_carry(v.e, carry_32, carry_64);
253 if e_in.oe = '1' then
255 calc_ov(a_inv(63), e_in.read_data2(63), carry_64, result_with_carry(63)),
256 calc_ov(a_inv(31), e_in.read_data2(31), carry_32, result_with_carry(31)));
259 when OP_AND | OP_OR | OP_XOR =>
260 result := logical_result;
263 f_out.redirect <= '1';
264 if (insn_aa(e_in.insn)) then
265 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.read_data2));
267 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
271 bo := insn_bo(e_in.insn);
272 bi := insn_bi(e_in.insn);
273 if bo(4-2) = '0' then
274 result := std_ulogic_vector(unsigned(e_in.read_data1) - 1);
276 v.e.write_reg := fast_spr_num(SPR_CTR);
278 if ppc_bc_taken(bo, bi, e_in.cr, e_in.read_data1) = 1 then
279 f_out.redirect <= '1';
280 if (insn_aa(e_in.insn)) then
281 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.read_data2));
283 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
288 -- read_data2 is target register (CTR, LR or TAR)
289 bo := insn_bo(e_in.insn);
290 bi := insn_bi(e_in.insn);
291 if bo(4-2) = '0' and e_in.insn(10) = '0' then
292 result := std_ulogic_vector(unsigned(e_in.read_data1) - 1);
294 v.e.write_reg := fast_spr_num(SPR_CTR);
296 if ppc_bc_taken(bo, bi, e_in.cr, e_in.read_data1) = 1 then
297 f_out.redirect <= '1';
298 f_out.redirect_nia <= e_in.read_data2(63 downto 2) & "00";
301 result := ppc_cmpb(e_in.read_data3, e_in.read_data2);
304 bf := insn_bf(e_in.insn);
305 l := insn_l(e_in.insn);
306 v.e.write_cr_enable := '1';
307 crnum := to_integer(unsigned(bf));
308 v.e.write_cr_mask := num_to_fxm(crnum);
312 v.e.write_cr_data(hi downto lo) := ppc_cmp(l, e_in.read_data1, e_in.read_data2, v.e.xerc.so);
315 bf := insn_bf(e_in.insn);
316 l := insn_l(e_in.insn);
317 v.e.write_cr_enable := '1';
318 crnum := to_integer(unsigned(bf));
319 v.e.write_cr_mask := num_to_fxm(crnum);
323 v.e.write_cr_data(hi downto lo) := ppc_cmpl(l, e_in.read_data1, e_in.read_data2, v.e.xerc.so);
326 result := countzero_result;
329 v.e.write_len := e_in.data_len;
330 v.e.sign_extend := '1';
331 result := e_in.read_data3;
334 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
335 if e_in.cr(31-crbit) = '1' then
336 result := e_in.read_data1;
338 result := e_in.read_data2;
342 cr_op := insn_cr(e_in.insn);
343 report "CR OP " & to_hstring(cr_op);
344 if cr_op(0) = '0' then -- MCRF
345 bf := insn_bf(e_in.insn);
346 bfa := insn_bfa(e_in.insn);
347 v.e.write_cr_enable := '1';
348 crnum := to_integer(unsigned(bf));
349 scrnum := to_integer(unsigned(bfa));
350 v.e.write_cr_mask := num_to_fxm(crnum);
355 newcrf := e_in.cr(hi downto lo);
361 v.e.write_cr_data(hi downto lo) := newcrf;
364 v.e.write_cr_enable := '1';
365 bt := insn_bt(e_in.insn);
366 ba := insn_ba(e_in.insn);
367 bb := insn_bb(e_in.insn);
368 btnum := 31 - to_integer(unsigned(bt));
369 banum := 31 - to_integer(unsigned(ba));
370 bbnum := 31 - to_integer(unsigned(bb));
371 case cr_op(8 downto 5) is
372 when "1001" => -- CREQV
373 crresult := not(e_in.cr(banum) xor e_in.cr(bbnum));
374 when "0111" => -- CRNAND
375 crresult := not(e_in.cr(banum) and e_in.cr(bbnum));
376 when "0100" => -- CRANDC
377 crresult := (e_in.cr(banum) and not e_in.cr(bbnum));
378 when "1000" => -- CRAND
379 crresult := (e_in.cr(banum) and e_in.cr(bbnum));
380 when "0001" => -- CRNOR
381 crresult := not(e_in.cr(banum) or e_in.cr(bbnum));
382 when "1101" => -- CRORC
383 crresult := (e_in.cr(banum) or not e_in.cr(bbnum));
384 when "0110" => -- CRXOR
385 crresult := (e_in.cr(banum) xor e_in.cr(bbnum));
386 when "1110" => -- CROR
387 crresult := (e_in.cr(banum) or e_in.cr(bbnum));
391 v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
392 for i in 0 to 31 loop
394 v.e.write_cr_data(i) := crresult;
396 v.e.write_cr_data(i) := e_in.cr(i);
401 if is_fast_spr(e_in.read_reg1) then
402 result := e_in.read_data1;
403 if decode_spr_num(e_in.insn) = SPR_XER then
404 -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
405 result(63 downto 32) := (others => '0');
406 result(63-32) := v.e.xerc.so;
407 result(63-33) := v.e.xerc.ov;
408 result(63-34) := v.e.xerc.ca;
409 result(63-35 downto 63-43) := "000000000";
410 result(63-44) := v.e.xerc.ov32;
411 result(63-45) := v.e.xerc.ca32;
414 case decode_spr_num(e_in.insn) is
418 result := (others => '0');
423 if e_in.insn(20) = '0' then
425 result := x"00000000" & e_in.cr;
428 crnum := fxm_to_num(insn_fxm(e_in.insn));
429 result := (others => '0');
434 result(hi downto lo) := e_in.cr(hi downto lo);
440 v.e.write_cr_enable := '1';
441 if e_in.insn(20) = '0' then
443 v.e.write_cr_mask := insn_fxm(e_in.insn);
445 -- mtocrf: We require one hot priority encoding here
446 crnum := fxm_to_num(insn_fxm(e_in.insn));
447 v.e.write_cr_mask := num_to_fxm(crnum);
449 v.e.write_cr_data := e_in.read_data3(31 downto 0);
451 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
452 "=" & to_hstring(e_in.read_data3);
453 if is_fast_spr(e_in.write_reg) then
454 result := e_in.read_data3;
456 if decode_spr_num(e_in.insn) = SPR_XER then
457 v.e.xerc.so := e_in.read_data3(63-32);
458 v.e.xerc.ov := e_in.read_data3(63-33);
459 v.e.xerc.ca := e_in.read_data3(63-34);
460 v.e.xerc.ov32 := e_in.read_data3(63-44);
461 v.e.xerc.ca32 := e_in.read_data3(63-45);
462 v.e.write_xerc_enable := '1';
465 -- TODO: Implement slow SPRs
466 -- case decode_spr_num(e_in.insn) is
471 result := ppc_popcntb(e_in.read_data3);
474 result := ppc_popcntw(e_in.read_data3);
477 result := ppc_popcntd(e_in.read_data3);
480 result := ppc_prtyd(e_in.read_data3);
483 result := ppc_prtyw(e_in.read_data3);
485 when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR =>
486 result := rotator_result;
487 if e_in.output_carry = '1' then
488 set_carry(v.e, rotator_carry, rotator_carry);
491 when OP_SIM_CONFIG =>
492 -- bit 0 was used to select the microwatt console, which
493 -- we no longer support.
494 result := x"0000000000000000";
498 -- Keep our test cases happy for now, ignore trap instructions
499 report "OP_TDI FIXME";
502 f_out.redirect <= '1';
503 f_out.redirect_nia <= next_nia;
509 terminate_out <= '1';
513 -- Update LR on the next cycle after a branch link
515 -- WARNING: The LR update isn't tracked by our hazard tracker. This
516 -- will work (well I hope) because it only happens on branches
517 -- which will flush all decoded instructions. By the time
518 -- fetch catches up, we'll have the new LR. This will
519 -- *not* work properly however if we have a branch predictor,
520 -- in which case the solution would probably be to keep a
521 -- local cache of the updated LR in execute1 (flushed on
522 -- exceptions) that is used instead of the value from
523 -- decode when its content is valid.
524 if e_in.lr = '1' then
526 v.next_lr := next_nia;
528 report "Delayed LR update to " & to_hstring(next_nia);
531 elsif r.lr_update = '1' then
534 v.e.write_reg := fast_spr_num(SPR_LR);
535 v.e.write_len := x"8";
536 v.e.sign_extend := '0';
540 v.e.write_data := result;
541 v.e.write_enable := result_en;
542 v.e.rc := e_in.rc and e_in.valid;
550 flush_out <= f_out.redirect;
552 end architecture behaviour;