2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.crhelpers.all;
10 use work.insn_helpers.all;
11 use work.ppc_fx_insns.all;
15 EX1_BYPASS : boolean := true
22 flush_out : out std_ulogic;
23 stall_out : out std_ulogic;
25 e_in : in Decode2ToExecute1Type;
28 l_out : out Execute1ToLoadstore1Type;
29 f_out : out Execute1ToFetch1Type;
31 e_out : out Execute1ToWritebackType;
33 icache_inval : out std_ulogic;
34 terminate_out : out std_ulogic
38 architecture behaviour of execute1 is
39 type reg_type is record
40 e : Execute1ToWritebackType;
41 lr_update : std_ulogic;
42 next_lr : std_ulogic_vector(63 downto 0);
43 mul_in_progress : std_ulogic;
44 div_in_progress : std_ulogic;
45 cntz_in_progress : std_ulogic;
46 slow_op_dest : gpr_index_t;
47 slow_op_rc : std_ulogic;
48 slow_op_oe : std_ulogic;
49 slow_op_xerc : xer_common_t;
51 constant reg_type_init : reg_type :=
52 (e => Execute1ToWritebackInit, lr_update => '0',
53 mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
54 slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
55 others => (others => '0'));
57 signal r, rin : reg_type;
59 signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
61 signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
62 signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
63 signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
64 signal rotator_result: std_ulogic_vector(63 downto 0);
65 signal rotator_carry: std_ulogic;
66 signal logical_result: std_ulogic_vector(63 downto 0);
67 signal countzero_result: std_ulogic_vector(63 downto 0);
68 signal popcnt_result: std_ulogic_vector(63 downto 0);
69 signal parity_result: std_ulogic_vector(63 downto 0);
72 signal x_to_multiply: Execute1ToMultiplyType;
73 signal multiply_to_x: MultiplyToExecute1Type;
76 signal x_to_divider: Execute1ToDividerType;
77 signal divider_to_x: DividerToExecute1Type;
79 type privilege_level is (USER, SUPER);
80 type op_privilege_array is array(insn_type_t) of privilege_level;
81 constant op_privilege: op_privilege_array := (
89 function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
92 if op_privilege(op) = SUPER then
94 elsif op = OP_MFSPR or op = OP_MTSPR then
95 return insn(20) = '1';
101 procedure set_carry(e: inout Execute1ToWritebackType;
102 carry32 : in std_ulogic;
103 carry : in std_ulogic) is
105 e.xerc.ca32 := carry32;
107 e.write_xerc_enable := '1';
110 procedure set_ov(e: inout Execute1ToWritebackType;
112 ov32 : in std_ulogic) is
119 e.write_xerc_enable := '1';
122 function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
123 ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
125 return (ca xor msb_r) and not (msb_a xor msb_b);
128 function decode_input_carry(ic : carry_in_t;
129 xerc : xer_common_t) return std_ulogic is
141 function msr_copy(msr: std_ulogic_vector(63 downto 0))
142 return std_ulogic_vector is
143 variable msr_out: std_ulogic_vector(63 downto 0);
146 -- Defined MSR bits are classified as either full func-
147 -- tion or partial function. Full function MSR bits are
148 -- saved in SRR1 or HSRR1 when an interrupt other
149 -- than a System Call Vectored interrupt occurs and
150 -- restored by rfscv, rfid, or hrfid, while partial func-
151 -- tion MSR bits are not saved or restored.
152 -- Full function MSR bits lie in the range 0:32, 37:41, and
153 -- 48:63, and partial function MSR bits lie in the range
154 -- 33:36 and 42:47. (Note this is IBM bit numbering).
155 msr_out := (others => '0');
156 msr_out(63 downto 31) := msr(63 downto 31);
157 msr_out(26 downto 22) := msr(26 downto 22);
158 msr_out(15 downto 0) := msr(15 downto 0);
164 rotator_0: entity work.rotator
168 shift => b_in(6 downto 0),
170 is_32bit => e_in.is_32bit,
171 right_shift => right_shift,
172 arith => e_in.is_signed,
173 clear_left => rot_clear_left,
174 clear_right => rot_clear_right,
175 result => rotator_result,
176 carry_out => rotator_carry
179 logical_0: entity work.logical
183 op => e_in.insn_type,
184 invert_in => e_in.invert_a,
185 invert_out => e_in.invert_out,
186 result => logical_result,
187 datalen => e_in.data_len,
188 popcnt => popcnt_result,
189 parity => parity_result
192 countzero_0: entity work.zero_counter
196 count_right => e_in.insn(10),
197 is_32bit => e_in.is_32bit,
198 result => countzero_result
201 multiply_0: entity work.multiply
204 m_in => x_to_multiply,
205 m_out => multiply_to_x
208 divider_0: entity work.divider
212 d_in => x_to_divider,
213 d_out => divider_to_x
216 a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
217 b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
218 c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
220 execute1_0: process(clk)
222 if rising_edge(clk) then
225 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
226 ctrl.irq_state <= WRITE_SRR0;
230 assert not (r.lr_update = '1' and e_in.valid = '1')
231 report "LR update collision with valid in EX1"
233 if r.lr_update = '1' then
234 report "LR update to " & to_hstring(r.next_lr);
240 execute1_1: process(all)
241 variable v : reg_type;
242 variable a_inv : std_ulogic_vector(63 downto 0);
243 variable result : std_ulogic_vector(63 downto 0);
244 variable newcrf : std_ulogic_vector(3 downto 0);
245 variable result_with_carry : std_ulogic_vector(64 downto 0);
246 variable result_en : std_ulogic;
247 variable crnum : crnum_t;
248 variable crbit : integer range 0 to 31;
249 variable scrnum : crnum_t;
250 variable lo, hi : integer;
251 variable sh, mb, me : std_ulogic_vector(5 downto 0);
252 variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
253 variable bo, bi : std_ulogic_vector(4 downto 0);
254 variable bf, bfa : std_ulogic_vector(2 downto 0);
255 variable cr_op : std_ulogic_vector(9 downto 0);
256 variable cr_operands : std_ulogic_vector(1 downto 0);
257 variable bt, ba, bb : std_ulogic_vector(4 downto 0);
258 variable btnum, banum, bbnum : integer range 0 to 31;
259 variable crresult : std_ulogic;
260 variable l : std_ulogic;
261 variable next_nia : std_ulogic_vector(63 downto 0);
262 variable carry_32, carry_64 : std_ulogic;
263 variable sign1, sign2 : std_ulogic;
264 variable abs1, abs2 : signed(63 downto 0);
265 variable overflow : std_ulogic;
266 variable negative : std_ulogic;
267 variable zerohi, zerolo : std_ulogic;
268 variable msb_a, msb_b : std_ulogic;
269 variable a_lt : std_ulogic;
270 variable lv : Execute1ToLoadstore1Type;
271 variable irq_valid : std_ulogic;
272 variable exception : std_ulogic;
273 variable exception_nextpc : std_ulogic;
274 variable trapval : std_ulogic_vector(4 downto 0);
275 variable illegal : std_ulogic;
277 result := (others => '0');
278 result_with_carry := (others => '0');
280 newcrf := (others => '0');
283 v.e := Execute1ToWritebackInit;
284 lv := Execute1ToLoadstore1Init;
286 -- XER forwarding. To avoid having to track XER hazards, we
287 -- use the previously latched value.
289 -- If the XER was modified by a multiply or a divide, those are
290 -- single issue, we'll get the up to date value from decode2 from
291 -- the register file.
293 -- If it was modified by an instruction older than the previous
294 -- one in EX1, it will have also hit writeback and will be up
295 -- to date in decode2.
297 -- That leaves us with the case where it was updated by the previous
298 -- instruction in EX1. In that case, we can forward it back here.
300 -- This will break if we allow pipelining of multiply and divide,
301 -- but ideally, those should go via EX1 anyway and run as a state
302 -- machine from here.
304 -- One additional hazard to beware of is an XER:SO modifying instruction
305 -- in EX1 followed immediately by a store conditional. Due to our
306 -- writeback latency, the store will go down the LSU with the previous
307 -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
309 -- We will need to handle that if we ever make stcx. not single issue
311 -- We always pass a valid XER value downto writeback even when
312 -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
313 -- to work for RC instructions.
315 if r.e.write_xerc_enable = '1' then
316 v.e.xerc := r.e.xerc;
318 v.e.xerc := e_in.xerc;
322 v.mul_in_progress := '0';
323 v.div_in_progress := '0';
324 v.cntz_in_progress := '0';
326 -- signals to multiply unit
327 x_to_multiply <= Execute1ToMultiplyInit;
328 x_to_multiply.insn_type <= e_in.insn_type;
329 x_to_multiply.is_32bit <= e_in.is_32bit;
331 if e_in.is_32bit = '1' then
332 if e_in.is_signed = '1' then
333 x_to_multiply.data1 <= (others => a_in(31));
334 x_to_multiply.data1(31 downto 0) <= a_in(31 downto 0);
335 x_to_multiply.data2 <= (others => b_in(31));
336 x_to_multiply.data2(31 downto 0) <= b_in(31 downto 0);
338 x_to_multiply.data1 <= '0' & x"00000000" & a_in(31 downto 0);
339 x_to_multiply.data2 <= '0' & x"00000000" & b_in(31 downto 0);
342 if e_in.is_signed = '1' then
343 x_to_multiply.data1 <= a_in(63) & a_in;
344 x_to_multiply.data2 <= b_in(63) & b_in;
346 x_to_multiply.data1 <= '0' & a_in;
347 x_to_multiply.data2 <= '0' & b_in;
351 -- signals to divide unit
354 if e_in.is_signed = '1' then
355 if e_in.is_32bit = '1' then
363 -- take absolute values
365 abs1 := signed(a_in);
367 abs1 := - signed(a_in);
370 abs2 := signed(b_in);
372 abs2 := - signed(b_in);
375 x_to_divider <= Execute1ToDividerInit;
376 x_to_divider.is_signed <= e_in.is_signed;
377 x_to_divider.is_32bit <= e_in.is_32bit;
378 if e_in.insn_type = OP_MOD then
379 x_to_divider.is_modulus <= '1';
381 x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
382 if e_in.is_32bit = '0' then
384 if e_in.insn_type = OP_DIVE then
385 x_to_divider.is_extended <= '1';
387 x_to_divider.dividend <= std_ulogic_vector(abs1);
388 x_to_divider.divisor <= std_ulogic_vector(abs2);
391 x_to_divider.is_extended <= '0';
392 if e_in.insn_type = OP_DIVE then -- extended forms
393 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
395 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
397 x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
401 -- FIXME: run at 512MHz not core freq
402 ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
403 ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
406 if ctrl.msr(MSR_EE) = '1' and ctrl.dec(63) = '1' then
411 terminate_out <= '0';
414 f_out <= Execute1ToFetch1TypeInit;
416 -- Next insn adder used in a couple of places
417 next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
419 -- rotator control signals
420 right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
421 rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
422 rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
424 ctrl_tmp.irq_state <= WRITE_SRR0;
427 exception_nextpc := '0';
428 v.e.exc_write_enable := '0';
429 v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
430 v.e.exc_write_data := e_in.nia;
432 if ctrl.irq_state = WRITE_SRR1 then
433 v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
434 v.e.exc_write_data := ctrl.srr1;
435 v.e.exc_write_enable := '1';
436 ctrl_tmp.msr(MSR_SF) <= '1';
437 ctrl_tmp.msr(MSR_EE) <= '0';
438 ctrl_tmp.msr(MSR_PR) <= '0';
439 ctrl_tmp.msr(MSR_IR) <= '0';
440 ctrl_tmp.msr(MSR_DR) <= '0';
441 ctrl_tmp.msr(MSR_RI) <= '0';
442 ctrl_tmp.msr(MSR_LE) <= '1';
443 f_out.redirect <= '1';
444 f_out.redirect_nia <= ctrl.irq_nia;
445 v.e.valid := e_in.valid;
446 report "Writing SRR1: " & to_hstring(ctrl.srr1);
448 elsif irq_valid = '1' then
449 -- we need two cycles to write srr0 and 1
450 -- will need more when we have to write DSISR, DAR and HIER
451 -- Don't deliver the interrupt until we have a valid instruction
452 -- coming in, so we have a valid NIA to put in SRR0.
453 exception := e_in.valid;
454 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
455 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
457 elsif e_in.valid = '1' and ctrl.msr(MSR_PR) = '1' and
458 instr_is_privileged(e_in.insn_type, e_in.insn) then
459 -- generate a program interrupt
461 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
462 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
463 -- set bit 45 to indicate privileged instruction type interrupt
464 ctrl_tmp.srr1(63 - 45) <= '1';
465 report "privileged instruction";
467 elsif e_in.valid = '1' and e_in.unit = ALU then
470 v.e.write_reg := e_in.write_reg;
471 v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
472 v.slow_op_rc := e_in.rc;
473 v.slow_op_oe := e_in.oe;
474 v.slow_op_xerc := v.e.xerc;
476 case_0: case e_in.insn_type is
479 -- we need two cycles to write srr0 and 1
480 -- will need more when we have to write DSISR, DAR and HIER
483 -- check bit 1 of the instruction is 1 so we know this is sc;
484 -- 0 would mean scv, so generate an illegal instruction interrupt
485 -- we need two cycles to write srr0 and 1
486 -- will need more when we have to write DSISR, DAR and HIER
487 if e_in.insn(1) = '1' then
489 exception_nextpc := '1';
490 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
491 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
497 -- check bits 1-10 of the instruction to make sure it's attn
498 -- if not then it is illegal
499 if e_in.insn(10 downto 1) = "0100000000" then
500 terminate_out <= '1';
507 when OP_ADD | OP_CMP | OP_TRAP =>
508 if e_in.invert_a = '0' then
513 result_with_carry := ppc_adde(a_inv, b_in,
514 decode_input_carry(e_in.input_carry, v.e.xerc));
515 result := result_with_carry(63 downto 0);
516 carry_32 := result(32) xor a_inv(32) xor b_in(32);
517 carry_64 := result_with_carry(64);
518 if e_in.insn_type = OP_ADD then
519 if e_in.output_carry = '1' then
520 set_carry(v.e, carry_32, carry_64);
522 if e_in.oe = '1' then
524 calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
525 calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
529 -- trap, CMP and CMPL instructions
530 -- Note, we have done RB - RA, not RA - RB
531 if e_in.insn_type = OP_CMP then
532 l := insn_l(e_in.insn);
534 l := not e_in.is_32bit;
536 zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
537 zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
538 if zerolo = '1' and (l = '0' or zerohi = '1') then
551 if msb_a /= msb_b then
552 -- Subtraction might overflow, but
553 -- comparison is clear from MSB difference.
554 -- for signed, 0 is greater; for unsigned, 1 is greater
555 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
557 -- Subtraction cannot overflow since MSBs are equal.
558 -- carry = 1 indicates RA is smaller (signed or unsigned)
559 a_lt := (not l and carry_32) or (l and carry_64);
560 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
563 if e_in.insn_type = OP_CMP then
564 if e_in.is_signed = '1' then
565 newcrf := trapval(4 downto 2) & v.e.xerc.so;
567 newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
569 bf := insn_bf(e_in.insn);
570 crnum := to_integer(unsigned(bf));
571 v.e.write_cr_enable := '1';
572 v.e.write_cr_mask := num_to_fxm(crnum);
576 v.e.write_cr_data(hi downto lo) := newcrf;
579 -- trap instructions (tw, twi, td, tdi)
580 if or (trapval and insn_to(e_in.insn)) = '1' then
581 -- generate trap-type program interrupt
583 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
584 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
585 -- set bit 46 to say trap occurred
586 ctrl_tmp.srr1(63 - 46) <= '1';
591 when OP_AND | OP_OR | OP_XOR =>
592 result := logical_result;
595 f_out.redirect <= '1';
596 if (insn_aa(e_in.insn)) then
597 f_out.redirect_nia <= b_in;
599 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
603 bo := insn_bo(e_in.insn);
604 bi := insn_bi(e_in.insn);
605 if bo(4-2) = '0' then
606 result := std_ulogic_vector(unsigned(a_in) - 1);
608 v.e.write_reg := fast_spr_num(SPR_CTR);
610 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
611 f_out.redirect <= '1';
612 if (insn_aa(e_in.insn)) then
613 f_out.redirect_nia <= b_in;
615 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
620 -- read_data2 is target register (CTR, LR or TAR)
621 bo := insn_bo(e_in.insn);
622 bi := insn_bi(e_in.insn);
623 if bo(4-2) = '0' and e_in.insn(10) = '0' then
624 result := std_ulogic_vector(unsigned(a_in) - 1);
626 v.e.write_reg := fast_spr_num(SPR_CTR);
628 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
629 f_out.redirect <= '1';
630 f_out.redirect_nia <= b_in(63 downto 2) & "00";
634 f_out.redirect <= '1';
635 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
636 -- Can't use msr_copy here because the partial function MSR
637 -- bits should be left unchanged, not zeroed.
638 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
639 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
640 ctrl_tmp.msr(15 downto 0) <= b_in(15 downto 0);
641 if b_in(MSR_PR) = '1' then
642 ctrl_tmp.msr(MSR_EE) <= '1';
643 ctrl_tmp.msr(MSR_IR) <= '1';
644 ctrl_tmp.msr(MSR_DR) <= '1';
648 result := ppc_cmpb(c_in, b_in);
652 v.cntz_in_progress := '1';
655 -- note data_len is a 1-hot encoding
656 negative := (e_in.data_len(0) and c_in(7)) or
657 (e_in.data_len(1) and c_in(15)) or
658 (e_in.data_len(2) and c_in(31));
659 result := (others => negative);
660 if e_in.data_len(2) = '1' then
661 result(31 downto 16) := c_in(31 downto 16);
663 if e_in.data_len(2) = '1' or e_in.data_len(1) = '1' then
664 result(15 downto 8) := c_in(15 downto 8);
666 result(7 downto 0) := c_in(7 downto 0);
669 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
670 if e_in.cr(31-crbit) = '1' then
677 cr_op := insn_cr(e_in.insn);
678 report "CR OP " & to_hstring(cr_op);
679 if cr_op(0) = '0' then -- MCRF
680 bf := insn_bf(e_in.insn);
681 bfa := insn_bfa(e_in.insn);
682 v.e.write_cr_enable := '1';
683 crnum := to_integer(unsigned(bf));
684 scrnum := to_integer(unsigned(bfa));
685 v.e.write_cr_mask := num_to_fxm(crnum);
690 newcrf := e_in.cr(hi downto lo);
696 v.e.write_cr_data(hi downto lo) := newcrf;
699 v.e.write_cr_enable := '1';
700 bt := insn_bt(e_in.insn);
701 ba := insn_ba(e_in.insn);
702 bb := insn_bb(e_in.insn);
703 btnum := 31 - to_integer(unsigned(bt));
704 banum := 31 - to_integer(unsigned(ba));
705 bbnum := 31 - to_integer(unsigned(bb));
706 -- Bits 5-8 of cr_op give the truth table of the requested
708 cr_operands := e_in.cr(banum) & e_in.cr(bbnum);
709 crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
710 v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
711 for i in 0 to 31 loop
713 v.e.write_cr_data(i) := crresult;
715 v.e.write_cr_data(i) := e_in.cr(i);
723 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
724 "=" & to_hstring(a_in);
725 if is_fast_spr(e_in.read_reg1) then
727 if decode_spr_num(e_in.insn) = SPR_XER then
728 -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
729 result(63 downto 32) := (others => '0');
730 result(63-32) := v.e.xerc.so;
731 result(63-33) := v.e.xerc.ov;
732 result(63-34) := v.e.xerc.ca;
733 result(63-35 downto 63-43) := "000000000";
734 result(63-44) := v.e.xerc.ov32;
735 result(63-45) := v.e.xerc.ca32;
738 case decode_spr_num(e_in.insn) is
744 result := (others => '0');
749 if e_in.insn(20) = '0' then
751 result := x"00000000" & e_in.cr;
754 crnum := fxm_to_num(insn_fxm(e_in.insn));
755 result := (others => '0');
760 result(hi downto lo) := e_in.cr(hi downto lo);
766 v.e.write_cr_enable := '1';
767 if e_in.insn(20) = '0' then
769 v.e.write_cr_mask := insn_fxm(e_in.insn);
771 -- mtocrf: We require one hot priority encoding here
772 crnum := fxm_to_num(insn_fxm(e_in.insn));
773 v.e.write_cr_mask := num_to_fxm(crnum);
775 v.e.write_cr_data := c_in(31 downto 0);
777 if e_in.insn(16) = '1' then
778 -- just update EE and RI
779 ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
780 ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
782 -- Architecture says to leave out bits 3 (HV), 51 (ME)
783 -- and 63 (LE) (IBM bit numbering)
784 ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
785 ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
786 ctrl_tmp.msr(11 downto 1) <= c_in(11 downto 1);
787 if c_in(MSR_PR) = '1' then
788 ctrl_tmp.msr(MSR_EE) <= '1';
789 ctrl_tmp.msr(MSR_IR) <= '1';
790 ctrl_tmp.msr(MSR_DR) <= '1';
794 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
795 "=" & to_hstring(c_in);
796 if is_fast_spr(e_in.write_reg) then
799 if decode_spr_num(e_in.insn) = SPR_XER then
800 v.e.xerc.so := c_in(63-32);
801 v.e.xerc.ov := c_in(63-33);
802 v.e.xerc.ca := c_in(63-34);
803 v.e.xerc.ov32 := c_in(63-44);
804 v.e.xerc.ca32 := c_in(63-45);
805 v.e.write_xerc_enable := '1';
809 case decode_spr_num(e_in.insn) is
811 ctrl_tmp.dec <= c_in;
816 result := popcnt_result;
819 result := parity_result;
821 when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR =>
822 result := rotator_result;
823 if e_in.output_carry = '1' then
824 set_carry(v.e, rotator_carry, rotator_carry);
829 f_out.redirect <= '1';
830 f_out.redirect_nia <= next_nia;
835 when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
837 v.mul_in_progress := '1';
839 x_to_multiply.valid <= '1';
841 when OP_DIV | OP_DIVE | OP_MOD =>
843 v.div_in_progress := '1';
845 x_to_divider.valid <= '1';
848 terminate_out <= '1';
852 v.e.rc := e_in.rc and e_in.valid;
854 -- Update LR on the next cycle after a branch link
856 -- WARNING: The LR update isn't tracked by our hazard tracker. This
857 -- will work (well I hope) because it only happens on branches
858 -- which will flush all decoded instructions. By the time
859 -- fetch catches up, we'll have the new LR. This will
860 -- *not* work properly however if we have a branch predictor,
861 -- in which case the solution would probably be to keep a
862 -- local cache of the updated LR in execute1 (flushed on
863 -- exceptions) that is used instead of the value from
864 -- decode when its content is valid.
865 if e_in.lr = '1' then
867 v.next_lr := next_nia;
869 report "Delayed LR update to " & to_hstring(next_nia);
873 elsif e_in.valid = '1' then
874 -- instruction for other units, i.e. LDST
876 if e_in.unit = LDST then
880 elsif r.lr_update = '1' then
883 v.e.write_reg := fast_spr_num(SPR_LR);
885 elsif r.cntz_in_progress = '1' then
886 -- cnt[lt]z always takes two cycles
887 result := countzero_result;
889 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
890 v.e.rc := v.slow_op_rc;
891 v.e.xerc := v.slow_op_xerc;
893 elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
894 if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
895 (r.div_in_progress = '1' and divider_to_x.valid = '1') then
896 if r.mul_in_progress = '1' then
897 result := multiply_to_x.write_reg_data;
898 overflow := multiply_to_x.overflow;
900 result := divider_to_x.write_reg_data;
901 overflow := divider_to_x.overflow;
904 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
905 v.e.rc := v.slow_op_rc;
906 v.e.xerc := v.slow_op_xerc;
907 v.e.write_xerc_enable := v.slow_op_oe;
908 -- We must test oe because the RC update code in writeback
909 -- will use the xerc value to set CR0:SO so we must not clobber
910 -- xerc if OE wasn't set.
911 if v.slow_op_oe = '1' then
912 v.e.xerc.ov := overflow;
913 v.e.xerc.ov32 := overflow;
914 v.e.xerc.so := v.slow_op_xerc.so or overflow;
919 v.mul_in_progress := r.mul_in_progress;
920 v.div_in_progress := r.div_in_progress;
924 if illegal = '1' then
926 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
927 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
928 -- Since we aren't doing Hypervisor emulation assist (0xe40) we
929 -- set bit 44 to indicate we have an illegal
930 ctrl_tmp.srr1(63 - 44) <= '1';
933 if exception = '1' then
934 v.e.exc_write_enable := '1';
935 if exception_nextpc = '1' then
936 v.e.exc_write_data := next_nia;
938 ctrl_tmp.irq_state <= WRITE_SRR1;
942 v.e.write_data := result;
943 v.e.write_enable := result_en;
945 -- Outputs to loadstore1 (async)
946 lv.op := e_in.insn_type;
950 lv.write_reg := gspr_to_gpr(e_in.write_reg);
951 lv.length := e_in.data_len;
952 lv.byte_reverse := e_in.byte_reverse;
953 lv.sign_extend := e_in.sign_extend;
954 lv.update := e_in.update;
955 lv.update_reg := gspr_to_gpr(e_in.read_reg1);
957 lv.reserve := e_in.reserve;
959 -- decode l*cix and st*cix instructions here
960 if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
961 e_in.insn(5 downto 1) = "10101" then
972 flush_out <= f_out.redirect;
974 end architecture behaviour;