Generalize the mul_32bit and mul_signed fields of decode_rom_t
[microwatt.git] / execute1.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 library work;
6 use work.decode_types.all;
7 use work.common.all;
8 use work.helpers.all;
9 use work.crhelpers.all;
10 use work.insn_helpers.all;
11 use work.ppc_fx_insns.all;
12
13 entity execute1 is
14 generic (
15 SIM : boolean := false
16 );
17 port (
18 clk : in std_logic;
19
20 -- asynchronous
21 flush_out : out std_ulogic;
22
23 e_in : in Decode2ToExecute1Type;
24
25 -- asynchronous
26 f_out : out Execute1ToFetch1Type;
27
28 e_out : out Execute1ToExecute2Type;
29
30 terminate_out : out std_ulogic
31 );
32 end entity execute1;
33
34 architecture behaviour of execute1 is
35 type reg_type is record
36 --f : Execute1ToFetch1Type;
37 e : Execute1ToExecute2Type;
38 end record;
39
40 signal r, rin : reg_type;
41
42 signal ctrl: ctrl_t := (carry => '0', others => (others => '0'));
43 signal ctrl_tmp: ctrl_t := (carry => '0', others => (others => '0'));
44
45 function decode_input_carry (carry_sel : carry_in_t; ca_in : std_ulogic) return std_ulogic is
46 begin
47 case carry_sel is
48 when ZERO =>
49 return '0';
50 when CA =>
51 return ca_in;
52 when ONE =>
53 return '1';
54 end case;
55 end;
56 begin
57 execute1_0: process(clk)
58 begin
59 if rising_edge(clk) then
60 r <= rin;
61 ctrl <= ctrl_tmp;
62 end if;
63 end process;
64
65 execute1_1: process(all)
66 variable v : reg_type;
67 variable a_inv : std_ulogic_vector(63 downto 0);
68 variable result : std_ulogic_vector(63 downto 0);
69 variable newcrf : std_ulogic_vector(3 downto 0);
70 variable result_with_carry : std_ulogic_vector(64 downto 0);
71 variable result_en : integer;
72 variable crnum : integer;
73 variable scrnum : integer;
74 variable lo, hi : integer;
75 variable sh, mb, me : std_ulogic_vector(5 downto 0);
76 variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
77 variable bo, bi : std_ulogic_vector(4 downto 0);
78 variable bf, bfa : std_ulogic_vector(2 downto 0);
79 variable l : std_ulogic;
80 begin
81 result := (others => '0');
82 result_with_carry := (others => '0');
83 result_en := 0;
84
85 v := r;
86 v.e := Execute1ToExecute2Init;
87 --v.f := Execute1ToFetch1TypeInit;
88
89 ctrl_tmp <= ctrl;
90 -- FIXME: run at 512MHz not core freq
91 ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
92
93 terminate_out <= '0';
94 f_out <= Execute1ToFetch1TypeInit;
95
96 if e_in.valid = '1' then
97
98 v.e.valid := '1';
99 v.e.write_reg := e_in.write_reg;
100
101 case_0: case e_in.insn_type is
102
103 when OP_ILLEGAL =>
104 terminate_out <= '1';
105 report "illegal";
106 when OP_NOP =>
107 -- Do nothing
108 when OP_ADD =>
109 if e_in.invert_a = '0' then
110 a_inv := e_in.read_data1;
111 else
112 a_inv := not e_in.read_data1;
113 end if;
114 result_with_carry := ppc_adde(a_inv, e_in.read_data2, decode_input_carry(e_in.input_carry, ctrl.carry));
115 result := result_with_carry(63 downto 0);
116 if e_in.output_carry then
117 ctrl_tmp.carry <= result_with_carry(64);
118 end if;
119 result_en := 1;
120 when OP_AND =>
121 result := ppc_and(e_in.read_data3, e_in.read_data2);
122 result_en := 1;
123 when OP_ANDC =>
124 result := ppc_andc(e_in.read_data3, e_in.read_data2);
125 result_en := 1;
126 when OP_B =>
127 f_out.redirect <= '1';
128 if (insn_aa(e_in.insn)) then
129 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.read_data2));
130 else
131 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
132 end if;
133 when OP_BC =>
134 bo := insn_bo(e_in.insn);
135 bi := insn_bi(e_in.insn);
136 if bo(4-2) = '0' then
137 ctrl_tmp.ctr <= std_ulogic_vector(unsigned(ctrl.ctr) - 1);
138 end if;
139 if ppc_bc_taken(bo, bi, e_in.cr, ctrl.ctr) = 1 then
140 f_out.redirect <= '1';
141 if (insn_aa(e_in.insn)) then
142 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.read_data2));
143 else
144 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(e_in.read_data2));
145 end if;
146 end if;
147 when OP_BCREG =>
148 -- bits 10 and 6 distinguish between bclr, bcctr and bctar
149 bo := insn_bo(e_in.insn);
150 bi := insn_bi(e_in.insn);
151 if bo(4-2) = '0' and e_in.insn(10) = '0' then
152 ctrl_tmp.ctr <= std_ulogic_vector(unsigned(ctrl.ctr) - 1);
153 end if;
154 if ppc_bc_taken(bo, bi, e_in.cr, ctrl.ctr) = 1 then
155 f_out.redirect <= '1';
156 if e_in.insn(10) = '0' then
157 f_out.redirect_nia <= ctrl.lr(63 downto 2) & "00";
158 else
159 f_out.redirect_nia <= ctrl.ctr(63 downto 2) & "00";
160 end if;
161 end if;
162 when OP_CMPB =>
163 result := ppc_cmpb(e_in.read_data3, e_in.read_data2);
164 result_en := 1;
165 when OP_CMP =>
166 bf := insn_bf(e_in.insn);
167 l := insn_l(e_in.insn);
168 v.e.write_cr_enable := '1';
169 crnum := to_integer(unsigned(bf));
170 v.e.write_cr_mask := num_to_fxm(crnum);
171 for i in 0 to 7 loop
172 lo := i*4;
173 hi := lo + 3;
174 v.e.write_cr_data(hi downto lo) := ppc_cmp(l, e_in.read_data1, e_in.read_data2);
175 end loop;
176 when OP_CMPL =>
177 bf := insn_bf(e_in.insn);
178 l := insn_l(e_in.insn);
179 v.e.write_cr_enable := '1';
180 crnum := to_integer(unsigned(bf));
181 v.e.write_cr_mask := num_to_fxm(crnum);
182 for i in 0 to 7 loop
183 lo := i*4;
184 hi := lo + 3;
185 v.e.write_cr_data(hi downto lo) := ppc_cmpl(l, e_in.read_data1, e_in.read_data2);
186 end loop;
187 when OP_CNTLZW =>
188 result := ppc_cntlzw(e_in.read_data3);
189 result_en := 1;
190 when OP_CNTTZW =>
191 result := ppc_cnttzw(e_in.read_data3);
192 result_en := 1;
193 when OP_CNTLZD =>
194 result := ppc_cntlzd(e_in.read_data3);
195 result_en := 1;
196 when OP_CNTTZD =>
197 result := ppc_cnttzd(e_in.read_data3);
198 result_en := 1;
199 when OP_EXTSB =>
200 result := ppc_extsb(e_in.read_data3);
201 result_en := 1;
202 when OP_EXTSH =>
203 result := ppc_extsh(e_in.read_data3);
204 result_en := 1;
205 when OP_EXTSW =>
206 result := ppc_extsw(e_in.read_data3);
207 result_en := 1;
208 when OP_EQV =>
209 result := ppc_eqv(e_in.read_data3, e_in.read_data2);
210 result_en := 1;
211 when OP_ISEL =>
212 crnum := to_integer(unsigned(insn_bc(e_in.insn)));
213 if e_in.cr(31-crnum) = '1' then
214 result := e_in.read_data1;
215 else
216 result := e_in.read_data2;
217 end if;
218 result_en := 1;
219 when OP_MCRF =>
220 bf := insn_bf(e_in.insn);
221 bfa := insn_bfa(e_in.insn);
222 v.e.write_cr_enable := '1';
223 crnum := to_integer(unsigned(bf));
224 scrnum := to_integer(unsigned(bfa));
225 v.e.write_cr_mask := num_to_fxm(crnum);
226 for i in 0 to 7 loop
227 lo := (7-i)*4;
228 hi := lo + 3;
229 if i = scrnum then
230 newcrf := e_in.cr(hi downto lo);
231 end if;
232 end loop;
233 for i in 0 to 7 loop
234 lo := i*4;
235 hi := lo + 3;
236 v.e.write_cr_data(hi downto lo) := newcrf;
237 end loop;
238 when OP_MFSPR =>
239 if std_match(e_in.insn(20 downto 11), "0100100000") then
240 result := ctrl.ctr;
241 result_en := 1;
242 elsif std_match(e_in.insn(20 downto 11), "0100000000") then
243 result := ctrl.lr;
244 result_en := 1;
245 elsif std_match(e_in.insn(20 downto 11), "0110001000") then
246 result := ctrl.tb;
247 result_en := 1;
248 end if;
249 when OP_MFCR =>
250 if e_in.insn(20) = '0' then
251 -- mfcr
252 result := x"00000000" & e_in.cr;
253 else
254 -- mfocrf
255 crnum := fxm_to_num(insn_fxm(e_in.insn));
256 result := (others => '0');
257 for i in 0 to 7 loop
258 lo := (7-i)*4;
259 hi := lo + 3;
260 if crnum = i then
261 result(hi downto lo) := e_in.cr(hi downto lo);
262 end if;
263 end loop;
264 end if;
265 result_en := 1;
266 when OP_MTCRF =>
267 v.e.write_cr_enable := '1';
268 if e_in.insn(20) = '0' then
269 -- mtcrf
270 v.e.write_cr_mask := insn_fxm(e_in.insn);
271 else
272 -- mtocrf: We require one hot priority encoding here
273 crnum := fxm_to_num(insn_fxm(e_in.insn));
274 v.e.write_cr_mask := num_to_fxm(crnum);
275 end if;
276 v.e.write_cr_data := e_in.read_data3(31 downto 0);
277 when OP_MTSPR =>
278 if std_match(e_in.insn(20 downto 11), "0100100000") then
279 ctrl_tmp.ctr <= e_in.read_data3;
280 elsif std_match(e_in.insn(20 downto 11), "0100000000") then
281 ctrl_tmp.lr <= e_in.read_data3;
282 end if;
283 when OP_NAND =>
284 result := ppc_nand(e_in.read_data3, e_in.read_data2);
285 result_en := 1;
286 when OP_NEG =>
287 result := ppc_neg(e_in.read_data1);
288 result_en := 1;
289 when OP_NOR =>
290 result := ppc_nor(e_in.read_data3, e_in.read_data2);
291 result_en := 1;
292 when OP_OR =>
293 result := ppc_or(e_in.read_data3, e_in.read_data2);
294 result_en := 1;
295 when OP_ORC =>
296 result := ppc_orc(e_in.read_data3, e_in.read_data2);
297 result_en := 1;
298 when OP_POPCNTB =>
299 result := ppc_popcntb(e_in.read_data3);
300 result_en := 1;
301 when OP_POPCNTW =>
302 result := ppc_popcntw(e_in.read_data3);
303 result_en := 1;
304 when OP_POPCNTD =>
305 result := ppc_popcntd(e_in.read_data3);
306 result_en := 1;
307 when OP_PRTYD =>
308 result := ppc_prtyd(e_in.read_data3);
309 result_en := 1;
310 when OP_PRTYW =>
311 result := ppc_prtyw(e_in.read_data3);
312 result_en := 1;
313 when OP_RLDCX =>
314 -- note rldcl mb field and rldcr me field are in the same place
315 mb := insn_mb(e_in.insn);
316 if e_in.insn(1) = '0' then
317 result := ppc_rldcl(e_in.read_data3, e_in.read_data2, mb);
318 else
319 result := ppc_rldcr(e_in.read_data3, e_in.read_data2, mb);
320 end if;
321 result_en := 1;
322 when OP_RLDICL =>
323 sh := insn_sh(e_in.insn);
324 mb := insn_mb(e_in.insn);
325 result := ppc_rldicl(e_in.read_data3, sh, mb);
326 result_en := 1;
327 when OP_RLDICR =>
328 sh := insn_sh(e_in.insn);
329 me := insn_me(e_in.insn);
330 result := ppc_rldicr(e_in.read_data3, sh, me);
331 result_en := 1;
332 when OP_RLWNM =>
333 mb32 := insn_mb32(e_in.insn);
334 me32 := insn_me32(e_in.insn);
335 result := ppc_rlwnm(e_in.read_data3, e_in.read_data2, mb32, me32);
336 result_en := 1;
337 when OP_RLWINM =>
338 sh32 := insn_sh32(e_in.insn);
339 mb32 := insn_mb32(e_in.insn);
340 me32 := insn_me32(e_in.insn);
341 result := ppc_rlwinm(e_in.read_data3, sh32, mb32, me32);
342 result_en := 1;
343 when OP_RLDIC =>
344 sh := insn_sh(e_in.insn);
345 mb := insn_mb(e_in.insn);
346 result := ppc_rldic(e_in.read_data3, sh, mb);
347 result_en := 1;
348 when OP_RLDIMI =>
349 sh := insn_sh(e_in.insn);
350 mb := insn_mb(e_in.insn);
351 result := ppc_rldimi(e_in.read_data1, e_in.read_data3, sh, mb);
352 result_en := 1;
353 when OP_RLWIMI =>
354 sh32 := insn_sh32(e_in.insn);
355 mb32 := insn_mb32(e_in.insn);
356 me32 := insn_me32(e_in.insn);
357 result := ppc_rlwimi(e_in.read_data1, e_in.read_data3, sh32, mb32, me32);
358 result_en := 1;
359 when OP_SLD =>
360 result := ppc_sld(e_in.read_data3, e_in.read_data2);
361 result_en := 1;
362 when OP_SLW =>
363 result := ppc_slw(e_in.read_data3, e_in.read_data2);
364 result_en := 1;
365 when OP_SRAW =>
366 result_with_carry := ppc_sraw(e_in.read_data3, e_in.read_data2);
367 result := result_with_carry(63 downto 0);
368 ctrl_tmp.carry <= result_with_carry(64);
369 result_en := 1;
370 when OP_SRAWI =>
371 sh := '0' & insn_sh32(e_in.insn);
372 result_with_carry := ppc_srawi(e_in.read_data3, sh);
373 result := result_with_carry(63 downto 0);
374 ctrl_tmp.carry <= result_with_carry(64);
375 result_en := 1;
376 when OP_SRAD =>
377 result_with_carry := ppc_srad(e_in.read_data3, e_in.read_data2);
378 result := result_with_carry(63 downto 0);
379 ctrl_tmp.carry <= result_with_carry(64);
380 result_en := 1;
381 when OP_SRADI =>
382 sh := insn_sh(e_in.insn);
383 result_with_carry := ppc_sradi(e_in.read_data3, sh);
384 result := result_with_carry(63 downto 0);
385 ctrl_tmp.carry <= result_with_carry(64);
386 result_en := 1;
387 when OP_SRD =>
388 result := ppc_srd(e_in.read_data3, e_in.read_data2);
389 result_en := 1;
390 when OP_SRW =>
391 result := ppc_srw(e_in.read_data3, e_in.read_data2);
392 result_en := 1;
393 when OP_XOR =>
394 result := ppc_xor(e_in.read_data3, e_in.read_data2);
395 result_en := 1;
396
397 when OP_SIM_CONFIG =>
398 -- bit 0 was used to select the microwatt console, which
399 -- we no longer support.
400 if SIM = true then
401 result := x"0000000000000000";
402 else
403 result := x"0000000000000000";
404 end if;
405 result_en := 1;
406
407 when OP_TDI =>
408 -- Keep our test cases happy for now, ignore trap instructions
409 report "OP_TDI FIXME";
410
411 when others =>
412 terminate_out <= '1';
413 report "illegal";
414 end case;
415
416 if e_in.lr = '1' then
417 ctrl_tmp.lr <= std_ulogic_vector(unsigned(e_in.nia) + 4);
418 end if;
419
420 if result_en = 1 then
421 v.e.write_data := result;
422 v.e.write_enable := '1';
423 v.e.rc := e_in.rc;
424 end if;
425 end if;
426
427 -- Update registers
428 rin <= v;
429
430 -- update outputs
431 --f_out <= r.f;
432 e_out <= r.e;
433 flush_out <= f_out.redirect;
434 end process;
435 end architecture behaviour;