2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.crhelpers.all;
10 use work.insn_helpers.all;
11 use work.ppc_fx_insns.all;
15 EX1_BYPASS : boolean := true;
16 -- Non-zero to enable log data collection
17 LOG_LENGTH : natural := 0
24 flush_out : out std_ulogic;
25 busy_out : out std_ulogic;
27 e_in : in Decode2ToExecute1Type;
28 l_in : in Loadstore1ToExecute1Type;
30 ext_irq_in : std_ulogic;
33 l_out : out Execute1ToLoadstore1Type;
34 f_out : out Execute1ToFetch1Type;
36 e_out : out Execute1ToWritebackType;
38 dbg_msr_out : out std_ulogic_vector(63 downto 0);
40 icache_inval : out std_ulogic;
41 terminate_out : out std_ulogic;
43 log_out : out std_ulogic_vector(14 downto 0);
44 log_rd_addr : out std_ulogic_vector(31 downto 0);
45 log_rd_data : in std_ulogic_vector(63 downto 0);
46 log_wr_addr : in std_ulogic_vector(31 downto 0)
50 architecture behaviour of execute1 is
51 type reg_type is record
52 e : Execute1ToWritebackType;
53 f : Execute1ToFetch1Type;
55 terminate: std_ulogic;
56 lr_update : std_ulogic;
57 next_lr : std_ulogic_vector(63 downto 0);
58 mul_in_progress : std_ulogic;
59 mul_finish : std_ulogic;
60 div_in_progress : std_ulogic;
61 cntz_in_progress : std_ulogic;
62 slow_op_insn : insn_type_t;
63 slow_op_dest : gpr_index_t;
64 slow_op_rc : std_ulogic;
65 slow_op_oe : std_ulogic;
66 slow_op_xerc : xer_common_t;
67 last_nia : std_ulogic_vector(63 downto 0);
68 log_addr_spr : std_ulogic_vector(31 downto 0);
70 constant reg_type_init : reg_type :=
71 (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
72 busy => '0', lr_update => '0', terminate => '0',
73 mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
74 slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
75 next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
77 signal r, rin : reg_type;
79 signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
80 signal cr_in : std_ulogic_vector(31 downto 0);
82 signal valid_in : std_ulogic;
83 signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
84 signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
85 signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
86 signal rot_sign_ext: std_ulogic;
87 signal rotator_result: std_ulogic_vector(63 downto 0);
88 signal rotator_carry: std_ulogic;
89 signal logical_result: std_ulogic_vector(63 downto 0);
90 signal countzero_result: std_ulogic_vector(63 downto 0);
93 signal x_to_multiply: MultiplyInputType;
94 signal multiply_to_x: MultiplyOutputType;
97 signal x_to_divider: Execute1ToDividerType;
98 signal divider_to_x: DividerToExecute1Type;
100 -- random number generator signals
101 signal random_raw : std_ulogic_vector(63 downto 0);
102 signal random_cond : std_ulogic_vector(63 downto 0);
103 signal random_err : std_ulogic;
105 -- signals for logging
106 signal exception_log : std_ulogic;
107 signal irq_valid_log : std_ulogic;
109 type privilege_level is (USER, SUPER);
110 type op_privilege_array is array(insn_type_t) of privilege_level;
111 constant op_privilege: op_privilege_array := (
120 function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
123 if op_privilege(op) = SUPER then
125 elsif op = OP_MFSPR or op = OP_MTSPR then
126 return insn(20) = '1';
132 procedure set_carry(e: inout Execute1ToWritebackType;
133 carry32 : in std_ulogic;
134 carry : in std_ulogic) is
136 e.xerc.ca32 := carry32;
138 e.write_xerc_enable := '1';
141 procedure set_ov(e: inout Execute1ToWritebackType;
143 ov32 : in std_ulogic) is
150 e.write_xerc_enable := '1';
153 function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
154 ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
156 return (ca xor msb_r) and not (msb_a xor msb_b);
159 function decode_input_carry(ic : carry_in_t;
160 xerc : xer_common_t) return std_ulogic is
172 function msr_copy(msr: std_ulogic_vector(63 downto 0))
173 return std_ulogic_vector is
174 variable msr_out: std_ulogic_vector(63 downto 0);
177 -- Defined MSR bits are classified as either full func-
178 -- tion or partial function. Full function MSR bits are
179 -- saved in SRR1 or HSRR1 when an interrupt other
180 -- than a System Call Vectored interrupt occurs and
181 -- restored by rfscv, rfid, or hrfid, while partial func-
182 -- tion MSR bits are not saved or restored.
183 -- Full function MSR bits lie in the range 0:32, 37:41, and
184 -- 48:63, and partial function MSR bits lie in the range
185 -- 33:36 and 42:47. (Note this is IBM bit numbering).
186 msr_out := (others => '0');
187 msr_out(63 downto 31) := msr(63 downto 31);
188 msr_out(26 downto 22) := msr(26 downto 22);
189 msr_out(15 downto 0) := msr(15 downto 0);
193 -- Tell vivado to keep the hierarchy for the random module so that the
194 -- net names in the xdc file match.
195 attribute keep_hierarchy : string;
196 attribute keep_hierarchy of random_0 : label is "yes";
200 rotator_0: entity work.rotator
204 shift => b_in(6 downto 0),
206 is_32bit => e_in.is_32bit,
207 right_shift => right_shift,
208 arith => e_in.is_signed,
209 clear_left => rot_clear_left,
210 clear_right => rot_clear_right,
211 sign_ext_rs => rot_sign_ext,
212 result => rotator_result,
213 carry_out => rotator_carry
216 logical_0: entity work.logical
220 op => e_in.insn_type,
221 invert_in => e_in.invert_a,
222 invert_out => e_in.invert_out,
223 result => logical_result,
224 datalen => e_in.data_len
227 countzero_0: entity work.zero_counter
231 count_right => e_in.insn(10),
232 is_32bit => e_in.is_32bit,
233 result => countzero_result
236 multiply_0: entity work.multiply
239 m_in => x_to_multiply,
240 m_out => multiply_to_x
243 divider_0: entity work.divider
247 d_in => x_to_divider,
248 d_out => divider_to_x
251 random_0: entity work.random
259 dbg_msr_out <= ctrl.msr;
260 log_rd_addr <= r.log_addr_spr;
262 a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
263 b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
264 c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
266 busy_out <= l_in.busy or r.busy;
267 valid_in <= e_in.valid and not busy_out;
269 terminate_out <= r.terminate;
271 execute1_0: process(clk)
273 if rising_edge(clk) then
276 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
277 ctrl.irq_state <= WRITE_SRR0;
281 assert not (r.lr_update = '1' and valid_in = '1')
282 report "LR update collision with valid in EX1"
284 if r.lr_update = '1' then
285 report "LR update to " & to_hstring(r.next_lr);
291 execute1_1: process(all)
292 variable v : reg_type;
293 variable a_inv : std_ulogic_vector(63 downto 0);
294 variable result : std_ulogic_vector(63 downto 0);
295 variable newcrf : std_ulogic_vector(3 downto 0);
296 variable result_with_carry : std_ulogic_vector(64 downto 0);
297 variable result_en : std_ulogic;
298 variable crnum : crnum_t;
299 variable crbit : integer range 0 to 31;
300 variable scrnum : crnum_t;
301 variable lo, hi : integer;
302 variable sh, mb, me : std_ulogic_vector(5 downto 0);
303 variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
304 variable bo, bi : std_ulogic_vector(4 downto 0);
305 variable bf, bfa : std_ulogic_vector(2 downto 0);
306 variable cr_op : std_ulogic_vector(9 downto 0);
307 variable cr_operands : std_ulogic_vector(1 downto 0);
308 variable bt, ba, bb : std_ulogic_vector(4 downto 0);
309 variable btnum, banum, bbnum : integer range 0 to 31;
310 variable crresult : std_ulogic;
311 variable l : std_ulogic;
312 variable next_nia : std_ulogic_vector(63 downto 0);
313 variable carry_32, carry_64 : std_ulogic;
314 variable sign1, sign2 : std_ulogic;
315 variable abs1, abs2 : signed(63 downto 0);
316 variable overflow : std_ulogic;
317 variable zerohi, zerolo : std_ulogic;
318 variable msb_a, msb_b : std_ulogic;
319 variable a_lt : std_ulogic;
320 variable lv : Execute1ToLoadstore1Type;
321 variable irq_valid : std_ulogic;
322 variable exception : std_ulogic;
323 variable exception_nextpc : std_ulogic;
324 variable trapval : std_ulogic_vector(4 downto 0);
325 variable illegal : std_ulogic;
326 variable is_branch : std_ulogic;
327 variable taken_branch : std_ulogic;
328 variable abs_branch : std_ulogic;
329 variable spr_val : std_ulogic_vector(63 downto 0);
330 variable addend : std_ulogic_vector(127 downto 0);
332 result := (others => '0');
333 result_with_carry := (others => '0');
335 newcrf := (others => '0');
341 v.e := Execute1ToWritebackInit;
342 lv := Execute1ToLoadstore1Init;
345 -- XER forwarding. To avoid having to track XER hazards, we
346 -- use the previously latched value.
348 -- If the XER was modified by a multiply or a divide, those are
349 -- single issue, we'll get the up to date value from decode2 from
350 -- the register file.
352 -- If it was modified by an instruction older than the previous
353 -- one in EX1, it will have also hit writeback and will be up
354 -- to date in decode2.
356 -- That leaves us with the case where it was updated by the previous
357 -- instruction in EX1. In that case, we can forward it back here.
359 -- This will break if we allow pipelining of multiply and divide,
360 -- but ideally, those should go via EX1 anyway and run as a state
361 -- machine from here.
363 -- One additional hazard to beware of is an XER:SO modifying instruction
364 -- in EX1 followed immediately by a store conditional. Due to our
365 -- writeback latency, the store will go down the LSU with the previous
366 -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
368 -- We will need to handle that if we ever make stcx. not single issue
370 -- We always pass a valid XER value downto writeback even when
371 -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
372 -- to work for RC instructions.
374 if r.e.write_xerc_enable = '1' then
375 v.e.xerc := r.e.xerc;
377 v.e.xerc := e_in.xerc;
382 if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
384 if r.e.write_cr_mask(i) = '1' then
385 cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
391 v.mul_in_progress := '0';
392 v.div_in_progress := '0';
393 v.cntz_in_progress := '0';
396 -- signals to multiply and divide units
399 if e_in.is_signed = '1' then
400 if e_in.is_32bit = '1' then
408 -- take absolute values
410 abs1 := signed(a_in);
412 abs1 := - signed(a_in);
415 abs2 := signed(b_in);
417 abs2 := - signed(b_in);
420 x_to_multiply <= MultiplyInputInit;
421 x_to_multiply.is_32bit <= e_in.is_32bit;
423 x_to_divider <= Execute1ToDividerInit;
424 x_to_divider.is_signed <= e_in.is_signed;
425 x_to_divider.is_32bit <= e_in.is_32bit;
426 if e_in.insn_type = OP_MOD then
427 x_to_divider.is_modulus <= '1';
430 addend := (others => '0');
431 if e_in.insn(26) = '0' then
432 -- integer multiply-add, major op 4 (if it is a multiply)
433 addend(63 downto 0) := c_in;
434 if e_in.is_signed = '1' then
435 addend(127 downto 64) := (others => c_in(63));
438 if (sign1 xor sign2) = '1' then
439 addend := not addend;
442 x_to_multiply.not_result <= sign1 xor sign2;
443 x_to_multiply.addend <= addend;
444 x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
445 if e_in.is_32bit = '0' then
447 x_to_multiply.data1 <= std_ulogic_vector(abs1);
448 x_to_multiply.data2 <= std_ulogic_vector(abs2);
449 if e_in.insn_type = OP_DIVE then
450 x_to_divider.is_extended <= '1';
452 x_to_divider.dividend <= std_ulogic_vector(abs1);
453 x_to_divider.divisor <= std_ulogic_vector(abs2);
456 x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
457 x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
458 x_to_divider.is_extended <= '0';
459 if e_in.insn_type = OP_DIVE then -- extended forms
460 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
462 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
464 x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
468 -- FIXME: run at 512MHz not core freq
469 ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
470 ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
473 if ctrl.msr(MSR_EE) = '1' then
474 if ctrl.dec(63) = '1' then
475 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
476 report "IRQ valid: DEC";
478 elsif ext_irq_in = '1' then
479 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
480 report "IRQ valid: External";
488 -- send MSR[IR] and ~MSR[PR] up to fetch1
489 v.f.virt_mode := ctrl.msr(MSR_IR);
490 v.f.priv_mode := not ctrl.msr(MSR_PR);
492 -- Next insn adder used in a couple of places
493 next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
495 -- rotator control signals
496 right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
497 rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
498 rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
499 rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
501 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
502 ctrl_tmp.irq_state <= WRITE_SRR0;
505 exception_nextpc := '0';
506 v.e.exc_write_enable := '0';
507 v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
508 v.e.exc_write_data := e_in.nia;
509 if valid_in = '1' then
510 v.last_nia := e_in.nia;
513 if ctrl.irq_state = WRITE_SRR1 then
514 v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
515 v.e.exc_write_data := ctrl.srr1;
516 v.e.exc_write_enable := '1';
517 ctrl_tmp.msr(MSR_SF) <= '1';
518 ctrl_tmp.msr(MSR_EE) <= '0';
519 ctrl_tmp.msr(MSR_PR) <= '0';
520 ctrl_tmp.msr(MSR_IR) <= '0';
521 ctrl_tmp.msr(MSR_DR) <= '0';
522 ctrl_tmp.msr(MSR_RI) <= '0';
523 ctrl_tmp.msr(MSR_LE) <= '1';
525 report "Writing SRR1: " & to_hstring(ctrl.srr1);
527 elsif irq_valid = '1' and valid_in = '1' then
528 -- we need two cycles to write srr0 and 1
529 -- will need more when we have to write HEIR
530 -- Don't deliver the interrupt until we have a valid instruction
531 -- coming in, so we have a valid NIA to put in SRR0.
534 elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
535 instr_is_privileged(e_in.insn_type, e_in.insn) then
536 -- generate a program interrupt
538 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
539 -- set bit 45 to indicate privileged instruction type interrupt
540 ctrl_tmp.srr1(63 - 45) <= '1';
541 report "privileged instruction";
543 elsif valid_in = '1' and e_in.unit = ALU then
545 report "execute nia " & to_hstring(e_in.nia);
548 v.e.write_reg := e_in.write_reg;
549 v.slow_op_insn := e_in.insn_type;
550 v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
551 v.slow_op_rc := e_in.rc;
552 v.slow_op_oe := e_in.oe;
553 v.slow_op_xerc := v.e.xerc;
555 case_0: case e_in.insn_type is
558 -- we need two cycles to write srr0 and 1
559 -- will need more when we have to write HEIR
562 -- check bit 1 of the instruction is 1 so we know this is sc;
563 -- 0 would mean scv, so generate an illegal instruction interrupt
564 -- we need two cycles to write srr0 and 1
565 if e_in.insn(1) = '1' then
567 exception_nextpc := '1';
568 v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
574 -- check bits 1-10 of the instruction to make sure it's attn
575 -- if not then it is illegal
576 if e_in.insn(10 downto 1) = "0100000000" then
584 when OP_ADD | OP_CMP | OP_TRAP =>
585 if e_in.invert_a = '0' then
590 result_with_carry := ppc_adde(a_inv, b_in,
591 decode_input_carry(e_in.input_carry, v.e.xerc));
592 result := result_with_carry(63 downto 0);
593 carry_32 := result(32) xor a_inv(32) xor b_in(32);
594 carry_64 := result_with_carry(64);
595 if e_in.insn_type = OP_ADD then
596 if e_in.output_carry = '1' then
597 set_carry(v.e, carry_32, carry_64);
599 if e_in.oe = '1' then
601 calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
602 calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
606 -- trap, CMP and CMPL instructions
607 -- Note, we have done RB - RA, not RA - RB
608 if e_in.insn_type = OP_CMP then
609 l := insn_l(e_in.insn);
611 l := not e_in.is_32bit;
613 zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
614 zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
615 if zerolo = '1' and (l = '0' or zerohi = '1') then
628 if msb_a /= msb_b then
629 -- Subtraction might overflow, but
630 -- comparison is clear from MSB difference.
631 -- for signed, 0 is greater; for unsigned, 1 is greater
632 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
634 -- Subtraction cannot overflow since MSBs are equal.
635 -- carry = 1 indicates RA is smaller (signed or unsigned)
636 a_lt := (not l and carry_32) or (l and carry_64);
637 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
640 if e_in.insn_type = OP_CMP then
641 if e_in.is_signed = '1' then
642 newcrf := trapval(4 downto 2) & v.e.xerc.so;
644 newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
646 bf := insn_bf(e_in.insn);
647 crnum := to_integer(unsigned(bf));
648 v.e.write_cr_enable := '1';
649 v.e.write_cr_mask := num_to_fxm(crnum);
653 v.e.write_cr_data(hi downto lo) := newcrf;
656 -- trap instructions (tw, twi, td, tdi)
657 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
658 -- set bit 46 to say trap occurred
659 ctrl_tmp.srr1(63 - 46) <= '1';
660 if or (trapval and insn_to(e_in.insn)) = '1' then
661 -- generate trap-type program interrupt
668 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
669 bf := insn_bf(e_in.insn);
670 crnum := to_integer(unsigned(bf));
671 v.e.write_cr_enable := '1';
672 v.e.write_cr_mask := num_to_fxm(crnum);
673 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
674 newcrf & newcrf & newcrf & newcrf;
676 newcrf := ppc_cmpeqb(a_in, b_in);
677 bf := insn_bf(e_in.insn);
678 crnum := to_integer(unsigned(bf));
679 v.e.write_cr_enable := '1';
680 v.e.write_cr_mask := num_to_fxm(crnum);
681 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
682 newcrf & newcrf & newcrf & newcrf;
683 when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS | OP_BPERM =>
684 result := logical_result;
689 abs_branch := insn_aa(e_in.insn);
692 bo := insn_bo(e_in.insn);
693 bi := insn_bi(e_in.insn);
694 if bo(4-2) = '0' then
695 result := std_ulogic_vector(unsigned(a_in) - 1);
697 v.e.write_reg := fast_spr_num(SPR_CTR);
700 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
701 abs_branch := insn_aa(e_in.insn);
704 -- read_data2 is target register (CTR, LR or TAR)
705 bo := insn_bo(e_in.insn);
706 bi := insn_bi(e_in.insn);
707 if bo(4-2) = '0' and e_in.insn(10) = '0' then
708 result := std_ulogic_vector(unsigned(a_in) - 1);
710 v.e.write_reg := fast_spr_num(SPR_CTR);
713 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
717 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
718 v.f.priv_mode := not a_in(MSR_PR);
719 -- Can't use msr_copy here because the partial function MSR
720 -- bits should be left unchanged, not zeroed.
721 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
722 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
723 ctrl_tmp.msr(15 downto 0) <= a_in(15 downto 0);
724 if a_in(MSR_PR) = '1' then
725 ctrl_tmp.msr(MSR_EE) <= '1';
726 ctrl_tmp.msr(MSR_IR) <= '1';
727 ctrl_tmp.msr(MSR_DR) <= '1';
729 -- mark this as a branch so CFAR gets updated
736 v.cntz_in_progress := '1';
739 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
740 if cr_in(31-crbit) = '1' then
747 cr_op := insn_cr(e_in.insn);
748 report "CR OP " & to_hstring(cr_op);
749 if cr_op(0) = '0' then -- MCRF
750 bf := insn_bf(e_in.insn);
751 bfa := insn_bfa(e_in.insn);
752 v.e.write_cr_enable := '1';
753 crnum := to_integer(unsigned(bf));
754 scrnum := to_integer(unsigned(bfa));
755 v.e.write_cr_mask := num_to_fxm(crnum);
760 newcrf := cr_in(hi downto lo);
766 v.e.write_cr_data(hi downto lo) := newcrf;
769 v.e.write_cr_enable := '1';
770 bt := insn_bt(e_in.insn);
771 ba := insn_ba(e_in.insn);
772 bb := insn_bb(e_in.insn);
773 btnum := 31 - to_integer(unsigned(bt));
774 banum := 31 - to_integer(unsigned(ba));
775 bbnum := 31 - to_integer(unsigned(bb));
776 -- Bits 5-8 of cr_op give the truth table of the requested
778 cr_operands := cr_in(banum) & cr_in(bbnum);
779 crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
780 v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
781 for i in 0 to 31 loop
783 v.e.write_cr_data(i) := crresult;
785 v.e.write_cr_data(i) := cr_in(i);
790 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
791 bf := insn_bf(e_in.insn);
792 crnum := to_integer(unsigned(bf));
793 v.e.write_cr_enable := '1';
794 v.e.write_cr_mask := num_to_fxm(crnum);
795 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
796 newcrf & newcrf & newcrf & newcrf;
798 if random_err = '0' then
799 case e_in.insn(17 downto 16) is
801 result := x"00000000" & random_cond(31 downto 0);
803 result := random_raw;
805 result := random_cond;
808 result := (others => '1');
815 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
816 "=" & to_hstring(a_in);
818 if is_fast_spr(e_in.read_reg1) then
820 if decode_spr_num(e_in.insn) = SPR_XER then
821 -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
822 result(63 downto 32) := (others => '0');
823 result(63-32) := v.e.xerc.so;
824 result(63-33) := v.e.xerc.ov;
825 result(63-34) := v.e.xerc.ca;
826 result(63-35 downto 63-43) := "000000000";
827 result(63-44) := v.e.xerc.ov32;
828 result(63-45) := v.e.xerc.ca32;
832 case decode_spr_num(e_in.insn) is
836 spr_val(63 downto 32) := (others => '0');
837 spr_val(31 downto 0) := ctrl.tb(63 downto 32);
841 spr_val := ctrl.cfar;
843 spr_val(63 downto 32) := (others => '0');
844 spr_val(31 downto 0) := PVR_MICROWATT;
845 when 724 => -- LOG_ADDR SPR
846 spr_val := log_wr_addr & r.log_addr_spr;
847 when 725 => -- LOG_DATA SPR
848 spr_val := log_rd_data;
849 v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
851 -- mfspr from unimplemented SPRs should be a nop in
852 -- supervisor mode and a program interrupt for user mode
853 if ctrl.msr(MSR_PR) = '1' then
860 if e_in.insn(20) = '0' then
862 result := x"00000000" & cr_in;
865 crnum := fxm_to_num(insn_fxm(e_in.insn));
866 result := (others => '0');
871 result(hi downto lo) := cr_in(hi downto lo);
877 v.e.write_cr_enable := '1';
878 if e_in.insn(20) = '0' then
880 v.e.write_cr_mask := insn_fxm(e_in.insn);
882 -- mtocrf: We require one hot priority encoding here
883 crnum := fxm_to_num(insn_fxm(e_in.insn));
884 v.e.write_cr_mask := num_to_fxm(crnum);
886 v.e.write_cr_data := c_in(31 downto 0);
888 if e_in.insn(16) = '1' then
889 -- just update EE and RI
890 ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
891 ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
893 -- Architecture says to leave out bits 3 (HV), 51 (ME)
894 -- and 63 (LE) (IBM bit numbering)
895 ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
896 ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
897 ctrl_tmp.msr(11 downto 1) <= c_in(11 downto 1);
898 if c_in(MSR_PR) = '1' then
899 ctrl_tmp.msr(MSR_EE) <= '1';
900 ctrl_tmp.msr(MSR_IR) <= '1';
901 ctrl_tmp.msr(MSR_DR) <= '1';
905 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
906 "=" & to_hstring(c_in);
907 if is_fast_spr(e_in.write_reg) then
910 if decode_spr_num(e_in.insn) = SPR_XER then
911 v.e.xerc.so := c_in(63-32);
912 v.e.xerc.ov := c_in(63-33);
913 v.e.xerc.ca := c_in(63-34);
914 v.e.xerc.ov32 := c_in(63-44);
915 v.e.xerc.ca32 := c_in(63-45);
916 v.e.write_xerc_enable := '1';
920 case decode_spr_num(e_in.insn) is
922 ctrl_tmp.dec <= c_in;
923 when 724 => -- LOG_ADDR SPR
924 v.log_addr_spr := c_in(31 downto 0);
926 -- mtspr to unimplemented SPRs should be a nop in
927 -- supervisor mode and a program interrupt for user mode
928 if ctrl.msr(MSR_PR) = '1' then
933 when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
934 result := rotator_result;
935 if e_in.output_carry = '1' then
936 set_carry(v.e, rotator_carry, rotator_carry);
940 bfa := insn_bfa(e_in.insn);
941 crbit := to_integer(unsigned(bfa)) * 4;
942 result := (others => '0');
943 if cr_in(31 - crbit) = '1' then
944 result := (others => '1');
945 elsif cr_in(30 - crbit) = '1' then
951 v.f.redirect_nia := next_nia;
956 when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
958 v.mul_in_progress := '1';
960 x_to_multiply.valid <= '1';
962 when OP_DIV | OP_DIVE | OP_MOD =>
964 v.div_in_progress := '1';
966 x_to_divider.valid <= '1';
973 v.e.rc := e_in.rc and valid_in;
975 -- Mispredicted branches cause a redirect
976 if is_branch = '1' then
977 if taken_branch = '1' then
978 ctrl_tmp.cfar <= e_in.nia;
980 if e_in.br_pred = '0' then
981 if abs_branch = '1' then
982 v.f.redirect_nia := b_in;
984 v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
987 v.f.redirect_nia := next_nia;
989 if taken_branch /= e_in.br_pred then
994 -- Update LR on the next cycle after a branch link
995 -- If we're not writing back anything else, we can write back LR
996 -- this cycle, otherwise we take an extra cycle. We use the
997 -- exc_write path since next_nia is written through that path
999 if e_in.lr = '1' then
1000 if result_en = '0' then
1001 v.e.exc_write_enable := '1';
1002 v.e.exc_write_data := next_nia;
1003 v.e.exc_write_reg := fast_spr_num(SPR_LR);
1006 v.next_lr := next_nia;
1008 report "Delayed LR update to " & to_hstring(next_nia);
1013 elsif valid_in = '1' then
1014 -- instruction for other units, i.e. LDST
1015 if e_in.unit = LDST then
1019 elsif r.f.redirect = '1' then
1021 elsif r.lr_update = '1' then
1022 v.e.exc_write_enable := '1';
1023 v.e.exc_write_data := r.next_lr;
1024 v.e.exc_write_reg := fast_spr_num(SPR_LR);
1026 elsif r.cntz_in_progress = '1' then
1027 -- cnt[lt]z always takes two cycles
1028 result := countzero_result;
1030 v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1031 v.e.rc := r.slow_op_rc;
1032 v.e.xerc := r.slow_op_xerc;
1034 elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1035 if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1036 (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1037 if r.mul_in_progress = '1' then
1039 case r.slow_op_insn is
1041 result := multiply_to_x.result(63 downto 32) &
1042 multiply_to_x.result(63 downto 32);
1044 result := multiply_to_x.result(127 downto 64);
1047 result := multiply_to_x.result(63 downto 0);
1050 result := divider_to_x.write_reg_data;
1051 overflow := divider_to_x.overflow;
1053 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1054 -- have to wait until next cycle for overflow indication
1055 v.mul_finish := '1';
1059 v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1060 v.e.rc := r.slow_op_rc;
1061 v.e.xerc := r.slow_op_xerc;
1062 v.e.write_xerc_enable := r.slow_op_oe;
1063 -- We must test oe because the RC update code in writeback
1064 -- will use the xerc value to set CR0:SO so we must not clobber
1065 -- xerc if OE wasn't set.
1066 if r.slow_op_oe = '1' then
1067 v.e.xerc.ov := overflow;
1068 v.e.xerc.ov32 := overflow;
1069 v.e.xerc.so := r.slow_op_xerc.so or overflow;
1075 v.mul_in_progress := r.mul_in_progress;
1076 v.div_in_progress := r.div_in_progress;
1078 elsif r.mul_finish = '1' then
1079 result := r.e.write_data;
1081 v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1082 v.e.rc := r.slow_op_rc;
1083 v.e.xerc := r.slow_op_xerc;
1084 v.e.write_xerc_enable := r.slow_op_oe;
1085 v.e.xerc.ov := multiply_to_x.overflow;
1086 v.e.xerc.ov32 := multiply_to_x.overflow;
1087 v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1091 if illegal = '1' then
1093 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1094 -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1095 -- set bit 44 to indicate we have an illegal
1096 ctrl_tmp.srr1(63 - 44) <= '1';
1099 if exception = '1' then
1100 v.e.exc_write_enable := '1';
1101 if exception_nextpc = '1' then
1102 v.e.exc_write_data := next_nia;
1106 v.e.write_data := result;
1107 v.e.write_enable := result_en and not exception;
1109 -- generate DSI or DSegI for load/store exceptions
1110 -- or ISI or ISegI for instruction fetch exceptions
1111 if l_in.exception = '1' then
1112 if l_in.instr_fault = '0' then
1113 if l_in.segment_fault = '0' then
1114 v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1116 v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1119 if l_in.segment_fault = '0' then
1120 ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1121 ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1122 ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1123 ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1124 v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1126 v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1129 v.e.exc_write_enable := '1';
1130 v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1131 v.e.exc_write_data := r.last_nia;
1132 report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1135 if exception = '1' or l_in.exception = '1' then
1136 ctrl_tmp.irq_state <= WRITE_SRR1;
1137 v.f.redirect := '1';
1138 v.f.virt_mode := '0';
1139 v.f.priv_mode := '1';
1142 if v.f.redirect = '1' then
1147 -- Outputs to loadstore1 (async)
1148 lv.op := e_in.insn_type;
1153 lv.write_reg := gspr_to_gpr(e_in.write_reg);
1154 lv.length := e_in.data_len;
1155 lv.byte_reverse := e_in.byte_reverse;
1156 lv.sign_extend := e_in.sign_extend;
1157 lv.update := e_in.update;
1158 lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1159 lv.xerc := v.e.xerc;
1160 lv.reserve := e_in.reserve;
1162 lv.insn := e_in.insn;
1163 -- decode l*cix and st*cix instructions here
1164 if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1165 e_in.insn(5 downto 1) = "10101" then
1168 lv.virt_mode := ctrl.msr(MSR_DR);
1169 lv.priv_mode := not ctrl.msr(MSR_PR);
1178 flush_out <= f_out.redirect;
1180 exception_log <= exception;
1181 irq_valid_log <= irq_valid;
1184 e1_log: if LOG_LENGTH > 0 generate
1185 signal log_data : std_ulogic_vector(14 downto 0);
1187 ex1_log : process(clk)
1189 if rising_edge(clk) then
1190 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1191 ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1194 std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1203 log_out <= log_data;
1205 end architecture behaviour;