2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.crhelpers.all;
10 use work.insn_helpers.all;
11 use work.ppc_fx_insns.all;
15 EX1_BYPASS : boolean := true;
16 HAS_FPU : boolean := true;
17 -- Non-zero to enable log data collection
18 LOG_LENGTH : natural := 0
25 flush_out : out std_ulogic;
26 busy_out : out std_ulogic;
28 e_in : in Decode2ToExecute1Type;
29 l_in : in Loadstore1ToExecute1Type;
30 fp_in : in FPUToExecute1Type;
32 ext_irq_in : std_ulogic;
35 l_out : out Execute1ToLoadstore1Type;
36 f_out : out Execute1ToFetch1Type;
37 fp_out : out Execute1ToFPUType;
39 e_out : out Execute1ToWritebackType;
41 dbg_msr_out : out std_ulogic_vector(63 downto 0);
43 icache_inval : out std_ulogic;
44 terminate_out : out std_ulogic;
46 log_out : out std_ulogic_vector(14 downto 0);
47 log_rd_addr : out std_ulogic_vector(31 downto 0);
48 log_rd_data : in std_ulogic_vector(63 downto 0);
49 log_wr_addr : in std_ulogic_vector(31 downto 0)
53 architecture behaviour of execute1 is
54 type reg_type is record
55 e : Execute1ToWritebackType;
56 f : Execute1ToFetch1Type;
58 terminate: std_ulogic;
59 fp_exception_next : std_ulogic;
60 trace_next : std_ulogic;
61 prev_op : insn_type_t;
62 lr_update : std_ulogic;
63 next_lr : std_ulogic_vector(63 downto 0);
64 mul_in_progress : std_ulogic;
65 mul_finish : std_ulogic;
66 div_in_progress : std_ulogic;
67 cntz_in_progress : std_ulogic;
68 slow_op_insn : insn_type_t;
69 slow_op_dest : gpr_index_t;
70 slow_op_rc : std_ulogic;
71 slow_op_oe : std_ulogic;
72 slow_op_xerc : xer_common_t;
73 last_nia : std_ulogic_vector(63 downto 0);
74 log_addr_spr : std_ulogic_vector(31 downto 0);
76 constant reg_type_init : reg_type :=
77 (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
78 busy => '0', lr_update => '0', terminate => '0',
79 fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL,
80 mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
81 slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
82 next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
84 signal r, rin : reg_type;
86 signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
87 signal cr_in : std_ulogic_vector(31 downto 0);
89 signal valid_in : std_ulogic;
90 signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
91 signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
92 signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
93 signal rot_sign_ext: std_ulogic;
94 signal rotator_result: std_ulogic_vector(63 downto 0);
95 signal rotator_carry: std_ulogic;
96 signal logical_result: std_ulogic_vector(63 downto 0);
97 signal countzero_result: std_ulogic_vector(63 downto 0);
100 signal x_to_multiply: MultiplyInputType;
101 signal multiply_to_x: MultiplyOutputType;
104 signal x_to_divider: Execute1ToDividerType;
105 signal divider_to_x: DividerToExecute1Type;
107 -- random number generator signals
108 signal random_raw : std_ulogic_vector(63 downto 0);
109 signal random_cond : std_ulogic_vector(63 downto 0);
110 signal random_err : std_ulogic;
112 -- signals for logging
113 signal exception_log : std_ulogic;
114 signal irq_valid_log : std_ulogic;
116 type privilege_level is (USER, SUPER);
117 type op_privilege_array is array(insn_type_t) of privilege_level;
118 constant op_privilege: op_privilege_array := (
127 function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
130 if op_privilege(op) = SUPER then
132 elsif op = OP_MFSPR or op = OP_MTSPR then
133 return insn(20) = '1';
139 procedure set_carry(e: inout Execute1ToWritebackType;
140 carry32 : in std_ulogic;
141 carry : in std_ulogic) is
143 e.xerc.ca32 := carry32;
145 e.write_xerc_enable := '1';
148 procedure set_ov(e: inout Execute1ToWritebackType;
150 ov32 : in std_ulogic) is
157 e.write_xerc_enable := '1';
160 function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
161 ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
163 return (ca xor msb_r) and not (msb_a xor msb_b);
166 function decode_input_carry(ic : carry_in_t;
167 xerc : xer_common_t) return std_ulogic is
181 function msr_copy(msr: std_ulogic_vector(63 downto 0))
182 return std_ulogic_vector is
183 variable msr_out: std_ulogic_vector(63 downto 0);
186 -- Defined MSR bits are classified as either full func-
187 -- tion or partial function. Full function MSR bits are
188 -- saved in SRR1 or HSRR1 when an interrupt other
189 -- than a System Call Vectored interrupt occurs and
190 -- restored by rfscv, rfid, or hrfid, while partial func-
191 -- tion MSR bits are not saved or restored.
192 -- Full function MSR bits lie in the range 0:32, 37:41, and
193 -- 48:63, and partial function MSR bits lie in the range
194 -- 33:36 and 42:47. (Note this is IBM bit numbering).
195 msr_out := (others => '0');
196 msr_out(63 downto 31) := msr(63 downto 31);
197 msr_out(26 downto 22) := msr(26 downto 22);
198 msr_out(15 downto 0) := msr(15 downto 0);
202 -- Tell vivado to keep the hierarchy for the random module so that the
203 -- net names in the xdc file match.
204 attribute keep_hierarchy : string;
205 attribute keep_hierarchy of random_0 : label is "yes";
209 rotator_0: entity work.rotator
213 shift => b_in(6 downto 0),
215 is_32bit => e_in.is_32bit,
216 right_shift => right_shift,
217 arith => e_in.is_signed,
218 clear_left => rot_clear_left,
219 clear_right => rot_clear_right,
220 sign_ext_rs => rot_sign_ext,
221 result => rotator_result,
222 carry_out => rotator_carry
225 logical_0: entity work.logical
229 op => e_in.insn_type,
230 invert_in => e_in.invert_a,
231 invert_out => e_in.invert_out,
232 result => logical_result,
233 datalen => e_in.data_len
236 countzero_0: entity work.zero_counter
240 count_right => e_in.insn(10),
241 is_32bit => e_in.is_32bit,
242 result => countzero_result
245 multiply_0: entity work.multiply
248 m_in => x_to_multiply,
249 m_out => multiply_to_x
252 divider_0: entity work.divider
256 d_in => x_to_divider,
257 d_out => divider_to_x
260 random_0: entity work.random
268 dbg_msr_out <= ctrl.msr;
269 log_rd_addr <= r.log_addr_spr;
271 a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
272 b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
273 c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
275 busy_out <= l_in.busy or r.busy or fp_in.busy;
276 valid_in <= e_in.valid and not busy_out;
278 terminate_out <= r.terminate;
280 execute1_0: process(clk)
282 if rising_edge(clk) then
285 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
286 ctrl.irq_state <= WRITE_SRR0;
290 assert not (r.lr_update = '1' and valid_in = '1')
291 report "LR update collision with valid in EX1"
293 if r.lr_update = '1' then
294 report "LR update to " & to_hstring(r.next_lr);
300 execute1_1: process(all)
301 variable v : reg_type;
302 variable a_inv : std_ulogic_vector(63 downto 0);
303 variable result : std_ulogic_vector(63 downto 0);
304 variable newcrf : std_ulogic_vector(3 downto 0);
305 variable sum_with_carry : std_ulogic_vector(64 downto 0);
306 variable result_en : std_ulogic;
307 variable crnum : crnum_t;
308 variable crbit : integer range 0 to 31;
309 variable scrnum : crnum_t;
310 variable lo, hi : integer;
311 variable sh, mb, me : std_ulogic_vector(5 downto 0);
312 variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
313 variable bo, bi : std_ulogic_vector(4 downto 0);
314 variable bf, bfa : std_ulogic_vector(2 downto 0);
315 variable cr_op : std_ulogic_vector(9 downto 0);
316 variable cr_operands : std_ulogic_vector(1 downto 0);
317 variable bt, ba, bb : std_ulogic_vector(4 downto 0);
318 variable btnum, banum, bbnum : integer range 0 to 31;
319 variable crresult : std_ulogic;
320 variable l : std_ulogic;
321 variable next_nia : std_ulogic_vector(63 downto 0);
322 variable carry_32, carry_64 : std_ulogic;
323 variable sign1, sign2 : std_ulogic;
324 variable abs1, abs2 : signed(63 downto 0);
325 variable overflow : std_ulogic;
326 variable zerohi, zerolo : std_ulogic;
327 variable msb_a, msb_b : std_ulogic;
328 variable a_lt : std_ulogic;
329 variable lv : Execute1ToLoadstore1Type;
330 variable irq_valid : std_ulogic;
331 variable exception : std_ulogic;
332 variable exception_nextpc : std_ulogic;
333 variable trapval : std_ulogic_vector(4 downto 0);
334 variable illegal : std_ulogic;
335 variable is_branch : std_ulogic;
336 variable taken_branch : std_ulogic;
337 variable abs_branch : std_ulogic;
338 variable spr_val : std_ulogic_vector(63 downto 0);
339 variable addend : std_ulogic_vector(127 downto 0);
340 variable do_trace : std_ulogic;
341 variable fv : Execute1ToFPUType;
343 result := (others => '0');
344 sum_with_carry := (others => '0');
346 newcrf := (others => '0');
352 v.e := Execute1ToWritebackInit;
353 lv := Execute1ToLoadstore1Init;
355 fv := Execute1ToFPUInit;
357 -- XER forwarding. To avoid having to track XER hazards, we
358 -- use the previously latched value.
360 -- If the XER was modified by a multiply or a divide, those are
361 -- single issue, we'll get the up to date value from decode2 from
362 -- the register file.
364 -- If it was modified by an instruction older than the previous
365 -- one in EX1, it will have also hit writeback and will be up
366 -- to date in decode2.
368 -- That leaves us with the case where it was updated by the previous
369 -- instruction in EX1. In that case, we can forward it back here.
371 -- This will break if we allow pipelining of multiply and divide,
372 -- but ideally, those should go via EX1 anyway and run as a state
373 -- machine from here.
375 -- One additional hazard to beware of is an XER:SO modifying instruction
376 -- in EX1 followed immediately by a store conditional. Due to our
377 -- writeback latency, the store will go down the LSU with the previous
378 -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
380 -- We will need to handle that if we ever make stcx. not single issue
382 -- We always pass a valid XER value downto writeback even when
383 -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
384 -- to work for RC instructions.
386 if r.e.write_xerc_enable = '1' then
387 v.e.xerc := r.e.xerc;
389 v.e.xerc := e_in.xerc;
394 if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
396 if r.e.write_cr_mask(i) = '1' then
397 cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
403 v.mul_in_progress := '0';
404 v.div_in_progress := '0';
405 v.cntz_in_progress := '0';
409 if e_in.invert_a = '0' then
414 sum_with_carry := ppc_adde(a_inv, b_in,
415 decode_input_carry(e_in.input_carry, v.e.xerc));
417 -- signals to multiply and divide units
420 if e_in.is_signed = '1' then
421 if e_in.is_32bit = '1' then
429 -- take absolute values
431 abs1 := signed(a_in);
433 abs1 := - signed(a_in);
436 abs2 := signed(b_in);
438 abs2 := - signed(b_in);
441 x_to_multiply <= MultiplyInputInit;
442 x_to_multiply.is_32bit <= e_in.is_32bit;
444 x_to_divider <= Execute1ToDividerInit;
445 x_to_divider.is_signed <= e_in.is_signed;
446 x_to_divider.is_32bit <= e_in.is_32bit;
447 if e_in.insn_type = OP_MOD then
448 x_to_divider.is_modulus <= '1';
451 addend := (others => '0');
452 if e_in.insn(26) = '0' then
453 -- integer multiply-add, major op 4 (if it is a multiply)
454 addend(63 downto 0) := c_in;
455 if e_in.is_signed = '1' then
456 addend(127 downto 64) := (others => c_in(63));
459 if (sign1 xor sign2) = '1' then
460 addend := not addend;
463 x_to_multiply.not_result <= sign1 xor sign2;
464 x_to_multiply.addend <= addend;
465 x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
466 if e_in.is_32bit = '0' then
468 x_to_multiply.data1 <= std_ulogic_vector(abs1);
469 x_to_multiply.data2 <= std_ulogic_vector(abs2);
470 if e_in.insn_type = OP_DIVE then
471 x_to_divider.is_extended <= '1';
473 x_to_divider.dividend <= std_ulogic_vector(abs1);
474 x_to_divider.divisor <= std_ulogic_vector(abs2);
477 x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
478 x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
479 x_to_divider.is_extended <= '0';
480 if e_in.insn_type = OP_DIVE then -- extended forms
481 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
483 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
485 x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
489 -- FIXME: run at 512MHz not core freq
490 ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
491 ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
494 if ctrl.msr(MSR_EE) = '1' then
495 if ctrl.dec(63) = '1' then
496 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
497 report "IRQ valid: DEC";
499 elsif ext_irq_in = '1' then
500 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
501 report "IRQ valid: External";
509 -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
510 v.f.virt_mode := ctrl.msr(MSR_IR);
511 v.f.priv_mode := not ctrl.msr(MSR_PR);
512 v.f.big_endian := not ctrl.msr(MSR_LE);
513 v.f.mode_32bit := not ctrl.msr(MSR_SF);
515 -- Next insn adder used in a couple of places
516 next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
518 -- rotator control signals
519 right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
520 rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
521 rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
522 rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
524 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
525 ctrl_tmp.irq_state <= WRITE_SRR0;
528 exception_nextpc := '0';
529 v.e.exc_write_enable := '0';
530 v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
531 if valid_in = '1' then
532 v.e.exc_write_data := e_in.nia;
533 v.last_nia := e_in.nia;
535 v.e.exc_write_data := r.last_nia;
538 v.e.mode_32bit := not ctrl.msr(MSR_SF);
540 do_trace := valid_in and ctrl.msr(MSR_SE);
541 if valid_in = '1' then
542 v.prev_op := e_in.insn_type;
545 if ctrl.irq_state = WRITE_SRR1 then
546 v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
547 v.e.exc_write_data := ctrl.srr1;
548 v.e.exc_write_enable := '1';
549 ctrl_tmp.msr(MSR_SF) <= '1';
550 ctrl_tmp.msr(MSR_EE) <= '0';
551 ctrl_tmp.msr(MSR_PR) <= '0';
552 ctrl_tmp.msr(MSR_SE) <= '0';
553 ctrl_tmp.msr(MSR_BE) <= '0';
554 ctrl_tmp.msr(MSR_FP) <= '0';
555 ctrl_tmp.msr(MSR_FE0) <= '0';
556 ctrl_tmp.msr(MSR_FE1) <= '0';
557 ctrl_tmp.msr(MSR_IR) <= '0';
558 ctrl_tmp.msr(MSR_DR) <= '0';
559 ctrl_tmp.msr(MSR_RI) <= '0';
560 ctrl_tmp.msr(MSR_LE) <= '1';
563 v.fp_exception_next := '0';
564 report "Writing SRR1: " & to_hstring(ctrl.srr1);
566 elsif valid_in = '1' and ((HAS_FPU and r.fp_exception_next = '1') or r.trace_next = '1') then
567 if HAS_FPU and r.fp_exception_next = '1' then
568 -- This is used for FP-type program interrupts that
569 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
570 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
571 ctrl_tmp.srr1(63 - 43) <= '1';
572 ctrl_tmp.srr1(63 - 47) <= '1';
574 -- Generate a trace interrupt rather than executing the next instruction
575 -- or taking any asynchronous interrupt
576 v.f.redirect_nia := std_logic_vector(to_unsigned(16#d00#, 64));
577 ctrl_tmp.srr1(63 - 33) <= '1';
578 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
579 r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
580 ctrl_tmp.srr1(63 - 35) <= '1';
581 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
582 ctrl_tmp.srr1(63 - 36) <= '1';
587 elsif irq_valid = '1' and valid_in = '1' then
588 -- we need two cycles to write srr0 and 1
589 -- will need more when we have to write HEIR
590 -- Don't deliver the interrupt until we have a valid instruction
591 -- coming in, so we have a valid NIA to put in SRR0.
594 elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
595 instr_is_privileged(e_in.insn_type, e_in.insn) then
596 -- generate a program interrupt
598 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
599 -- set bit 45 to indicate privileged instruction type interrupt
600 ctrl_tmp.srr1(63 - 45) <= '1';
601 report "privileged instruction";
603 elsif not HAS_FPU and valid_in = '1' and
604 (e_in.insn_type = OP_FPLOAD or e_in.insn_type = OP_FPSTORE) then
605 -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
608 elsif HAS_FPU and valid_in = '1' and ctrl.msr(MSR_FP) = '0' and
609 (e_in.unit = FPU or e_in.insn_type = OP_FPLOAD or e_in.insn_type = OP_FPSTORE) then
610 -- generate a floating-point unavailable interrupt
612 v.f.redirect_nia := std_logic_vector(to_unsigned(16#800#, 64));
613 report "FP unavailable interrupt";
615 elsif valid_in = '1' and e_in.unit = ALU then
617 report "execute nia " & to_hstring(e_in.nia);
620 v.e.write_reg := e_in.write_reg;
621 v.slow_op_insn := e_in.insn_type;
622 v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
623 v.slow_op_rc := e_in.rc;
624 v.slow_op_oe := e_in.oe;
625 v.slow_op_xerc := v.e.xerc;
627 case_0: case e_in.insn_type is
630 -- we need two cycles to write srr0 and 1
631 -- will need more when we have to write HEIR
634 -- check bit 1 of the instruction is 1 so we know this is sc;
635 -- 0 would mean scv, so generate an illegal instruction interrupt
636 -- we need two cycles to write srr0 and 1
637 if e_in.insn(1) = '1' then
639 exception_nextpc := '1';
640 v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
646 -- check bits 1-10 of the instruction to make sure it's attn
647 -- if not then it is illegal
648 if e_in.insn(10 downto 1) = "0100000000" then
654 when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
656 when OP_ADD | OP_CMP | OP_TRAP =>
657 result := sum_with_carry(63 downto 0);
658 carry_32 := result(32) xor a_inv(32) xor b_in(32);
659 carry_64 := sum_with_carry(64);
660 if e_in.insn_type = OP_ADD then
661 if e_in.output_carry = '1' then
662 if e_in.input_carry /= OV then
663 set_carry(v.e, carry_32, carry_64);
665 v.e.xerc.ov := carry_64;
666 v.e.xerc.ov32 := carry_32;
667 v.e.write_xerc_enable := '1';
670 if e_in.oe = '1' then
672 calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
673 calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
677 -- trap, CMP and CMPL instructions
678 -- Note, we have done RB - RA, not RA - RB
679 if e_in.insn_type = OP_CMP then
680 l := insn_l(e_in.insn);
682 l := not e_in.is_32bit;
684 zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
685 zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
686 if zerolo = '1' and (l = '0' or zerohi = '1') then
699 if msb_a /= msb_b then
700 -- Subtraction might overflow, but
701 -- comparison is clear from MSB difference.
702 -- for signed, 0 is greater; for unsigned, 1 is greater
703 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
705 -- Subtraction cannot overflow since MSBs are equal.
706 -- carry = 1 indicates RA is smaller (signed or unsigned)
707 a_lt := (not l and carry_32) or (l and carry_64);
708 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
711 if e_in.insn_type = OP_CMP then
712 if e_in.is_signed = '1' then
713 newcrf := trapval(4 downto 2) & v.e.xerc.so;
715 newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
717 bf := insn_bf(e_in.insn);
718 crnum := to_integer(unsigned(bf));
719 v.e.write_cr_enable := '1';
720 v.e.write_cr_mask := num_to_fxm(crnum);
724 v.e.write_cr_data(hi downto lo) := newcrf;
727 -- trap instructions (tw, twi, td, tdi)
728 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
729 -- set bit 46 to say trap occurred
730 ctrl_tmp.srr1(63 - 46) <= '1';
731 if or (trapval and insn_to(e_in.insn)) = '1' then
732 -- generate trap-type program interrupt
739 result := (others => '0');
740 for i in 0 to 14 loop
743 if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
744 result(lo + 3 downto lo) := "0110";
747 if sum_with_carry(64) = '0' then
748 result(63 downto 60) := "0110";
752 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
753 bf := insn_bf(e_in.insn);
754 crnum := to_integer(unsigned(bf));
755 v.e.write_cr_enable := '1';
756 v.e.write_cr_mask := num_to_fxm(crnum);
757 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
758 newcrf & newcrf & newcrf & newcrf;
760 newcrf := ppc_cmpeqb(a_in, b_in);
761 bf := insn_bf(e_in.insn);
762 crnum := to_integer(unsigned(bf));
763 v.e.write_cr_enable := '1';
764 v.e.write_cr_mask := num_to_fxm(crnum);
765 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
766 newcrf & newcrf & newcrf & newcrf;
767 when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
769 result := logical_result;
774 abs_branch := insn_aa(e_in.insn);
775 if ctrl.msr(MSR_BE) = '1' then
780 bo := insn_bo(e_in.insn);
781 bi := insn_bi(e_in.insn);
782 if bo(4-2) = '0' then
783 result := std_ulogic_vector(unsigned(a_in) - 1);
785 v.e.write_reg := fast_spr_num(SPR_CTR);
788 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
789 abs_branch := insn_aa(e_in.insn);
790 if ctrl.msr(MSR_BE) = '1' then
795 -- read_data2 is target register (CTR, LR or TAR)
796 bo := insn_bo(e_in.insn);
797 bi := insn_bi(e_in.insn);
798 if bo(4-2) = '0' and e_in.insn(10) = '0' then
799 result := std_ulogic_vector(unsigned(a_in) - 1);
801 v.e.write_reg := fast_spr_num(SPR_CTR);
804 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
806 if ctrl.msr(MSR_BE) = '1' then
811 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
812 v.f.priv_mode := not a_in(MSR_PR);
813 v.f.big_endian := not a_in(MSR_LE);
814 v.f.mode_32bit := not a_in(MSR_SF);
815 -- Can't use msr_copy here because the partial function MSR
816 -- bits should be left unchanged, not zeroed.
817 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
818 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
819 ctrl_tmp.msr(15 downto 0) <= a_in(15 downto 0);
820 if a_in(MSR_PR) = '1' then
821 ctrl_tmp.msr(MSR_EE) <= '1';
822 ctrl_tmp.msr(MSR_IR) <= '1';
823 ctrl_tmp.msr(MSR_DR) <= '1';
825 -- mark this as a branch so CFAR gets updated
830 v.fp_exception_next := fp_in.exception and
831 (a_in(MSR_FE0) or a_in(MSR_FE1));
837 v.cntz_in_progress := '1';
840 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
841 if cr_in(31-crbit) = '1' then
848 cr_op := insn_cr(e_in.insn);
849 report "CR OP " & to_hstring(cr_op);
850 if cr_op(0) = '0' then -- MCRF
851 bf := insn_bf(e_in.insn);
852 bfa := insn_bfa(e_in.insn);
853 v.e.write_cr_enable := '1';
854 crnum := to_integer(unsigned(bf));
855 scrnum := to_integer(unsigned(bfa));
856 v.e.write_cr_mask := num_to_fxm(crnum);
861 newcrf := cr_in(hi downto lo);
867 v.e.write_cr_data(hi downto lo) := newcrf;
870 v.e.write_cr_enable := '1';
871 bt := insn_bt(e_in.insn);
872 ba := insn_ba(e_in.insn);
873 bb := insn_bb(e_in.insn);
874 btnum := 31 - to_integer(unsigned(bt));
875 banum := 31 - to_integer(unsigned(ba));
876 bbnum := 31 - to_integer(unsigned(bb));
877 -- Bits 5-8 of cr_op give the truth table of the requested
879 cr_operands := cr_in(banum) & cr_in(bbnum);
880 crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
881 v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
882 for i in 0 to 31 loop
884 v.e.write_cr_data(i) := crresult;
886 v.e.write_cr_data(i) := cr_in(i);
891 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
892 bf := insn_bf(e_in.insn);
893 crnum := to_integer(unsigned(bf));
894 v.e.write_cr_enable := '1';
895 v.e.write_cr_mask := num_to_fxm(crnum);
896 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
897 newcrf & newcrf & newcrf & newcrf;
899 if random_err = '0' then
900 case e_in.insn(17 downto 16) is
902 result := x"00000000" & random_cond(31 downto 0);
904 result := random_raw;
906 result := random_cond;
909 result := (others => '1');
916 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
917 "=" & to_hstring(a_in);
919 if is_fast_spr(e_in.read_reg1) then
921 if decode_spr_num(e_in.insn) = SPR_XER then
922 -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
923 result(63 downto 32) := (others => '0');
924 result(63-32) := v.e.xerc.so;
925 result(63-33) := v.e.xerc.ov;
926 result(63-34) := v.e.xerc.ca;
927 result(63-35 downto 63-43) := "000000000";
928 result(63-44) := v.e.xerc.ov32;
929 result(63-45) := v.e.xerc.ca32;
933 case decode_spr_num(e_in.insn) is
937 spr_val(63 downto 32) := (others => '0');
938 spr_val(31 downto 0) := ctrl.tb(63 downto 32);
942 spr_val := ctrl.cfar;
944 spr_val(63 downto 32) := (others => '0');
945 spr_val(31 downto 0) := PVR_MICROWATT;
946 when 724 => -- LOG_ADDR SPR
947 spr_val := log_wr_addr & r.log_addr_spr;
948 when 725 => -- LOG_DATA SPR
949 spr_val := log_rd_data;
950 v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
952 -- mfspr from unimplemented SPRs should be a nop in
953 -- supervisor mode and a program interrupt for user mode
954 if ctrl.msr(MSR_PR) = '1' then
961 if e_in.insn(20) = '0' then
963 result := x"00000000" & cr_in;
966 crnum := fxm_to_num(insn_fxm(e_in.insn));
967 result := (others => '0');
972 result(hi downto lo) := cr_in(hi downto lo);
978 v.e.write_cr_enable := '1';
979 if e_in.insn(20) = '0' then
981 v.e.write_cr_mask := insn_fxm(e_in.insn);
983 -- mtocrf: We require one hot priority encoding here
984 crnum := fxm_to_num(insn_fxm(e_in.insn));
985 v.e.write_cr_mask := num_to_fxm(crnum);
987 v.e.write_cr_data := c_in(31 downto 0);
989 if e_in.insn(16) = '1' then
990 -- just update EE and RI
991 ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
992 ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
994 -- Architecture says to leave out bits 3 (HV), 51 (ME)
995 -- and 63 (LE) (IBM bit numbering)
996 if e_in.is_32bit = '0' then
997 ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
998 ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
1000 ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1001 ctrl_tmp.msr(11 downto 1) <= c_in(11 downto 1);
1002 if c_in(MSR_PR) = '1' then
1003 ctrl_tmp.msr(MSR_EE) <= '1';
1004 ctrl_tmp.msr(MSR_IR) <= '1';
1005 ctrl_tmp.msr(MSR_DR) <= '1';
1008 v.fp_exception_next := fp_in.exception and
1009 (c_in(MSR_FE0) or c_in(MSR_FE1));
1013 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1014 "=" & to_hstring(c_in);
1015 if is_fast_spr(e_in.write_reg) then
1018 if decode_spr_num(e_in.insn) = SPR_XER then
1019 v.e.xerc.so := c_in(63-32);
1020 v.e.xerc.ov := c_in(63-33);
1021 v.e.xerc.ca := c_in(63-34);
1022 v.e.xerc.ov32 := c_in(63-44);
1023 v.e.xerc.ca32 := c_in(63-45);
1024 v.e.write_xerc_enable := '1';
1028 case decode_spr_num(e_in.insn) is
1030 ctrl_tmp.dec <= c_in;
1031 when 724 => -- LOG_ADDR SPR
1032 v.log_addr_spr := c_in(31 downto 0);
1034 -- mtspr to unimplemented SPRs should be a nop in
1035 -- supervisor mode and a program interrupt for user mode
1036 if ctrl.msr(MSR_PR) = '1' then
1041 when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1042 result := rotator_result;
1043 if e_in.output_carry = '1' then
1044 set_carry(v.e, rotator_carry, rotator_carry);
1048 bfa := insn_bfa(e_in.insn);
1049 crbit := to_integer(unsigned(bfa)) * 4;
1050 result := (others => '0');
1051 if cr_in(31 - crbit) = '1' then
1052 result := (others => '1');
1053 elsif cr_in(30 - crbit) = '1' then
1058 v.f.redirect := '1';
1059 v.f.redirect_nia := next_nia;
1062 icache_inval <= '1';
1064 when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1066 v.mul_in_progress := '1';
1068 x_to_multiply.valid <= '1';
1070 when OP_DIV | OP_DIVE | OP_MOD =>
1072 v.div_in_progress := '1';
1074 x_to_divider.valid <= '1';
1081 v.e.rc := e_in.rc and valid_in;
1083 -- Mispredicted branches cause a redirect
1084 if is_branch = '1' then
1085 if taken_branch = '1' then
1086 ctrl_tmp.cfar <= e_in.nia;
1088 if e_in.br_pred = '0' then
1089 if abs_branch = '1' then
1090 v.f.redirect_nia := b_in;
1092 v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
1095 v.f.redirect_nia := next_nia;
1097 if taken_branch /= e_in.br_pred then
1098 v.f.redirect := '1';
1102 -- Update LR on the next cycle after a branch link
1103 -- If we're not writing back anything else, we can write back LR
1104 -- this cycle, otherwise we take an extra cycle. We use the
1105 -- exc_write path since next_nia is written through that path
1107 if e_in.lr = '1' then
1108 if result_en = '0' then
1109 v.e.exc_write_enable := '1';
1110 v.e.exc_write_data := next_nia;
1111 v.e.exc_write_reg := fast_spr_num(SPR_LR);
1114 v.next_lr := next_nia;
1116 report "Delayed LR update to " & to_hstring(next_nia);
1121 elsif valid_in = '1' then
1122 -- instruction for other units, i.e. LDST
1123 if e_in.unit = LDST then
1125 elsif e_in.unit = NONE then
1127 elsif HAS_FPU and e_in.unit = FPU then
1130 -- Handling an ITLB miss doesn't count as having executed an instruction
1131 if e_in.insn_type = OP_FETCH_FAILED then
1136 -- The following cases all occur when r.busy = 1 and therefore
1137 -- valid_in = 0. Hence they don't happen in the same cycle as any of
1138 -- the cases above which depend on valid_in = 1.
1140 if r.f.redirect = '1' then
1143 if r.lr_update = '1' then
1144 v.e.exc_write_enable := '1';
1145 v.e.exc_write_data := r.next_lr;
1146 v.e.exc_write_reg := fast_spr_num(SPR_LR);
1148 elsif r.cntz_in_progress = '1' then
1149 -- cnt[lt]z always takes two cycles
1150 result := countzero_result;
1152 v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1153 v.e.rc := r.slow_op_rc;
1154 v.e.xerc := r.slow_op_xerc;
1156 elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1157 if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1158 (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1159 if r.mul_in_progress = '1' then
1161 case r.slow_op_insn is
1163 result := multiply_to_x.result(63 downto 32) &
1164 multiply_to_x.result(63 downto 32);
1166 result := multiply_to_x.result(127 downto 64);
1169 result := multiply_to_x.result(63 downto 0);
1172 result := divider_to_x.write_reg_data;
1173 overflow := divider_to_x.overflow;
1175 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1176 -- have to wait until next cycle for overflow indication
1177 v.mul_finish := '1';
1181 v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1182 v.e.rc := r.slow_op_rc;
1183 v.e.xerc := r.slow_op_xerc;
1184 v.e.write_xerc_enable := r.slow_op_oe;
1185 -- We must test oe because the RC update code in writeback
1186 -- will use the xerc value to set CR0:SO so we must not clobber
1187 -- xerc if OE wasn't set.
1188 if r.slow_op_oe = '1' then
1189 v.e.xerc.ov := overflow;
1190 v.e.xerc.ov32 := overflow;
1191 v.e.xerc.so := r.slow_op_xerc.so or overflow;
1197 v.mul_in_progress := r.mul_in_progress;
1198 v.div_in_progress := r.div_in_progress;
1200 elsif r.mul_finish = '1' then
1201 result := r.e.write_data;
1203 v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1204 v.e.rc := r.slow_op_rc;
1205 v.e.xerc := r.slow_op_xerc;
1206 v.e.write_xerc_enable := r.slow_op_oe;
1207 v.e.xerc.ov := multiply_to_x.overflow;
1208 v.e.xerc.ov32 := multiply_to_x.overflow;
1209 v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1213 -- Generate FP-type program interrupt. fp_in.interrupt will only
1214 -- be set during the execution of a FP instruction.
1215 -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1216 -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1217 if HAS_FPU and fp_in.interrupt = '1' then
1218 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1219 ctrl_tmp.srr1(63 - 43) <= '1';
1223 if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1225 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1226 -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1227 -- set bit 44 to indicate we have an illegal
1228 ctrl_tmp.srr1(63 - 44) <= '1';
1231 if exception = '1' then
1232 v.e.exc_write_enable := '1';
1233 if exception_nextpc = '1' then
1234 v.e.exc_write_data := next_nia;
1238 if do_trace = '1' then
1239 v.trace_next := '1';
1242 v.e.write_data := result;
1243 v.e.write_enable := result_en and not exception;
1245 -- generate DSI or DSegI for load/store exceptions
1246 -- or ISI or ISegI for instruction fetch exceptions
1247 if l_in.exception = '1' then
1248 if l_in.alignment = '1' then
1249 v.f.redirect_nia := std_logic_vector(to_unsigned(16#600#, 64));
1250 elsif l_in.instr_fault = '0' then
1251 if l_in.segment_fault = '0' then
1252 v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1254 v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1257 if l_in.segment_fault = '0' then
1258 ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1259 ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1260 ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1261 ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1262 v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1264 v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1267 v.e.exc_write_enable := '1';
1268 v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1269 report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1272 if exception = '1' or l_in.exception = '1' then
1273 ctrl_tmp.irq_state <= WRITE_SRR1;
1274 v.f.redirect := '1';
1275 v.f.virt_mode := '0';
1276 v.f.priv_mode := '1';
1277 -- XXX need an interrupt LE bit here, e.g. from LPCR
1278 v.f.big_endian := '0';
1279 v.f.mode_32bit := '0';
1282 if v.f.redirect = '1' then
1287 -- Outputs to loadstore1 (async)
1288 lv.op := e_in.insn_type;
1293 lv.write_reg := e_in.write_reg;
1294 lv.length := e_in.data_len;
1295 lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1296 lv.sign_extend := e_in.sign_extend;
1297 lv.update := e_in.update;
1298 lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1299 lv.xerc := v.e.xerc;
1300 lv.reserve := e_in.reserve;
1302 lv.insn := e_in.insn;
1303 -- decode l*cix and st*cix instructions here
1304 if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1305 e_in.insn(5 downto 1) = "10101" then
1308 lv.virt_mode := ctrl.msr(MSR_DR);
1309 lv.priv_mode := not ctrl.msr(MSR_PR);
1310 lv.mode_32bit := not ctrl.msr(MSR_SF);
1311 lv.is_32bit := e_in.is_32bit;
1314 fv.op := e_in.insn_type;
1316 fv.insn := e_in.insn;
1317 fv.single := e_in.is_32bit;
1318 fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1322 fv.frt := e_in.write_reg;
1324 fv.out_cr := e_in.output_cr;
1334 flush_out <= f_out.redirect;
1336 exception_log <= exception;
1337 irq_valid_log <= irq_valid;
1340 e1_log: if LOG_LENGTH > 0 generate
1341 signal log_data : std_ulogic_vector(14 downto 0);
1343 ex1_log : process(clk)
1345 if rising_edge(clk) then
1346 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1347 ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1350 std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1359 log_out <= log_data;
1361 end architecture behaviour;