2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.crhelpers.all;
10 use work.insn_helpers.all;
11 use work.ppc_fx_insns.all;
15 EX1_BYPASS : boolean := true
22 flush_out : out std_ulogic;
23 busy_out : out std_ulogic;
25 e_in : in Decode2ToExecute1Type;
26 l_in : in Loadstore1ToExecute1Type;
28 ext_irq_in : std_ulogic;
31 l_out : out Execute1ToLoadstore1Type;
32 f_out : out Execute1ToFetch1Type;
34 e_out : out Execute1ToWritebackType;
36 dbg_msr_out : out std_ulogic_vector(63 downto 0);
38 icache_inval : out std_ulogic;
39 terminate_out : out std_ulogic;
41 log_out : out std_ulogic_vector(14 downto 0);
42 log_rd_addr : out std_ulogic_vector(31 downto 0);
43 log_rd_data : in std_ulogic_vector(63 downto 0);
44 log_wr_addr : in std_ulogic_vector(31 downto 0)
48 architecture behaviour of execute1 is
49 type reg_type is record
50 e : Execute1ToWritebackType;
52 terminate: std_ulogic;
53 lr_update : std_ulogic;
54 next_lr : std_ulogic_vector(63 downto 0);
55 mul_in_progress : std_ulogic;
56 div_in_progress : std_ulogic;
57 cntz_in_progress : std_ulogic;
58 slow_op_insn : insn_type_t;
59 slow_op_dest : gpr_index_t;
60 slow_op_rc : std_ulogic;
61 slow_op_oe : std_ulogic;
62 slow_op_xerc : xer_common_t;
63 last_nia : std_ulogic_vector(63 downto 0);
64 log_addr_spr : std_ulogic_vector(31 downto 0);
66 constant reg_type_init : reg_type :=
67 (e => Execute1ToWritebackInit, busy => '0', lr_update => '0', terminate => '0',
68 mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
69 slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
70 next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
72 signal r, rin : reg_type;
74 signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
76 signal valid_in : std_ulogic;
77 signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
78 signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
79 signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
80 signal rot_sign_ext: std_ulogic;
81 signal rotator_result: std_ulogic_vector(63 downto 0);
82 signal rotator_carry: std_ulogic;
83 signal logical_result: std_ulogic_vector(63 downto 0);
84 signal countzero_result: std_ulogic_vector(63 downto 0);
87 signal x_to_multiply: Execute1ToMultiplyType;
88 signal multiply_to_x: MultiplyToExecute1Type;
91 signal x_to_divider: Execute1ToDividerType;
92 signal divider_to_x: DividerToExecute1Type;
94 -- signals for logging
95 signal exception_log : std_ulogic;
96 signal irq_valid_log : std_ulogic;
97 signal log_data : std_ulogic_vector(14 downto 0);
99 type privilege_level is (USER, SUPER);
100 type op_privilege_array is array(insn_type_t) of privilege_level;
101 constant op_privilege: op_privilege_array := (
110 function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
113 if op_privilege(op) = SUPER then
115 elsif op = OP_MFSPR or op = OP_MTSPR then
116 return insn(20) = '1';
122 procedure set_carry(e: inout Execute1ToWritebackType;
123 carry32 : in std_ulogic;
124 carry : in std_ulogic) is
126 e.xerc.ca32 := carry32;
128 e.write_xerc_enable := '1';
131 procedure set_ov(e: inout Execute1ToWritebackType;
133 ov32 : in std_ulogic) is
140 e.write_xerc_enable := '1';
143 function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
144 ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
146 return (ca xor msb_r) and not (msb_a xor msb_b);
149 function decode_input_carry(ic : carry_in_t;
150 xerc : xer_common_t) return std_ulogic is
162 function msr_copy(msr: std_ulogic_vector(63 downto 0))
163 return std_ulogic_vector is
164 variable msr_out: std_ulogic_vector(63 downto 0);
167 -- Defined MSR bits are classified as either full func-
168 -- tion or partial function. Full function MSR bits are
169 -- saved in SRR1 or HSRR1 when an interrupt other
170 -- than a System Call Vectored interrupt occurs and
171 -- restored by rfscv, rfid, or hrfid, while partial func-
172 -- tion MSR bits are not saved or restored.
173 -- Full function MSR bits lie in the range 0:32, 37:41, and
174 -- 48:63, and partial function MSR bits lie in the range
175 -- 33:36 and 42:47. (Note this is IBM bit numbering).
176 msr_out := (others => '0');
177 msr_out(63 downto 31) := msr(63 downto 31);
178 msr_out(26 downto 22) := msr(26 downto 22);
179 msr_out(15 downto 0) := msr(15 downto 0);
185 rotator_0: entity work.rotator
189 shift => b_in(6 downto 0),
191 is_32bit => e_in.is_32bit,
192 right_shift => right_shift,
193 arith => e_in.is_signed,
194 clear_left => rot_clear_left,
195 clear_right => rot_clear_right,
196 sign_ext_rs => rot_sign_ext,
197 result => rotator_result,
198 carry_out => rotator_carry
201 logical_0: entity work.logical
205 op => e_in.insn_type,
206 invert_in => e_in.invert_a,
207 invert_out => e_in.invert_out,
208 result => logical_result,
209 datalen => e_in.data_len
212 countzero_0: entity work.zero_counter
216 count_right => e_in.insn(10),
217 is_32bit => e_in.is_32bit,
218 result => countzero_result
221 multiply_0: entity work.multiply
224 m_in => x_to_multiply,
225 m_out => multiply_to_x
228 divider_0: entity work.divider
232 d_in => x_to_divider,
233 d_out => divider_to_x
236 dbg_msr_out <= ctrl.msr;
237 log_rd_addr <= r.log_addr_spr;
239 a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
240 b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
241 c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
243 busy_out <= l_in.busy or r.busy;
244 valid_in <= e_in.valid and not busy_out;
246 terminate_out <= r.terminate;
248 execute1_0: process(clk)
250 if rising_edge(clk) then
253 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
254 ctrl.irq_state <= WRITE_SRR0;
258 assert not (r.lr_update = '1' and valid_in = '1')
259 report "LR update collision with valid in EX1"
261 if r.lr_update = '1' then
262 report "LR update to " & to_hstring(r.next_lr);
268 execute1_1: process(all)
269 variable v : reg_type;
270 variable a_inv : std_ulogic_vector(63 downto 0);
271 variable result : std_ulogic_vector(63 downto 0);
272 variable newcrf : std_ulogic_vector(3 downto 0);
273 variable result_with_carry : std_ulogic_vector(64 downto 0);
274 variable result_en : std_ulogic;
275 variable crnum : crnum_t;
276 variable crbit : integer range 0 to 31;
277 variable scrnum : crnum_t;
278 variable lo, hi : integer;
279 variable sh, mb, me : std_ulogic_vector(5 downto 0);
280 variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
281 variable bo, bi : std_ulogic_vector(4 downto 0);
282 variable bf, bfa : std_ulogic_vector(2 downto 0);
283 variable cr_op : std_ulogic_vector(9 downto 0);
284 variable cr_operands : std_ulogic_vector(1 downto 0);
285 variable bt, ba, bb : std_ulogic_vector(4 downto 0);
286 variable btnum, banum, bbnum : integer range 0 to 31;
287 variable crresult : std_ulogic;
288 variable l : std_ulogic;
289 variable next_nia : std_ulogic_vector(63 downto 0);
290 variable carry_32, carry_64 : std_ulogic;
291 variable sign1, sign2 : std_ulogic;
292 variable abs1, abs2 : signed(63 downto 0);
293 variable overflow : std_ulogic;
294 variable zerohi, zerolo : std_ulogic;
295 variable msb_a, msb_b : std_ulogic;
296 variable a_lt : std_ulogic;
297 variable lv : Execute1ToLoadstore1Type;
298 variable irq_valid : std_ulogic;
299 variable exception : std_ulogic;
300 variable exception_nextpc : std_ulogic;
301 variable trapval : std_ulogic_vector(4 downto 0);
302 variable illegal : std_ulogic;
303 variable is_branch : std_ulogic;
304 variable taken_branch : std_ulogic;
305 variable abs_branch : std_ulogic;
306 variable spr_val : std_ulogic_vector(63 downto 0);
308 result := (others => '0');
309 result_with_carry := (others => '0');
311 newcrf := (others => '0');
317 v.e := Execute1ToWritebackInit;
318 lv := Execute1ToLoadstore1Init;
320 -- XER forwarding. To avoid having to track XER hazards, we
321 -- use the previously latched value.
323 -- If the XER was modified by a multiply or a divide, those are
324 -- single issue, we'll get the up to date value from decode2 from
325 -- the register file.
327 -- If it was modified by an instruction older than the previous
328 -- one in EX1, it will have also hit writeback and will be up
329 -- to date in decode2.
331 -- That leaves us with the case where it was updated by the previous
332 -- instruction in EX1. In that case, we can forward it back here.
334 -- This will break if we allow pipelining of multiply and divide,
335 -- but ideally, those should go via EX1 anyway and run as a state
336 -- machine from here.
338 -- One additional hazard to beware of is an XER:SO modifying instruction
339 -- in EX1 followed immediately by a store conditional. Due to our
340 -- writeback latency, the store will go down the LSU with the previous
341 -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
343 -- We will need to handle that if we ever make stcx. not single issue
345 -- We always pass a valid XER value downto writeback even when
346 -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
347 -- to work for RC instructions.
349 if r.e.write_xerc_enable = '1' then
350 v.e.xerc := r.e.xerc;
352 v.e.xerc := e_in.xerc;
356 v.mul_in_progress := '0';
357 v.div_in_progress := '0';
358 v.cntz_in_progress := '0';
360 -- signals to multiply and divide units
363 if e_in.is_signed = '1' then
364 if e_in.is_32bit = '1' then
372 -- take absolute values
374 abs1 := signed(a_in);
376 abs1 := - signed(a_in);
379 abs2 := signed(b_in);
381 abs2 := - signed(b_in);
384 x_to_multiply <= Execute1ToMultiplyInit;
385 x_to_multiply.is_32bit <= e_in.is_32bit;
387 x_to_divider <= Execute1ToDividerInit;
388 x_to_divider.is_signed <= e_in.is_signed;
389 x_to_divider.is_32bit <= e_in.is_32bit;
390 if e_in.insn_type = OP_MOD then
391 x_to_divider.is_modulus <= '1';
394 x_to_multiply.neg_result <= sign1 xor sign2;
395 x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
396 if e_in.is_32bit = '0' then
398 x_to_multiply.data1 <= std_ulogic_vector(abs1);
399 x_to_multiply.data2 <= std_ulogic_vector(abs2);
400 if e_in.insn_type = OP_DIVE then
401 x_to_divider.is_extended <= '1';
403 x_to_divider.dividend <= std_ulogic_vector(abs1);
404 x_to_divider.divisor <= std_ulogic_vector(abs2);
407 x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
408 x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
409 x_to_divider.is_extended <= '0';
410 if e_in.insn_type = OP_DIVE then -- extended forms
411 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
413 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
415 x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
419 -- FIXME: run at 512MHz not core freq
420 ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
421 ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
424 if ctrl.msr(MSR_EE) = '1' then
425 if ctrl.dec(63) = '1' then
426 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
427 report "IRQ valid: DEC";
429 elsif ext_irq_in = '1' then
430 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#500#, 64));
431 report "IRQ valid: External";
439 f_out <= Execute1ToFetch1TypeInit;
440 -- send MSR[IR] and ~MSR[PR] up to fetch1
441 f_out.virt_mode <= ctrl.msr(MSR_IR);
442 f_out.priv_mode <= not ctrl.msr(MSR_PR);
444 -- Next insn adder used in a couple of places
445 next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
447 -- rotator control signals
448 right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
449 rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
450 rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
451 rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
453 ctrl_tmp.irq_state <= WRITE_SRR0;
456 exception_nextpc := '0';
457 v.e.exc_write_enable := '0';
458 v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
459 v.e.exc_write_data := e_in.nia;
460 if valid_in = '1' then
461 v.last_nia := e_in.nia;
464 if ctrl.irq_state = WRITE_SRR1 then
465 v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
466 v.e.exc_write_data := ctrl.srr1;
467 v.e.exc_write_enable := '1';
468 ctrl_tmp.msr(MSR_SF) <= '1';
469 ctrl_tmp.msr(MSR_EE) <= '0';
470 ctrl_tmp.msr(MSR_PR) <= '0';
471 ctrl_tmp.msr(MSR_IR) <= '0';
472 ctrl_tmp.msr(MSR_DR) <= '0';
473 ctrl_tmp.msr(MSR_RI) <= '0';
474 ctrl_tmp.msr(MSR_LE) <= '1';
475 f_out.redirect <= '1';
476 f_out.virt_mode <= '0';
477 f_out.priv_mode <= '1';
478 f_out.redirect_nia <= ctrl.irq_nia;
480 report "Writing SRR1: " & to_hstring(ctrl.srr1);
482 elsif irq_valid = '1' and valid_in = '1' then
483 -- we need two cycles to write srr0 and 1
484 -- will need more when we have to write HEIR
485 -- Don't deliver the interrupt until we have a valid instruction
486 -- coming in, so we have a valid NIA to put in SRR0.
488 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
490 elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
491 instr_is_privileged(e_in.insn_type, e_in.insn) then
492 -- generate a program interrupt
494 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
495 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
496 -- set bit 45 to indicate privileged instruction type interrupt
497 ctrl_tmp.srr1(63 - 45) <= '1';
498 report "privileged instruction";
500 elsif valid_in = '1' and e_in.unit = ALU then
502 report "execute nia " & to_hstring(e_in.nia);
505 v.e.write_reg := e_in.write_reg;
506 v.slow_op_insn := e_in.insn_type;
507 v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
508 v.slow_op_rc := e_in.rc;
509 v.slow_op_oe := e_in.oe;
510 v.slow_op_xerc := v.e.xerc;
512 case_0: case e_in.insn_type is
515 -- we need two cycles to write srr0 and 1
516 -- will need more when we have to write HEIR
519 -- check bit 1 of the instruction is 1 so we know this is sc;
520 -- 0 would mean scv, so generate an illegal instruction interrupt
521 -- we need two cycles to write srr0 and 1
522 if e_in.insn(1) = '1' then
524 exception_nextpc := '1';
525 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
526 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
532 -- check bits 1-10 of the instruction to make sure it's attn
533 -- if not then it is illegal
534 if e_in.insn(10 downto 1) = "0100000000" then
542 when OP_ADD | OP_CMP | OP_TRAP =>
543 if e_in.invert_a = '0' then
548 result_with_carry := ppc_adde(a_inv, b_in,
549 decode_input_carry(e_in.input_carry, v.e.xerc));
550 result := result_with_carry(63 downto 0);
551 carry_32 := result(32) xor a_inv(32) xor b_in(32);
552 carry_64 := result_with_carry(64);
553 if e_in.insn_type = OP_ADD then
554 if e_in.output_carry = '1' then
555 set_carry(v.e, carry_32, carry_64);
557 if e_in.oe = '1' then
559 calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
560 calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
564 -- trap, CMP and CMPL instructions
565 -- Note, we have done RB - RA, not RA - RB
566 if e_in.insn_type = OP_CMP then
567 l := insn_l(e_in.insn);
569 l := not e_in.is_32bit;
571 zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
572 zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
573 if zerolo = '1' and (l = '0' or zerohi = '1') then
586 if msb_a /= msb_b then
587 -- Subtraction might overflow, but
588 -- comparison is clear from MSB difference.
589 -- for signed, 0 is greater; for unsigned, 1 is greater
590 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
592 -- Subtraction cannot overflow since MSBs are equal.
593 -- carry = 1 indicates RA is smaller (signed or unsigned)
594 a_lt := (not l and carry_32) or (l and carry_64);
595 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
598 if e_in.insn_type = OP_CMP then
599 if e_in.is_signed = '1' then
600 newcrf := trapval(4 downto 2) & v.e.xerc.so;
602 newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
604 bf := insn_bf(e_in.insn);
605 crnum := to_integer(unsigned(bf));
606 v.e.write_cr_enable := '1';
607 v.e.write_cr_mask := num_to_fxm(crnum);
611 v.e.write_cr_data(hi downto lo) := newcrf;
614 -- trap instructions (tw, twi, td, tdi)
615 if or (trapval and insn_to(e_in.insn)) = '1' then
616 -- generate trap-type program interrupt
618 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
619 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
620 -- set bit 46 to say trap occurred
621 ctrl_tmp.srr1(63 - 46) <= '1';
626 when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS =>
627 result := logical_result;
632 abs_branch := insn_aa(e_in.insn);
635 bo := insn_bo(e_in.insn);
636 bi := insn_bi(e_in.insn);
637 if bo(4-2) = '0' then
638 result := std_ulogic_vector(unsigned(a_in) - 1);
640 v.e.write_reg := fast_spr_num(SPR_CTR);
643 taken_branch := ppc_bc_taken(bo, bi, e_in.cr, a_in);
644 abs_branch := insn_aa(e_in.insn);
647 -- read_data2 is target register (CTR, LR or TAR)
648 bo := insn_bo(e_in.insn);
649 bi := insn_bi(e_in.insn);
650 if bo(4-2) = '0' and e_in.insn(10) = '0' then
651 result := std_ulogic_vector(unsigned(a_in) - 1);
653 v.e.write_reg := fast_spr_num(SPR_CTR);
655 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = '1' then
656 f_out.redirect <= '1';
657 f_out.redirect_nia <= b_in(63 downto 2) & "00";
661 f_out.redirect <= '1';
662 f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
663 f_out.priv_mode <= not b_in(MSR_PR);
664 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
665 -- Can't use msr_copy here because the partial function MSR
666 -- bits should be left unchanged, not zeroed.
667 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
668 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
669 ctrl_tmp.msr(15 downto 0) <= b_in(15 downto 0);
670 if b_in(MSR_PR) = '1' then
671 ctrl_tmp.msr(MSR_EE) <= '1';
672 ctrl_tmp.msr(MSR_IR) <= '1';
673 ctrl_tmp.msr(MSR_DR) <= '1';
678 v.cntz_in_progress := '1';
681 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
682 if e_in.cr(31-crbit) = '1' then
689 cr_op := insn_cr(e_in.insn);
690 report "CR OP " & to_hstring(cr_op);
691 if cr_op(0) = '0' then -- MCRF
692 bf := insn_bf(e_in.insn);
693 bfa := insn_bfa(e_in.insn);
694 v.e.write_cr_enable := '1';
695 crnum := to_integer(unsigned(bf));
696 scrnum := to_integer(unsigned(bfa));
697 v.e.write_cr_mask := num_to_fxm(crnum);
702 newcrf := e_in.cr(hi downto lo);
708 v.e.write_cr_data(hi downto lo) := newcrf;
711 v.e.write_cr_enable := '1';
712 bt := insn_bt(e_in.insn);
713 ba := insn_ba(e_in.insn);
714 bb := insn_bb(e_in.insn);
715 btnum := 31 - to_integer(unsigned(bt));
716 banum := 31 - to_integer(unsigned(ba));
717 bbnum := 31 - to_integer(unsigned(bb));
718 -- Bits 5-8 of cr_op give the truth table of the requested
720 cr_operands := e_in.cr(banum) & e_in.cr(bbnum);
721 crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
722 v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
723 for i in 0 to 31 loop
725 v.e.write_cr_data(i) := crresult;
727 v.e.write_cr_data(i) := e_in.cr(i);
735 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
736 "=" & to_hstring(a_in);
738 if is_fast_spr(e_in.read_reg1) then
740 if decode_spr_num(e_in.insn) = SPR_XER then
741 -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
742 result(63 downto 32) := (others => '0');
743 result(63-32) := v.e.xerc.so;
744 result(63-33) := v.e.xerc.ov;
745 result(63-34) := v.e.xerc.ca;
746 result(63-35 downto 63-43) := "000000000";
747 result(63-44) := v.e.xerc.ov32;
748 result(63-45) := v.e.xerc.ca32;
752 case decode_spr_num(e_in.insn) is
756 spr_val(63 downto 32) := (others => '0');
757 spr_val(31 downto 0) := ctrl.tb(63 downto 32);
760 when 724 => -- LOG_ADDR SPR
761 spr_val := log_wr_addr & r.log_addr_spr;
762 when 725 => -- LOG_DATA SPR
763 spr_val := log_rd_data;
764 v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
766 -- mfspr from unimplemented SPRs should be a nop in
767 -- supervisor mode and a program interrupt for user mode
768 if ctrl.msr(MSR_PR) = '1' then
775 if e_in.insn(20) = '0' then
777 result := x"00000000" & e_in.cr;
780 crnum := fxm_to_num(insn_fxm(e_in.insn));
781 result := (others => '0');
786 result(hi downto lo) := e_in.cr(hi downto lo);
792 v.e.write_cr_enable := '1';
793 if e_in.insn(20) = '0' then
795 v.e.write_cr_mask := insn_fxm(e_in.insn);
797 -- mtocrf: We require one hot priority encoding here
798 crnum := fxm_to_num(insn_fxm(e_in.insn));
799 v.e.write_cr_mask := num_to_fxm(crnum);
801 v.e.write_cr_data := c_in(31 downto 0);
803 if e_in.insn(16) = '1' then
804 -- just update EE and RI
805 ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
806 ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
808 -- Architecture says to leave out bits 3 (HV), 51 (ME)
809 -- and 63 (LE) (IBM bit numbering)
810 ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
811 ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
812 ctrl_tmp.msr(11 downto 1) <= c_in(11 downto 1);
813 if c_in(MSR_PR) = '1' then
814 ctrl_tmp.msr(MSR_EE) <= '1';
815 ctrl_tmp.msr(MSR_IR) <= '1';
816 ctrl_tmp.msr(MSR_DR) <= '1';
820 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
821 "=" & to_hstring(c_in);
822 if is_fast_spr(e_in.write_reg) then
825 if decode_spr_num(e_in.insn) = SPR_XER then
826 v.e.xerc.so := c_in(63-32);
827 v.e.xerc.ov := c_in(63-33);
828 v.e.xerc.ca := c_in(63-34);
829 v.e.xerc.ov32 := c_in(63-44);
830 v.e.xerc.ca32 := c_in(63-45);
831 v.e.write_xerc_enable := '1';
835 case decode_spr_num(e_in.insn) is
837 ctrl_tmp.dec <= c_in;
838 when 724 => -- LOG_ADDR SPR
839 v.log_addr_spr := c_in(31 downto 0);
841 -- mtspr to unimplemented SPRs should be a nop in
842 -- supervisor mode and a program interrupt for user mode
843 if ctrl.msr(MSR_PR) = '1' then
848 when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
849 result := rotator_result;
850 if e_in.output_carry = '1' then
851 set_carry(v.e, rotator_carry, rotator_carry);
856 f_out.redirect <= '1';
857 f_out.redirect_nia <= next_nia;
862 when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
864 v.mul_in_progress := '1';
866 x_to_multiply.valid <= '1';
868 when OP_DIV | OP_DIVE | OP_MOD =>
870 v.div_in_progress := '1';
872 x_to_divider.valid <= '1';
879 v.e.rc := e_in.rc and valid_in;
881 -- Mispredicted branches cause a redirect
882 if is_branch = '1' and taken_branch /= e_in.br_pred then
883 f_out.redirect <= '1';
884 if taken_branch = '1' then
885 if abs_branch = '1' then
886 f_out.redirect_nia <= b_in;
888 f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
891 f_out.redirect_nia <= next_nia;
895 -- Update LR on the next cycle after a branch link
896 -- If we're not writing back anything else, we can write back LR
897 -- this cycle, otherwise we take an extra cycle. We use the
898 -- exc_write path since next_nia is written through that path
900 if e_in.lr = '1' then
901 if result_en = '0' then
902 v.e.exc_write_enable := '1';
903 v.e.exc_write_data := next_nia;
904 v.e.exc_write_reg := fast_spr_num(SPR_LR);
907 v.next_lr := next_nia;
909 report "Delayed LR update to " & to_hstring(next_nia);
914 elsif valid_in = '1' then
915 -- instruction for other units, i.e. LDST
916 if e_in.unit = LDST then
920 elsif r.lr_update = '1' then
921 v.e.exc_write_enable := '1';
922 v.e.exc_write_data := r.next_lr;
923 v.e.exc_write_reg := fast_spr_num(SPR_LR);
925 elsif r.cntz_in_progress = '1' then
926 -- cnt[lt]z always takes two cycles
927 result := countzero_result;
929 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
930 v.e.rc := v.slow_op_rc;
931 v.e.xerc := v.slow_op_xerc;
933 elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
934 if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
935 (r.div_in_progress = '1' and divider_to_x.valid = '1') then
936 if r.mul_in_progress = '1' then
938 case r.slow_op_insn is
940 result := multiply_to_x.result(63 downto 32) &
941 multiply_to_x.result(63 downto 32);
943 result := multiply_to_x.result(127 downto 64);
946 result := multiply_to_x.result(63 downto 0);
947 overflow := multiply_to_x.overflow;
950 result := divider_to_x.write_reg_data;
951 overflow := divider_to_x.overflow;
954 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
955 v.e.rc := v.slow_op_rc;
956 v.e.xerc := v.slow_op_xerc;
957 v.e.write_xerc_enable := v.slow_op_oe;
958 -- We must test oe because the RC update code in writeback
959 -- will use the xerc value to set CR0:SO so we must not clobber
960 -- xerc if OE wasn't set.
961 if v.slow_op_oe = '1' then
962 v.e.xerc.ov := overflow;
963 v.e.xerc.ov32 := overflow;
964 v.e.xerc.so := v.slow_op_xerc.so or overflow;
969 v.mul_in_progress := r.mul_in_progress;
970 v.div_in_progress := r.div_in_progress;
974 if illegal = '1' then
976 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
977 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
978 -- Since we aren't doing Hypervisor emulation assist (0xe40) we
979 -- set bit 44 to indicate we have an illegal
980 ctrl_tmp.srr1(63 - 44) <= '1';
983 if exception = '1' then
984 v.e.exc_write_enable := '1';
985 if exception_nextpc = '1' then
986 v.e.exc_write_data := next_nia;
988 ctrl_tmp.irq_state <= WRITE_SRR1;
993 v.e.write_data := result;
994 v.e.write_enable := result_en;
996 -- generate DSI or DSegI for load/store exceptions
997 -- or ISI or ISegI for instruction fetch exceptions
998 if l_in.exception = '1' then
999 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
1000 if l_in.instr_fault = '0' then
1001 if l_in.segment_fault = '0' then
1002 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#300#, 64));
1004 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#380#, 64));
1007 if l_in.segment_fault = '0' then
1008 ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1009 ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1010 ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1011 ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1012 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#400#, 64));
1014 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#480#, 64));
1017 v.e.exc_write_enable := '1';
1018 v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1019 v.e.exc_write_data := r.last_nia;
1020 report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1021 ctrl_tmp.irq_state <= WRITE_SRR1;
1024 -- Outputs to loadstore1 (async)
1025 lv.op := e_in.insn_type;
1030 lv.write_reg := gspr_to_gpr(e_in.write_reg);
1031 lv.length := e_in.data_len;
1032 lv.byte_reverse := e_in.byte_reverse;
1033 lv.sign_extend := e_in.sign_extend;
1034 lv.update := e_in.update;
1035 lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1036 lv.xerc := v.e.xerc;
1037 lv.reserve := e_in.reserve;
1039 lv.insn := e_in.insn;
1040 -- decode l*cix and st*cix instructions here
1041 if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1042 e_in.insn(5 downto 1) = "10101" then
1045 lv.virt_mode := ctrl.msr(MSR_DR);
1046 lv.priv_mode := not ctrl.msr(MSR_PR);
1055 flush_out <= f_out.redirect;
1057 exception_log <= exception;
1058 irq_valid_log <= irq_valid;
1061 ex1_log : process(clk)
1063 if rising_edge(clk) then
1064 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1065 ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1068 std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1077 log_out <= log_data;
1078 end architecture behaviour;