execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true
  16         );
  17     port (
  18         clk   : in std_ulogic;
  19         rst   : in std_ulogic;
  20
  21         -- asynchronous
  22         flush_out : out std_ulogic;
  23         busy_out : out std_ulogic;
  24
  25         e_in  : in Decode2ToExecute1Type;
  26         l_in  : in Loadstore1ToExecute1Type;
  27
  28         ext_irq_in : std_ulogic;
  29
  30         -- asynchronous
  31         l_out : out Execute1ToLoadstore1Type;
  32         f_out : out Execute1ToFetch1Type;
  33
  34         e_out : out Execute1ToWritebackType;
  35
  36         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  37
  38         icache_inval : out std_ulogic;
  39         terminate_out : out std_ulogic;
  40
  41         log_out : out std_ulogic_vector(14 downto 0);
  42         log_rd_addr : out std_ulogic_vector(31 downto 0);
  43         log_rd_data : in std_ulogic_vector(63 downto 0);
  44         log_wr_addr : in std_ulogic_vector(31 downto 0)
  45         );
  46 end entity execute1;
  47
  48 architecture behaviour of execute1 is
  49     type reg_type is record
  50         e : Execute1ToWritebackType;
  51         f : Execute1ToFetch1Type;
  52         busy: std_ulogic;
  53         terminate: std_ulogic;
  54         lr_update : std_ulogic;
  55         next_lr : std_ulogic_vector(63 downto 0);
  56         mul_in_progress : std_ulogic;
  57         div_in_progress : std_ulogic;
  58         cntz_in_progress : std_ulogic;
  59         slow_op_insn : insn_type_t;
  60         slow_op_dest : gpr_index_t;
  61         slow_op_rc : std_ulogic;
  62         slow_op_oe : std_ulogic;
  63         slow_op_xerc : xer_common_t;
  64         last_nia : std_ulogic_vector(63 downto 0);
  65         log_addr_spr : std_ulogic_vector(31 downto 0);
  66     end record;
  67     constant reg_type_init : reg_type :=
  68         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  69          busy => '0', lr_update => '0', terminate => '0',
  70          mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
  71          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  72          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  73
  74     signal r, rin : reg_type;
  75
  76     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  77     signal cr_in : std_ulogic_vector(31 downto 0);
  78
  79     signal valid_in : std_ulogic;
  80     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  81     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  82     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  83     signal rot_sign_ext: std_ulogic;
  84     signal rotator_result: std_ulogic_vector(63 downto 0);
  85     signal rotator_carry: std_ulogic;
  86     signal logical_result: std_ulogic_vector(63 downto 0);
  87     signal countzero_result: std_ulogic_vector(63 downto 0);
  88
  89     -- multiply signals
  90     signal x_to_multiply: Execute1ToMultiplyType;
  91     signal multiply_to_x: MultiplyToExecute1Type;
  92
  93     -- divider signals
  94     signal x_to_divider: Execute1ToDividerType;
  95     signal divider_to_x: DividerToExecute1Type;
  96
  97     -- signals for logging
  98     signal exception_log : std_ulogic;
  99     signal irq_valid_log : std_ulogic;
 100     signal log_data : std_ulogic_vector(14 downto 0);
 101
 102     type privilege_level is (USER, SUPER);
 103     type op_privilege_array is array(insn_type_t) of privilege_level;
 104     constant op_privilege: op_privilege_array := (
 105         OP_ATTN => SUPER,
 106         OP_MFMSR => SUPER,
 107         OP_MTMSRD => SUPER,
 108         OP_RFID => SUPER,
 109         OP_TLBIE => SUPER,
 110         others => USER
 111         );
 112
 113     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 114         return boolean is
 115     begin
 116         if op_privilege(op) = SUPER then
 117             return true;
 118         elsif op = OP_MFSPR or op = OP_MTSPR then
 119             return insn(20) = '1';
 120         else
 121             return false;
 122         end if;
 123     end;
 124
 125     procedure set_carry(e: inout Execute1ToWritebackType;
 126                         carry32 : in std_ulogic;
 127                         carry : in std_ulogic) is
 128     begin
 129         e.xerc.ca32 := carry32;
 130         e.xerc.ca := carry;
 131         e.write_xerc_enable := '1';
 132     end;
 133
 134     procedure set_ov(e: inout Execute1ToWritebackType;
 135                      ov   : in std_ulogic;
 136                      ov32 : in std_ulogic) is
 137     begin
 138         e.xerc.ov32 := ov32;
 139         e.xerc.ov := ov;
 140         if ov = '1' then
 141             e.xerc.so := '1';
 142         end if;
 143         e.write_xerc_enable := '1';
 144     end;
 145
 146     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 147                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 148     begin
 149         return (ca xor msb_r) and not (msb_a xor msb_b);
 150     end;
 151
 152     function decode_input_carry(ic : carry_in_t;
 153                                 xerc : xer_common_t) return std_ulogic is
 154     begin
 155         case ic is
 156         when ZERO =>
 157             return '0';
 158         when CA =>
 159             return xerc.ca;
 160         when ONE =>
 161             return '1';
 162         end case;
 163     end;
 164
 165     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 166         return std_ulogic_vector is
 167         variable msr_out: std_ulogic_vector(63 downto 0);
 168     begin
 169         -- ISA says this:
 170         --  Defined MSR bits are classified as either full func-
 171         --  tion or partial function. Full function MSR bits are
 172         --  saved in SRR1 or HSRR1 when an interrupt other
 173         --  than a System Call Vectored interrupt occurs and
 174         --  restored by rfscv, rfid, or hrfid, while partial func-
 175         --  tion MSR bits are not saved or restored.
 176         --  Full function MSR bits lie in the range 0:32, 37:41, and
 177         --  48:63, and partial function MSR bits lie in the range
 178         --  33:36 and 42:47. (Note this is IBM bit numbering).
 179         msr_out := (others => '0');
 180         msr_out(63 downto 31) := msr(63 downto 31);
 181         msr_out(26 downto 22) := msr(26 downto 22);
 182         msr_out(15 downto 0)  := msr(15 downto 0);
 183         return msr_out;
 184     end;
 185
 186 begin
 187
 188     rotator_0: entity work.rotator
 189         port map (
 190             rs => c_in,
 191             ra => a_in,
 192             shift => b_in(6 downto 0),
 193             insn => e_in.insn,
 194             is_32bit => e_in.is_32bit,
 195             right_shift => right_shift,
 196             arith => e_in.is_signed,
 197             clear_left => rot_clear_left,
 198             clear_right => rot_clear_right,
 199             sign_ext_rs => rot_sign_ext,
 200             result => rotator_result,
 201             carry_out => rotator_carry
 202             );
 203
 204     logical_0: entity work.logical
 205         port map (
 206             rs => c_in,
 207             rb => b_in,
 208             op => e_in.insn_type,
 209             invert_in => e_in.invert_a,
 210             invert_out => e_in.invert_out,
 211             result => logical_result,
 212             datalen => e_in.data_len
 213             );
 214
 215     countzero_0: entity work.zero_counter
 216         port map (
 217             clk => clk,
 218             rs => c_in,
 219             count_right => e_in.insn(10),
 220             is_32bit => e_in.is_32bit,
 221             result => countzero_result
 222             );
 223
 224     multiply_0: entity work.multiply
 225         port map (
 226             clk => clk,
 227             m_in => x_to_multiply,
 228             m_out => multiply_to_x
 229             );
 230
 231     divider_0: entity work.divider
 232         port map (
 233             clk => clk,
 234             rst => rst,
 235             d_in => x_to_divider,
 236             d_out => divider_to_x
 237             );
 238
 239     dbg_msr_out <= ctrl.msr;
 240     log_rd_addr <= r.log_addr_spr;
 241
 242     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 243     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 244     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 245
 246     busy_out <= l_in.busy or r.busy;
 247     valid_in <= e_in.valid and not busy_out;
 248
 249     terminate_out <= r.terminate;
 250
 251     execute1_0: process(clk)
 252     begin
 253         if rising_edge(clk) then
 254             if rst = '1' then
 255                 r <= reg_type_init;
 256                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 257                 ctrl.irq_state <= WRITE_SRR0;
 258             else
 259                 r <= rin;
 260                 ctrl <= ctrl_tmp;
 261                 assert not (r.lr_update = '1' and valid_in = '1')
 262                     report "LR update collision with valid in EX1"
 263                     severity failure;
 264                 if r.lr_update = '1' then
 265                     report "LR update to " & to_hstring(r.next_lr);
 266                 end if;
 267             end if;
 268         end if;
 269     end process;
 270
 271     execute1_1: process(all)
 272         variable v : reg_type;
 273         variable a_inv : std_ulogic_vector(63 downto 0);
 274         variable result : std_ulogic_vector(63 downto 0);
 275         variable newcrf : std_ulogic_vector(3 downto 0);
 276         variable result_with_carry : std_ulogic_vector(64 downto 0);
 277         variable result_en : std_ulogic;
 278         variable crnum : crnum_t;
 279         variable crbit : integer range 0 to 31;
 280         variable scrnum : crnum_t;
 281         variable lo, hi : integer;
 282         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 283         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 284         variable bo, bi : std_ulogic_vector(4 downto 0);
 285         variable bf, bfa : std_ulogic_vector(2 downto 0);
 286         variable cr_op : std_ulogic_vector(9 downto 0);
 287         variable cr_operands : std_ulogic_vector(1 downto 0);
 288         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 289         variable btnum, banum, bbnum : integer range 0 to 31;
 290         variable crresult : std_ulogic;
 291         variable l : std_ulogic;
 292         variable next_nia : std_ulogic_vector(63 downto 0);
 293         variable carry_32, carry_64 : std_ulogic;
 294         variable sign1, sign2 : std_ulogic;
 295         variable abs1, abs2 : signed(63 downto 0);
 296         variable overflow : std_ulogic;
 297         variable zerohi, zerolo : std_ulogic;
 298         variable msb_a, msb_b : std_ulogic;
 299         variable a_lt : std_ulogic;
 300         variable lv : Execute1ToLoadstore1Type;
 301         variable irq_valid : std_ulogic;
 302         variable exception : std_ulogic;
 303         variable exception_nextpc : std_ulogic;
 304         variable trapval : std_ulogic_vector(4 downto 0);
 305         variable illegal : std_ulogic;
 306         variable is_branch : std_ulogic;
 307         variable taken_branch : std_ulogic;
 308         variable abs_branch : std_ulogic;
 309         variable spr_val : std_ulogic_vector(63 downto 0);
 310     begin
 311         result := (others => '0');
 312         result_with_carry := (others => '0');
 313         result_en := '0';
 314         newcrf := (others => '0');
 315         is_branch := '0';
 316         taken_branch := '0';
 317         abs_branch := '0';
 318
 319         v := r;
 320         v.e := Execute1ToWritebackInit;
 321         lv := Execute1ToLoadstore1Init;
 322         v.f.redirect := '0';
 323
 324         -- XER forwarding. To avoid having to track XER hazards, we
 325         -- use the previously latched value.
 326         --
 327         -- If the XER was modified by a multiply or a divide, those are
 328         -- single issue, we'll get the up to date value from decode2 from
 329         -- the register file.
 330         --
 331         -- If it was modified by an instruction older than the previous
 332         -- one in EX1, it will have also hit writeback and will be up
 333         -- to date in decode2.
 334         --
 335         -- That leaves us with the case where it was updated by the previous
 336         -- instruction in EX1. In that case, we can forward it back here.
 337         --
 338         -- This will break if we allow pipelining of multiply and divide,
 339         -- but ideally, those should go via EX1 anyway and run as a state
 340         -- machine from here.
 341         --
 342         -- One additional hazard to beware of is an XER:SO modifying instruction
 343         -- in EX1 followed immediately by a store conditional. Due to our
 344         -- writeback latency, the store will go down the LSU with the previous
 345         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 346         --
 347         -- We will need to handle that if we ever make stcx. not single issue
 348         --
 349         -- We always pass a valid XER value downto writeback even when
 350         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 351         -- to work for RC instructions.
 352         --
 353         if r.e.write_xerc_enable = '1' then
 354             v.e.xerc := r.e.xerc;
 355         else
 356             v.e.xerc := e_in.xerc;
 357         end if;
 358
 359         -- CR forwarding
 360         cr_in <= e_in.cr;
 361         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 362             for i in 0 to 7 loop
 363                 if r.e.write_cr_mask(i) = '1' then
 364                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 365                 end if;
 366             end loop;
 367         end if;
 368
 369         v.lr_update := '0';
 370         v.mul_in_progress := '0';
 371         v.div_in_progress := '0';
 372         v.cntz_in_progress := '0';
 373
 374         -- signals to multiply and divide units
 375         sign1 := '0';
 376         sign2 := '0';
 377         if e_in.is_signed = '1' then
 378             if e_in.is_32bit = '1' then
 379                 sign1 := a_in(31);
 380                 sign2 := b_in(31);
 381             else
 382                 sign1 := a_in(63);
 383                 sign2 := b_in(63);
 384             end if;
 385         end if;
 386         -- take absolute values
 387         if sign1 = '0' then
 388             abs1 := signed(a_in);
 389         else
 390             abs1 := - signed(a_in);
 391         end if;
 392         if sign2 = '0' then
 393             abs2 := signed(b_in);
 394         else
 395             abs2 := - signed(b_in);
 396         end if;
 397
 398         x_to_multiply <= Execute1ToMultiplyInit;
 399         x_to_multiply.is_32bit <= e_in.is_32bit;
 400
 401         x_to_divider <= Execute1ToDividerInit;
 402         x_to_divider.is_signed <= e_in.is_signed;
 403         x_to_divider.is_32bit <= e_in.is_32bit;
 404         if e_in.insn_type = OP_MOD then
 405             x_to_divider.is_modulus <= '1';
 406         end if;
 407
 408         x_to_multiply.neg_result <= sign1 xor sign2;
 409         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 410         if e_in.is_32bit = '0' then
 411             -- 64-bit forms
 412             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 413             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 414             if e_in.insn_type = OP_DIVE then
 415                 x_to_divider.is_extended <= '1';
 416             end if;
 417             x_to_divider.dividend <= std_ulogic_vector(abs1);
 418             x_to_divider.divisor <= std_ulogic_vector(abs2);
 419         else
 420             -- 32-bit forms
 421             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 422             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 423             x_to_divider.is_extended <= '0';
 424             if e_in.insn_type = OP_DIVE then   -- extended forms
 425                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 426             else
 427                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 428             end if;
 429             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 430         end if;
 431
 432         ctrl_tmp <= ctrl;
 433         -- FIXME: run at 512MHz not core freq
 434         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 435         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 436
 437         irq_valid := '0';
 438         if ctrl.msr(MSR_EE) = '1' then
 439             if ctrl.dec(63) = '1' then
 440                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 441                 report "IRQ valid: DEC";
 442                 irq_valid := '1';
 443             elsif ext_irq_in = '1' then
 444                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 445                 report "IRQ valid: External";
 446                 irq_valid := '1';
 447             end if;
 448         end if;
 449
 450         v.terminate := '0';
 451         icache_inval <= '0';
 452         v.busy := '0';
 453         -- send MSR[IR] and ~MSR[PR] up to fetch1
 454         v.f.virt_mode := ctrl.msr(MSR_IR);
 455         v.f.priv_mode := not ctrl.msr(MSR_PR);
 456
 457         -- Next insn adder used in a couple of places
 458         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 459
 460         -- rotator control signals
 461         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 462         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 463         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 464         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 465
 466         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 467         ctrl_tmp.irq_state <= WRITE_SRR0;
 468         exception := '0';
 469         illegal := '0';
 470         exception_nextpc := '0';
 471         v.e.exc_write_enable := '0';
 472         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 473         v.e.exc_write_data := e_in.nia;
 474         if valid_in = '1' then
 475             v.last_nia := e_in.nia;
 476         end if;
 477
 478         if ctrl.irq_state = WRITE_SRR1 then
 479             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 480             v.e.exc_write_data := ctrl.srr1;
 481             v.e.exc_write_enable := '1';
 482             ctrl_tmp.msr(MSR_SF) <= '1';
 483             ctrl_tmp.msr(MSR_EE) <= '0';
 484             ctrl_tmp.msr(MSR_PR) <= '0';
 485             ctrl_tmp.msr(MSR_IR) <= '0';
 486             ctrl_tmp.msr(MSR_DR) <= '0';
 487             ctrl_tmp.msr(MSR_RI) <= '0';
 488             ctrl_tmp.msr(MSR_LE) <= '1';
 489             v.e.valid := '1';
 490             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 491
 492         elsif irq_valid = '1' and valid_in = '1' then
 493             -- we need two cycles to write srr0 and 1
 494             -- will need more when we have to write HEIR
 495             -- Don't deliver the interrupt until we have a valid instruction
 496             -- coming in, so we have a valid NIA to put in SRR0.
 497             exception := '1';
 498
 499         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 500             instr_is_privileged(e_in.insn_type, e_in.insn) then
 501             -- generate a program interrupt
 502             exception := '1';
 503             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 504             -- set bit 45 to indicate privileged instruction type interrupt
 505             ctrl_tmp.srr1(63 - 45) <= '1';
 506             report "privileged instruction";
 507
 508         elsif valid_in = '1' and e_in.unit = ALU then
 509
 510             report "execute nia " & to_hstring(e_in.nia);
 511
 512             v.e.valid := '1';
 513             v.e.write_reg := e_in.write_reg;
 514             v.slow_op_insn := e_in.insn_type;
 515             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 516             v.slow_op_rc := e_in.rc;
 517             v.slow_op_oe := e_in.oe;
 518             v.slow_op_xerc := v.e.xerc;
 519
 520             case_0: case e_in.insn_type is
 521
 522             when OP_ILLEGAL =>
 523                 -- we need two cycles to write srr0 and 1
 524                 -- will need more when we have to write HEIR
 525                 illegal := '1';
 526             when OP_SC =>
 527                 -- check bit 1 of the instruction is 1 so we know this is sc;
 528                 -- 0 would mean scv, so generate an illegal instruction interrupt
 529                 -- we need two cycles to write srr0 and 1
 530                 if e_in.insn(1) = '1' then
 531                     exception := '1';
 532                     exception_nextpc := '1';
 533                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 534                     report "sc";
 535                 else
 536                     illegal := '1';
 537                 end if;
 538             when OP_ATTN =>
 539                 -- check bits 1-10 of the instruction to make sure it's attn
 540                 -- if not then it is illegal
 541                 if e_in.insn(10 downto 1) = "0100000000" then
 542                     v.terminate := '1';
 543                     report "ATTN";
 544                 else
 545                     illegal := '1';
 546                 end if;
 547             when OP_NOP =>
 548                 -- Do nothing
 549             when OP_ADD | OP_CMP | OP_TRAP =>
 550                 if e_in.invert_a = '0' then
 551                     a_inv := a_in;
 552                 else
 553                     a_inv := not a_in;
 554                 end if;
 555                 result_with_carry := ppc_adde(a_inv, b_in,
 556                                               decode_input_carry(e_in.input_carry, v.e.xerc));
 557                 result := result_with_carry(63 downto 0);
 558                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 559                 carry_64 := result_with_carry(64);
 560                 if e_in.insn_type = OP_ADD then
 561                     if e_in.output_carry = '1' then
 562                         set_carry(v.e, carry_32, carry_64);
 563                     end if;
 564                     if e_in.oe = '1' then
 565                         set_ov(v.e,
 566                                calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
 567                                calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
 568                     end if;
 569                     result_en := '1';
 570                 else
 571                     -- trap, CMP and CMPL instructions
 572                     -- Note, we have done RB - RA, not RA - RB
 573                     if e_in.insn_type = OP_CMP then
 574                         l := insn_l(e_in.insn);
 575                     else
 576                         l := not e_in.is_32bit;
 577                     end if;
 578                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 579                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 580                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 581                         -- values are equal
 582                         trapval := "00100";
 583                     else
 584                         if l = '1' then
 585                             -- 64-bit comparison
 586                             msb_a := a_in(63);
 587                             msb_b := b_in(63);
 588                         else
 589                             -- 32-bit comparison
 590                             msb_a := a_in(31);
 591                             msb_b := b_in(31);
 592                         end if;
 593                         if msb_a /= msb_b then
 594                             -- Subtraction might overflow, but
 595                             -- comparison is clear from MSB difference.
 596                             -- for signed, 0 is greater; for unsigned, 1 is greater
 597                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 598                         else
 599                             -- Subtraction cannot overflow since MSBs are equal.
 600                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 601                             a_lt := (not l and carry_32) or (l and carry_64);
 602                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 603                         end if;
 604                     end if;
 605                     if e_in.insn_type = OP_CMP then
 606                         if e_in.is_signed = '1' then
 607                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 608                         else
 609                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 610                         end if;
 611                         bf := insn_bf(e_in.insn);
 612                         crnum := to_integer(unsigned(bf));
 613                         v.e.write_cr_enable := '1';
 614                         v.e.write_cr_mask := num_to_fxm(crnum);
 615                         for i in 0 to 7 loop
 616                             lo := i*4;
 617                             hi := lo + 3;
 618                             v.e.write_cr_data(hi downto lo) := newcrf;
 619                         end loop;
 620                     else
 621                         -- trap instructions (tw, twi, td, tdi)
 622                         v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 623                         -- set bit 46 to say trap occurred
 624                         ctrl_tmp.srr1(63 - 46) <= '1';
 625                         if or (trapval and insn_to(e_in.insn)) = '1' then
 626                             -- generate trap-type program interrupt
 627                             exception := '1';
 628                             report "trap";
 629                         end if;
 630                     end if;
 631                 end if;
 632             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS =>
 633                 result := logical_result;
 634                 result_en := '1';
 635             when OP_B =>
 636                 is_branch := '1';
 637                 taken_branch := '1';
 638                 abs_branch := insn_aa(e_in.insn);
 639             when OP_BC =>
 640                 -- read_data1 is CTR
 641                 bo := insn_bo(e_in.insn);
 642                 bi := insn_bi(e_in.insn);
 643                 if bo(4-2) = '0' then
 644                     result := std_ulogic_vector(unsigned(a_in) - 1);
 645                     result_en := '1';
 646                     v.e.write_reg := fast_spr_num(SPR_CTR);
 647                 end if;
 648                 is_branch := '1';
 649                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 650                 abs_branch := insn_aa(e_in.insn);
 651             when OP_BCREG =>
 652                 -- read_data1 is CTR
 653                 -- read_data2 is target register (CTR, LR or TAR)
 654                 bo := insn_bo(e_in.insn);
 655                 bi := insn_bi(e_in.insn);
 656                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 657                     result := std_ulogic_vector(unsigned(a_in) - 1);
 658                     result_en := '1';
 659                     v.e.write_reg := fast_spr_num(SPR_CTR);
 660                 end if;
 661                 is_branch := '1';
 662                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 663                 abs_branch := '1';
 664
 665             when OP_RFID =>
 666                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 667                 v.f.priv_mode := not a_in(MSR_PR);
 668                 -- Can't use msr_copy here because the partial function MSR
 669                 -- bits should be left unchanged, not zeroed.
 670                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 671                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 672                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 673                 if a_in(MSR_PR) = '1' then
 674                     ctrl_tmp.msr(MSR_EE) <= '1';
 675                     ctrl_tmp.msr(MSR_IR) <= '1';
 676                     ctrl_tmp.msr(MSR_DR) <= '1';
 677                 end if;
 678                 -- mark this as a branch so CFAR gets updated
 679                 is_branch := '1';
 680                 taken_branch := '1';
 681                 abs_branch := '1';
 682
 683             when OP_CNTZ =>
 684                 v.e.valid := '0';
 685                 v.cntz_in_progress := '1';
 686                 v.busy := '1';
 687             when OP_ISEL =>
 688                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 689                 if cr_in(31-crbit) = '1' then
 690                     result := a_in;
 691                 else
 692                     result := b_in;
 693                 end if;
 694                 result_en := '1';
 695             when OP_CROP =>
 696                 cr_op := insn_cr(e_in.insn);
 697                 report "CR OP " & to_hstring(cr_op);
 698                 if cr_op(0) = '0' then -- MCRF
 699                     bf := insn_bf(e_in.insn);
 700                     bfa := insn_bfa(e_in.insn);
 701                     v.e.write_cr_enable := '1';
 702                     crnum := to_integer(unsigned(bf));
 703                     scrnum := to_integer(unsigned(bfa));
 704                     v.e.write_cr_mask := num_to_fxm(crnum);
 705                     for i in 0 to 7 loop
 706                         lo := (7-i)*4;
 707                         hi := lo + 3;
 708                         if i = scrnum then
 709                             newcrf := cr_in(hi downto lo);
 710                         end if;
 711                     end loop;
 712                     for i in 0 to 7 loop
 713                         lo := i*4;
 714                         hi := lo + 3;
 715                         v.e.write_cr_data(hi downto lo) := newcrf;
 716                     end loop;
 717                 else
 718                     v.e.write_cr_enable := '1';
 719                     bt := insn_bt(e_in.insn);
 720                     ba := insn_ba(e_in.insn);
 721                     bb := insn_bb(e_in.insn);
 722                     btnum := 31 - to_integer(unsigned(bt));
 723                     banum := 31 - to_integer(unsigned(ba));
 724                     bbnum := 31 - to_integer(unsigned(bb));
 725                     -- Bits 5-8 of cr_op give the truth table of the requested
 726                     -- logical operation
 727                     cr_operands := cr_in(banum) & cr_in(bbnum);
 728                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 729                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 730                     for i in 0 to 31 loop
 731                         if i = btnum then
 732                             v.e.write_cr_data(i) := crresult;
 733                         else
 734                             v.e.write_cr_data(i) := cr_in(i);
 735                         end if;
 736                     end loop;
 737                 end if;
 738             when OP_MFMSR =>
 739                 result := ctrl.msr;
 740                 result_en := '1';
 741             when OP_MFSPR =>
 742                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 743                     "=" & to_hstring(a_in);
 744                 result_en := '1';
 745                 if is_fast_spr(e_in.read_reg1) then
 746                     result := a_in;
 747                     if decode_spr_num(e_in.insn) = SPR_XER then
 748                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 749                         result(63 downto 32) := (others => '0');
 750                         result(63-32) := v.e.xerc.so;
 751                         result(63-33) := v.e.xerc.ov;
 752                         result(63-34) := v.e.xerc.ca;
 753                         result(63-35 downto 63-43) := "000000000";
 754                         result(63-44) := v.e.xerc.ov32;
 755                         result(63-45) := v.e.xerc.ca32;
 756                     end if;
 757                 else
 758                     spr_val := c_in;
 759                     case decode_spr_num(e_in.insn) is
 760                     when SPR_TB =>
 761                         spr_val := ctrl.tb;
 762                     when SPR_TBU =>
 763                         spr_val(63 downto 32) := (others => '0');
 764                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 765                     when SPR_DEC =>
 766                         spr_val := ctrl.dec;
 767                     when SPR_CFAR =>
 768                         spr_val := ctrl.cfar;
 769                     when SPR_PVR =>
 770                         spr_val(63 downto 32) := (others => '0');
 771                         spr_val(31 downto 0) := PVR_MICROWATT;
 772                     when 724 =>     -- LOG_ADDR SPR
 773                         spr_val := log_wr_addr & r.log_addr_spr;
 774                     when 725 =>     -- LOG_DATA SPR
 775                         spr_val := log_rd_data;
 776                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 777                     when others =>
 778                         -- mfspr from unimplemented SPRs should be a nop in
 779                         -- supervisor mode and a program interrupt for user mode
 780                         if ctrl.msr(MSR_PR) = '1' then
 781                             illegal := '1';
 782                         end if;
 783                     end case;
 784                     result := spr_val;
 785                 end if;
 786             when OP_MFCR =>
 787                 if e_in.insn(20) = '0' then
 788                     -- mfcr
 789                     result := x"00000000" & cr_in;
 790                 else
 791                     -- mfocrf
 792                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 793                     result := (others => '0');
 794                     for i in 0 to 7 loop
 795                         lo := (7-i)*4;
 796                         hi := lo + 3;
 797                         if crnum = i then
 798                             result(hi downto lo) := cr_in(hi downto lo);
 799                         end if;
 800                     end loop;
 801                 end if;
 802                 result_en := '1';
 803             when OP_MTCRF =>
 804                 v.e.write_cr_enable := '1';
 805                 if e_in.insn(20) = '0' then
 806                     -- mtcrf
 807                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 808                 else
 809                     -- mtocrf: We require one hot priority encoding here
 810                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 811                     v.e.write_cr_mask := num_to_fxm(crnum);
 812                 end if;
 813                 v.e.write_cr_data := c_in(31 downto 0);
 814             when OP_MTMSRD =>
 815                 if e_in.insn(16) = '1' then
 816                     -- just update EE and RI
 817                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 818                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 819                 else
 820                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 821                     -- and 63 (LE) (IBM bit numbering)
 822                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 823                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 824                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 825                     if c_in(MSR_PR) = '1' then
 826                         ctrl_tmp.msr(MSR_EE) <= '1';
 827                         ctrl_tmp.msr(MSR_IR) <= '1';
 828                         ctrl_tmp.msr(MSR_DR) <= '1';
 829                     end if;
 830                 end if;
 831             when OP_MTSPR =>
 832                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 833                     "=" & to_hstring(c_in);
 834                 if is_fast_spr(e_in.write_reg) then
 835                     result := c_in;
 836                     result_en := '1';
 837                     if decode_spr_num(e_in.insn) = SPR_XER then
 838                         v.e.xerc.so := c_in(63-32);
 839                         v.e.xerc.ov := c_in(63-33);
 840                         v.e.xerc.ca := c_in(63-34);
 841                         v.e.xerc.ov32 := c_in(63-44);
 842                         v.e.xerc.ca32 := c_in(63-45);
 843                         v.e.write_xerc_enable := '1';
 844                     end if;
 845                 else
 846                     -- slow spr
 847                     case decode_spr_num(e_in.insn) is
 848                     when SPR_DEC =>
 849                         ctrl_tmp.dec <= c_in;
 850                     when 724 =>     -- LOG_ADDR SPR
 851                         v.log_addr_spr := c_in(31 downto 0);
 852                     when others =>
 853                         -- mtspr to unimplemented SPRs should be a nop in
 854                         -- supervisor mode and a program interrupt for user mode
 855                         if ctrl.msr(MSR_PR) = '1' then
 856                             illegal := '1';
 857                         end if;
 858                     end case;
 859                 end if;
 860             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 861                 result := rotator_result;
 862                 if e_in.output_carry = '1' then
 863                     set_carry(v.e, rotator_carry, rotator_carry);
 864                 end if;
 865                 result_en := '1';
 866
 867             when OP_ISYNC =>
 868                 v.f.redirect := '1';
 869                 v.f.redirect_nia := next_nia;
 870
 871             when OP_ICBI =>
 872                 icache_inval <= '1';
 873
 874             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 875                 v.e.valid := '0';
 876                 v.mul_in_progress := '1';
 877                 v.busy := '1';
 878                 x_to_multiply.valid <= '1';
 879
 880             when OP_DIV | OP_DIVE | OP_MOD =>
 881                 v.e.valid := '0';
 882                 v.div_in_progress := '1';
 883                 v.busy := '1';
 884                 x_to_divider.valid <= '1';
 885
 886             when others =>
 887                 v.terminate := '1';
 888                 report "illegal";
 889             end case;
 890
 891             v.e.rc := e_in.rc and valid_in;
 892
 893             -- Mispredicted branches cause a redirect
 894             if is_branch = '1' then
 895                 if taken_branch = '1' then
 896                     ctrl_tmp.cfar <= e_in.nia;
 897                 end if;
 898                 if e_in.br_pred = '0' then
 899                     if abs_branch = '1' then
 900                         v.f.redirect_nia := b_in;
 901                     else
 902                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 903                     end if;
 904                 else
 905                     v.f.redirect_nia := next_nia;
 906                 end if;
 907                 if taken_branch /= e_in.br_pred then
 908                     v.f.redirect := '1';
 909                 end if;
 910             end if;
 911
 912             -- Update LR on the next cycle after a branch link
 913             -- If we're not writing back anything else, we can write back LR
 914             -- this cycle, otherwise we take an extra cycle.  We use the
 915             -- exc_write path since next_nia is written through that path
 916             -- in other places.
 917             if e_in.lr = '1' then
 918                 if result_en = '0' then
 919                     v.e.exc_write_enable := '1';
 920                     v.e.exc_write_data := next_nia;
 921                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
 922                 else
 923                     v.lr_update := '1';
 924                     v.next_lr := next_nia;
 925                     v.e.valid := '0';
 926                     report "Delayed LR update to " & to_hstring(next_nia);
 927                     v.busy := '1';
 928                 end if;
 929             end if;
 930
 931         elsif valid_in = '1' then
 932             -- instruction for other units, i.e. LDST
 933             if e_in.unit = LDST then
 934                 lv.valid := '1';
 935             end if;
 936
 937         elsif r.f.redirect = '1' then
 938             v.e.valid := '1';
 939         elsif r.lr_update = '1' then
 940             v.e.exc_write_enable := '1';
 941             v.e.exc_write_data := r.next_lr;
 942             v.e.exc_write_reg := fast_spr_num(SPR_LR);
 943             v.e.valid := '1';
 944         elsif r.cntz_in_progress = '1' then
 945             -- cnt[lt]z always takes two cycles
 946             result := countzero_result;
 947             result_en := '1';
 948             v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 949             v.e.rc := v.slow_op_rc;
 950             v.e.xerc := v.slow_op_xerc;
 951             v.e.valid := '1';
 952         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 953             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
 954                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
 955                 if r.mul_in_progress = '1' then
 956                     overflow := '0';
 957                     case r.slow_op_insn is
 958                         when OP_MUL_H32 =>
 959                             result := multiply_to_x.result(63 downto 32) &
 960                                       multiply_to_x.result(63 downto 32);
 961                         when OP_MUL_H64 =>
 962                             result := multiply_to_x.result(127 downto 64);
 963                         when others =>
 964                             -- i.e. OP_MUL_L64
 965                             result := multiply_to_x.result(63 downto 0);
 966                             overflow := multiply_to_x.overflow;
 967                     end case;
 968                 else
 969                     result := divider_to_x.write_reg_data;
 970                     overflow := divider_to_x.overflow;
 971                 end if;
 972                 result_en := '1';
 973                 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 974                 v.e.rc := v.slow_op_rc;
 975                 v.e.xerc := v.slow_op_xerc;
 976                 v.e.write_xerc_enable := v.slow_op_oe;
 977                 -- We must test oe because the RC update code in writeback
 978                 -- will use the xerc value to set CR0:SO so we must not clobber
 979                 -- xerc if OE wasn't set.
 980                 if v.slow_op_oe = '1' then
 981                     v.e.xerc.ov := overflow;
 982                     v.e.xerc.ov32 := overflow;
 983                     v.e.xerc.so := v.slow_op_xerc.so or overflow;
 984                 end if;
 985                 v.e.valid := '1';
 986             else
 987                 v.busy := '1';
 988                 v.mul_in_progress := r.mul_in_progress;
 989                 v.div_in_progress := r.div_in_progress;
 990             end if;
 991         end if;
 992
 993         if illegal = '1' then
 994             exception := '1';
 995             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 996             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
 997             -- set bit 44 to indicate we have an illegal
 998             ctrl_tmp.srr1(63 - 44) <= '1';
 999             report "illegal";
1000         end if;
1001         if exception = '1' then
1002             v.e.exc_write_enable := '1';
1003             if exception_nextpc = '1' then
1004                 v.e.exc_write_data := next_nia;
1005             end if;
1006         end if;
1007
1008         v.e.write_data := result;
1009         v.e.write_enable := result_en and not exception;
1010
1011         -- generate DSI or DSegI for load/store exceptions
1012         -- or ISI or ISegI for instruction fetch exceptions
1013         if l_in.exception = '1' then
1014             if l_in.instr_fault = '0' then
1015                 if l_in.segment_fault = '0' then
1016                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1017                 else
1018                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1019                 end if;
1020             else
1021                 if l_in.segment_fault = '0' then
1022                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1023                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1024                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1025                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1026                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1027                 else
1028                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1029                 end if;
1030             end if;
1031             v.e.exc_write_enable := '1';
1032             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1033             v.e.exc_write_data := r.last_nia;
1034             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1035         end if;
1036
1037         if exception = '1' or l_in.exception = '1' then
1038             ctrl_tmp.irq_state <= WRITE_SRR1;
1039             v.f.redirect := '1';
1040             v.f.virt_mode := '0';
1041             v.f.priv_mode := '1';
1042         end if;
1043
1044         if v.f.redirect = '1' then
1045             v.busy := '1';
1046             v.e.valid := '0';
1047         end if;
1048
1049         -- Outputs to loadstore1 (async)
1050         lv.op := e_in.insn_type;
1051         lv.nia := e_in.nia;
1052         lv.addr1 := a_in;
1053         lv.addr2 := b_in;
1054         lv.data := c_in;
1055         lv.write_reg := gspr_to_gpr(e_in.write_reg);
1056         lv.length := e_in.data_len;
1057         lv.byte_reverse := e_in.byte_reverse;
1058         lv.sign_extend := e_in.sign_extend;
1059         lv.update := e_in.update;
1060         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1061         lv.xerc := v.e.xerc;
1062         lv.reserve := e_in.reserve;
1063         lv.rc := e_in.rc;
1064         lv.insn := e_in.insn;
1065         -- decode l*cix and st*cix instructions here
1066         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1067             e_in.insn(5 downto 1) = "10101" then
1068             lv.ci := '1';
1069         end if;
1070         lv.virt_mode := ctrl.msr(MSR_DR);
1071         lv.priv_mode := not ctrl.msr(MSR_PR);
1072
1073         -- Update registers
1074         rin <= v;
1075
1076         -- update outputs
1077         f_out <= r.f;
1078         l_out <= lv;
1079         e_out <= r.e;
1080         flush_out <= f_out.redirect;
1081
1082         exception_log <= exception;
1083         irq_valid_log <= irq_valid;
1084     end process;
1085
1086     ex1_log : process(clk)
1087     begin
1088         if rising_edge(clk) then
1089             log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1090                         ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1091                         exception_log &
1092                         irq_valid_log &
1093                         std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1094                         "000" &
1095                         r.e.write_enable &
1096                         r.e.valid &
1097                         f_out.redirect &
1098                         r.busy &
1099                         flush_out;
1100         end if;
1101     end process;
1102     log_out <= log_data;
1103 end architecture behaviour;