execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true
  16         );
  17     port (
  18         clk   : in std_ulogic;
  19         rst   : in std_ulogic;
  20
  21         -- asynchronous
  22         flush_out : out std_ulogic;
  23         stall_out : out std_ulogic;
  24
  25         e_in  : in Decode2ToExecute1Type;
  26         l_in  : in Loadstore1ToExecute1Type;
  27
  28         ext_irq_in : std_ulogic;
  29
  30         -- asynchronous
  31         l_out : out Execute1ToLoadstore1Type;
  32         f_out : out Execute1ToFetch1Type;
  33
  34         e_out : out Execute1ToWritebackType;
  35
  36         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  37
  38         icache_inval : out std_ulogic;
  39         terminate_out : out std_ulogic;
  40
  41         log_out : out std_ulogic_vector(14 downto 0);
  42         log_rd_addr : out std_ulogic_vector(31 downto 0);
  43         log_rd_data : in std_ulogic_vector(63 downto 0);
  44         log_wr_addr : in std_ulogic_vector(31 downto 0)
  45         );
  46 end entity execute1;
  47
  48 architecture behaviour of execute1 is
  49     type reg_type is record
  50         e : Execute1ToWritebackType;
  51         lr_update : std_ulogic;
  52         next_lr : std_ulogic_vector(63 downto 0);
  53         mul_in_progress : std_ulogic;
  54         div_in_progress : std_ulogic;
  55         cntz_in_progress : std_ulogic;
  56         slow_op_insn : insn_type_t;
  57         slow_op_dest : gpr_index_t;
  58         slow_op_rc : std_ulogic;
  59         slow_op_oe : std_ulogic;
  60         slow_op_xerc : xer_common_t;
  61         ldst_nia : std_ulogic_vector(63 downto 0);
  62         log_addr_spr : std_ulogic_vector(31 downto 0);
  63     end record;
  64     constant reg_type_init : reg_type :=
  65         (e => Execute1ToWritebackInit, lr_update => '0',
  66          mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
  67          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  68          next_lr => (others => '0'), ldst_nia => (others => '0'), others => (others => '0'));
  69
  70     signal r, rin : reg_type;
  71
  72     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  73
  74     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  75     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  76     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  77     signal rot_sign_ext: std_ulogic;
  78     signal rotator_result: std_ulogic_vector(63 downto 0);
  79     signal rotator_carry: std_ulogic;
  80     signal logical_result: std_ulogic_vector(63 downto 0);
  81     signal countzero_result: std_ulogic_vector(63 downto 0);
  82     signal popcnt_result: std_ulogic_vector(63 downto 0);
  83     signal parity_result: std_ulogic_vector(63 downto 0);
  84
  85     -- multiply signals
  86     signal x_to_multiply: Execute1ToMultiplyType;
  87     signal multiply_to_x: MultiplyToExecute1Type;
  88
  89     -- divider signals
  90     signal x_to_divider: Execute1ToDividerType;
  91     signal divider_to_x: DividerToExecute1Type;
  92
  93     -- signals for logging
  94     signal exception_log : std_ulogic;
  95     signal irq_valid_log : std_ulogic;
  96     signal log_data : std_ulogic_vector(14 downto 0);
  97
  98     type privilege_level is (USER, SUPER);
  99     type op_privilege_array is array(insn_type_t) of privilege_level;
 100     constant op_privilege: op_privilege_array := (
 101         OP_ATTN => SUPER,
 102         OP_MFMSR => SUPER,
 103         OP_MTMSRD => SUPER,
 104         OP_RFID => SUPER,
 105         OP_TLBIE => SUPER,
 106         others => USER
 107         );
 108
 109     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 110         return boolean is
 111     begin
 112         if op_privilege(op) = SUPER then
 113             return true;
 114         elsif op = OP_MFSPR or op = OP_MTSPR then
 115             return insn(20) = '1';
 116         else
 117             return false;
 118         end if;
 119     end;
 120
 121     procedure set_carry(e: inout Execute1ToWritebackType;
 122                         carry32 : in std_ulogic;
 123                         carry : in std_ulogic) is
 124     begin
 125         e.xerc.ca32 := carry32;
 126         e.xerc.ca := carry;
 127         e.write_xerc_enable := '1';
 128     end;
 129
 130     procedure set_ov(e: inout Execute1ToWritebackType;
 131                      ov   : in std_ulogic;
 132                      ov32 : in std_ulogic) is
 133     begin
 134         e.xerc.ov32 := ov32;
 135         e.xerc.ov := ov;
 136         if ov = '1' then
 137             e.xerc.so := '1';
 138         end if;
 139         e.write_xerc_enable := '1';
 140     end;
 141
 142     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 143                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 144     begin
 145         return (ca xor msb_r) and not (msb_a xor msb_b);
 146     end;
 147
 148     function decode_input_carry(ic : carry_in_t;
 149                                 xerc : xer_common_t) return std_ulogic is
 150     begin
 151         case ic is
 152         when ZERO =>
 153             return '0';
 154         when CA =>
 155             return xerc.ca;
 156         when ONE =>
 157             return '1';
 158         end case;
 159     end;
 160
 161     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 162         return std_ulogic_vector is
 163         variable msr_out: std_ulogic_vector(63 downto 0);
 164     begin
 165         -- ISA says this:
 166         --  Defined MSR bits are classified as either full func-
 167         --  tion or partial function. Full function MSR bits are
 168         --  saved in SRR1 or HSRR1 when an interrupt other
 169         --  than a System Call Vectored interrupt occurs and
 170         --  restored by rfscv, rfid, or hrfid, while partial func-
 171         --  tion MSR bits are not saved or restored.
 172         --  Full function MSR bits lie in the range 0:32, 37:41, and
 173         --  48:63, and partial function MSR bits lie in the range
 174         --  33:36 and 42:47. (Note this is IBM bit numbering).
 175         msr_out := (others => '0');
 176         msr_out(63 downto 31) := msr(63 downto 31);
 177         msr_out(26 downto 22) := msr(26 downto 22);
 178         msr_out(15 downto 0)  := msr(15 downto 0);
 179         return msr_out;
 180     end;
 181
 182 begin
 183
 184     rotator_0: entity work.rotator
 185         port map (
 186             rs => c_in,
 187             ra => a_in,
 188             shift => b_in(6 downto 0),
 189             insn => e_in.insn,
 190             is_32bit => e_in.is_32bit,
 191             right_shift => right_shift,
 192             arith => e_in.is_signed,
 193             clear_left => rot_clear_left,
 194             clear_right => rot_clear_right,
 195             sign_ext_rs => rot_sign_ext,
 196             result => rotator_result,
 197             carry_out => rotator_carry
 198             );
 199
 200     logical_0: entity work.logical
 201         port map (
 202             rs => c_in,
 203             rb => b_in,
 204             op => e_in.insn_type,
 205             invert_in => e_in.invert_a,
 206             invert_out => e_in.invert_out,
 207             result => logical_result,
 208             datalen => e_in.data_len,
 209             popcnt => popcnt_result,
 210             parity => parity_result
 211             );
 212
 213     countzero_0: entity work.zero_counter
 214         port map (
 215             clk => clk,
 216             rs => c_in,
 217             count_right => e_in.insn(10),
 218             is_32bit => e_in.is_32bit,
 219             result => countzero_result
 220             );
 221
 222     multiply_0: entity work.multiply
 223         port map (
 224             clk => clk,
 225             m_in => x_to_multiply,
 226             m_out => multiply_to_x
 227             );
 228
 229     divider_0: entity work.divider
 230         port map (
 231             clk => clk,
 232             rst => rst,
 233             d_in => x_to_divider,
 234             d_out => divider_to_x
 235             );
 236
 237     dbg_msr_out <= ctrl.msr;
 238     log_rd_addr <= r.log_addr_spr;
 239
 240     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 241     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 242     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 243
 244     execute1_0: process(clk)
 245     begin
 246         if rising_edge(clk) then
 247             if rst = '1' then
 248                 r <= reg_type_init;
 249                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 250                 ctrl.irq_state <= WRITE_SRR0;
 251             else
 252                 r <= rin;
 253                 ctrl <= ctrl_tmp;
 254                 assert not (r.lr_update = '1' and e_in.valid = '1')
 255                     report "LR update collision with valid in EX1"
 256                     severity failure;
 257                 if r.lr_update = '1' then
 258                     report "LR update to " & to_hstring(r.next_lr);
 259                 end if;
 260             end if;
 261         end if;
 262     end process;
 263
 264     execute1_1: process(all)
 265         variable v : reg_type;
 266         variable a_inv : std_ulogic_vector(63 downto 0);
 267         variable result : std_ulogic_vector(63 downto 0);
 268         variable newcrf : std_ulogic_vector(3 downto 0);
 269         variable result_with_carry : std_ulogic_vector(64 downto 0);
 270         variable result_en : std_ulogic;
 271         variable crnum : crnum_t;
 272         variable crbit : integer range 0 to 31;
 273         variable scrnum : crnum_t;
 274         variable lo, hi : integer;
 275         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 276         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 277         variable bo, bi : std_ulogic_vector(4 downto 0);
 278         variable bf, bfa : std_ulogic_vector(2 downto 0);
 279         variable cr_op : std_ulogic_vector(9 downto 0);
 280         variable cr_operands : std_ulogic_vector(1 downto 0);
 281         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 282         variable btnum, banum, bbnum : integer range 0 to 31;
 283         variable crresult : std_ulogic;
 284         variable l : std_ulogic;
 285         variable next_nia : std_ulogic_vector(63 downto 0);
 286         variable carry_32, carry_64 : std_ulogic;
 287         variable sign1, sign2 : std_ulogic;
 288         variable abs1, abs2 : signed(63 downto 0);
 289         variable overflow : std_ulogic;
 290         variable negative : std_ulogic;
 291         variable zerohi, zerolo : std_ulogic;
 292         variable msb_a, msb_b : std_ulogic;
 293         variable a_lt : std_ulogic;
 294         variable lv : Execute1ToLoadstore1Type;
 295         variable irq_valid : std_ulogic;
 296         variable exception : std_ulogic;
 297         variable exception_nextpc : std_ulogic;
 298         variable trapval : std_ulogic_vector(4 downto 0);
 299         variable illegal : std_ulogic;
 300     begin
 301         result := (others => '0');
 302         result_with_carry := (others => '0');
 303         result_en := '0';
 304         newcrf := (others => '0');
 305
 306         v := r;
 307         v.e := Execute1ToWritebackInit;
 308         lv := Execute1ToLoadstore1Init;
 309
 310         -- XER forwarding. To avoid having to track XER hazards, we
 311         -- use the previously latched value.
 312         --
 313         -- If the XER was modified by a multiply or a divide, those are
 314         -- single issue, we'll get the up to date value from decode2 from
 315         -- the register file.
 316         --
 317         -- If it was modified by an instruction older than the previous
 318         -- one in EX1, it will have also hit writeback and will be up
 319         -- to date in decode2.
 320         --
 321         -- That leaves us with the case where it was updated by the previous
 322         -- instruction in EX1. In that case, we can forward it back here.
 323         --
 324         -- This will break if we allow pipelining of multiply and divide,
 325         -- but ideally, those should go via EX1 anyway and run as a state
 326         -- machine from here.
 327         --
 328         -- One additional hazard to beware of is an XER:SO modifying instruction
 329         -- in EX1 followed immediately by a store conditional. Due to our
 330         -- writeback latency, the store will go down the LSU with the previous
 331         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 332         --
 333         -- We will need to handle that if we ever make stcx. not single issue
 334         --
 335         -- We always pass a valid XER value downto writeback even when
 336         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 337         -- to work for RC instructions.
 338         --
 339         if r.e.write_xerc_enable = '1' then
 340             v.e.xerc := r.e.xerc;
 341         else
 342             v.e.xerc := e_in.xerc;
 343         end if;
 344
 345         v.lr_update := '0';
 346         v.mul_in_progress := '0';
 347         v.div_in_progress := '0';
 348         v.cntz_in_progress := '0';
 349
 350         -- signals to multiply and divide units
 351         sign1 := '0';
 352         sign2 := '0';
 353         if e_in.is_signed = '1' then
 354             if e_in.is_32bit = '1' then
 355                 sign1 := a_in(31);
 356                 sign2 := b_in(31);
 357             else
 358                 sign1 := a_in(63);
 359                 sign2 := b_in(63);
 360             end if;
 361         end if;
 362         -- take absolute values
 363         if sign1 = '0' then
 364             abs1 := signed(a_in);
 365         else
 366             abs1 := - signed(a_in);
 367         end if;
 368         if sign2 = '0' then
 369             abs2 := signed(b_in);
 370         else
 371             abs2 := - signed(b_in);
 372         end if;
 373
 374         x_to_multiply <= Execute1ToMultiplyInit;
 375         x_to_multiply.is_32bit <= e_in.is_32bit;
 376
 377         x_to_divider <= Execute1ToDividerInit;
 378         x_to_divider.is_signed <= e_in.is_signed;
 379         x_to_divider.is_32bit <= e_in.is_32bit;
 380         if e_in.insn_type = OP_MOD then
 381             x_to_divider.is_modulus <= '1';
 382         end if;
 383
 384         x_to_multiply.neg_result <= sign1 xor sign2;
 385         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 386         if e_in.is_32bit = '0' then
 387             -- 64-bit forms
 388             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 389             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 390             if e_in.insn_type = OP_DIVE then
 391                 x_to_divider.is_extended <= '1';
 392             end if;
 393             x_to_divider.dividend <= std_ulogic_vector(abs1);
 394             x_to_divider.divisor <= std_ulogic_vector(abs2);
 395         else
 396             -- 32-bit forms
 397             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 398             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 399             x_to_divider.is_extended <= '0';
 400             if e_in.insn_type = OP_DIVE then   -- extended forms
 401                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 402             else
 403                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 404             end if;
 405             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 406         end if;
 407
 408         ctrl_tmp <= ctrl;
 409         -- FIXME: run at 512MHz not core freq
 410         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 411         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 412
 413         irq_valid := '0';
 414         if ctrl.msr(MSR_EE) = '1' then
 415             if ctrl.dec(63) = '1' then
 416                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
 417                 report "IRQ valid: DEC";
 418                 irq_valid := '1';
 419             elsif ext_irq_in = '1' then
 420                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#500#, 64));
 421                 report "IRQ valid: External";
 422                 irq_valid := '1';
 423             end if;
 424         end if;
 425
 426         terminate_out <= '0';
 427         icache_inval <= '0';
 428         stall_out <= '0';
 429         f_out <= Execute1ToFetch1TypeInit;
 430         -- send MSR[IR] and ~MSR[PR] up to fetch1
 431         f_out.virt_mode <= ctrl.msr(MSR_IR);
 432         f_out.priv_mode <= not ctrl.msr(MSR_PR);
 433
 434         -- Next insn adder used in a couple of places
 435         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 436
 437         -- rotator control signals
 438         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 439         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 440         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 441         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 442
 443         ctrl_tmp.irq_state <= WRITE_SRR0;
 444         exception := '0';
 445         illegal := '0';
 446         exception_nextpc := '0';
 447         v.e.exc_write_enable := '0';
 448         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 449         v.e.exc_write_data := e_in.nia;
 450
 451         if ctrl.irq_state = WRITE_SRR1 then
 452             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 453             v.e.exc_write_data := ctrl.srr1;
 454             v.e.exc_write_enable := '1';
 455             ctrl_tmp.msr(MSR_SF) <= '1';
 456             ctrl_tmp.msr(MSR_EE) <= '0';
 457             ctrl_tmp.msr(MSR_PR) <= '0';
 458             ctrl_tmp.msr(MSR_IR) <= '0';
 459             ctrl_tmp.msr(MSR_DR) <= '0';
 460             ctrl_tmp.msr(MSR_RI) <= '0';
 461             ctrl_tmp.msr(MSR_LE) <= '1';
 462             f_out.redirect <= '1';
 463             f_out.virt_mode <= '0';
 464             f_out.priv_mode <= '1';
 465             f_out.redirect_nia <= ctrl.irq_nia;
 466             v.e.valid := e_in.valid;
 467             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 468
 469         elsif irq_valid = '1' and e_in.valid = '1' then
 470             -- we need two cycles to write srr0 and 1
 471             -- will need more when we have to write HEIR
 472             -- Don't deliver the interrupt until we have a valid instruction
 473             -- coming in, so we have a valid NIA to put in SRR0.
 474             exception := '1';
 475             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 476
 477         elsif e_in.valid = '1' and ctrl.msr(MSR_PR) = '1' and
 478             instr_is_privileged(e_in.insn_type, e_in.insn) then
 479             -- generate a program interrupt
 480             exception := '1';
 481             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 482             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 483             -- set bit 45 to indicate privileged instruction type interrupt
 484             ctrl_tmp.srr1(63 - 45) <= '1';
 485             report "privileged instruction";
 486
 487         elsif e_in.valid = '1' and e_in.unit = ALU then
 488
 489             report "execute nia " & to_hstring(e_in.nia);
 490
 491             v.e.valid := '1';
 492             v.e.write_reg := e_in.write_reg;
 493             v.slow_op_insn := e_in.insn_type;
 494             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 495             v.slow_op_rc := e_in.rc;
 496             v.slow_op_oe := e_in.oe;
 497             v.slow_op_xerc := v.e.xerc;
 498
 499             case_0: case e_in.insn_type is
 500
 501             when OP_ILLEGAL =>
 502                 -- we need two cycles to write srr0 and 1
 503                 -- will need more when we have to write HEIR
 504                 illegal := '1';
 505             when OP_SC =>
 506                 -- check bit 1 of the instruction is 1 so we know this is sc;
 507                 -- 0 would mean scv, so generate an illegal instruction interrupt
 508                 -- we need two cycles to write srr0 and 1
 509                 if e_in.insn(1) = '1' then
 510                     exception := '1';
 511                     exception_nextpc := '1';
 512                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 513                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 514                     report "sc";
 515                 else
 516                     illegal := '1';
 517                 end if;
 518             when OP_ATTN =>
 519                 -- check bits 1-10 of the instruction to make sure it's attn
 520                 -- if not then it is illegal
 521                 if e_in.insn(10 downto 1) = "0100000000" then
 522                     terminate_out <= '1';
 523                     report "ATTN";
 524                 else
 525                     illegal := '1';
 526                 end if;
 527             when OP_NOP =>
 528                 -- Do nothing
 529             when OP_ADD | OP_CMP | OP_TRAP =>
 530                 if e_in.invert_a = '0' then
 531                     a_inv := a_in;
 532                 else
 533                     a_inv := not a_in;
 534                 end if;
 535                 result_with_carry := ppc_adde(a_inv, b_in,
 536                                               decode_input_carry(e_in.input_carry, v.e.xerc));
 537                 result := result_with_carry(63 downto 0);
 538                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 539                 carry_64 := result_with_carry(64);
 540                 if e_in.insn_type = OP_ADD then
 541                     if e_in.output_carry = '1' then
 542                         set_carry(v.e, carry_32, carry_64);
 543                     end if;
 544                     if e_in.oe = '1' then
 545                         set_ov(v.e,
 546                                calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
 547                                calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
 548                     end if;
 549                     result_en := '1';
 550                 else
 551                     -- trap, CMP and CMPL instructions
 552                     -- Note, we have done RB - RA, not RA - RB
 553                     if e_in.insn_type = OP_CMP then
 554                         l := insn_l(e_in.insn);
 555                     else
 556                         l := not e_in.is_32bit;
 557                     end if;
 558                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 559                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 560                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 561                         -- values are equal
 562                         trapval := "00100";
 563                     else
 564                         if l = '1' then
 565                             -- 64-bit comparison
 566                             msb_a := a_in(63);
 567                             msb_b := b_in(63);
 568                         else
 569                             -- 32-bit comparison
 570                             msb_a := a_in(31);
 571                             msb_b := b_in(31);
 572                         end if;
 573                         if msb_a /= msb_b then
 574                             -- Subtraction might overflow, but
 575                             -- comparison is clear from MSB difference.
 576                             -- for signed, 0 is greater; for unsigned, 1 is greater
 577                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 578                         else
 579                             -- Subtraction cannot overflow since MSBs are equal.
 580                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 581                             a_lt := (not l and carry_32) or (l and carry_64);
 582                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 583                         end if;
 584                     end if;
 585                     if e_in.insn_type = OP_CMP then
 586                         if e_in.is_signed = '1' then
 587                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 588                         else
 589                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 590                         end if;
 591                         bf := insn_bf(e_in.insn);
 592                         crnum := to_integer(unsigned(bf));
 593                         v.e.write_cr_enable := '1';
 594                         v.e.write_cr_mask := num_to_fxm(crnum);
 595                         for i in 0 to 7 loop
 596                             lo := i*4;
 597                             hi := lo + 3;
 598                             v.e.write_cr_data(hi downto lo) := newcrf;
 599                         end loop;
 600                     else
 601                         -- trap instructions (tw, twi, td, tdi)
 602                         if or (trapval and insn_to(e_in.insn)) = '1' then
 603                             -- generate trap-type program interrupt
 604                             exception := '1';
 605                             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 606                             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 607                             -- set bit 46 to say trap occurred
 608                             ctrl_tmp.srr1(63 - 46) <= '1';
 609                             report "trap";
 610                         end if;
 611                     end if;
 612                 end if;
 613             when OP_AND | OP_OR | OP_XOR =>
 614                 result := logical_result;
 615                 result_en := '1';
 616             when OP_B =>
 617                 f_out.redirect <= '1';
 618                 if (insn_aa(e_in.insn)) then
 619                     f_out.redirect_nia <= b_in;
 620                 else
 621                     f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 622                 end if;
 623             when OP_BC =>
 624                 -- read_data1 is CTR
 625                 bo := insn_bo(e_in.insn);
 626                 bi := insn_bi(e_in.insn);
 627                 if bo(4-2) = '0' then
 628                     result := std_ulogic_vector(unsigned(a_in) - 1);
 629                     result_en := '1';
 630                     v.e.write_reg := fast_spr_num(SPR_CTR);
 631                 end if;
 632                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 633                     f_out.redirect <= '1';
 634                     if (insn_aa(e_in.insn)) then
 635                         f_out.redirect_nia <= b_in;
 636                     else
 637                         f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 638                     end if;
 639                 end if;
 640             when OP_BCREG =>
 641                 -- read_data1 is CTR
 642                 -- read_data2 is target register (CTR, LR or TAR)
 643                 bo := insn_bo(e_in.insn);
 644                 bi := insn_bi(e_in.insn);
 645                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 646                     result := std_ulogic_vector(unsigned(a_in) - 1);
 647                     result_en := '1';
 648                     v.e.write_reg := fast_spr_num(SPR_CTR);
 649                 end if;
 650                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 651                     f_out.redirect <= '1';
 652                     f_out.redirect_nia <= b_in(63 downto 2) & "00";
 653                 end if;
 654
 655             when OP_RFID =>
 656                 f_out.redirect <= '1';
 657                 f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 658                 f_out.priv_mode <= not b_in(MSR_PR);
 659                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 660                 -- Can't use msr_copy here because the partial function MSR
 661                 -- bits should be left unchanged, not zeroed.
 662                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 663                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 664                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 665                 if b_in(MSR_PR) = '1' then
 666                     ctrl_tmp.msr(MSR_EE) <= '1';
 667                     ctrl_tmp.msr(MSR_IR) <= '1';
 668                     ctrl_tmp.msr(MSR_DR) <= '1';
 669                 end if;
 670
 671             when OP_CMPB =>
 672                 result := ppc_cmpb(c_in, b_in);
 673                 result_en := '1';
 674             when OP_CNTZ =>
 675                 v.e.valid := '0';
 676                 v.cntz_in_progress := '1';
 677                 stall_out <= '1';
 678             when OP_EXTS =>
 679                 -- note data_len is a 1-hot encoding
 680                 negative := (e_in.data_len(0) and c_in(7)) or
 681                             (e_in.data_len(1) and c_in(15)) or
 682                             (e_in.data_len(2) and c_in(31));
 683                 result := (others => negative);
 684                 if e_in.data_len(2) = '1' then
 685                     result(31 downto 16) := c_in(31 downto 16);
 686                 end if;
 687                 if e_in.data_len(2) = '1' or e_in.data_len(1) = '1' then
 688                     result(15 downto 8) := c_in(15 downto 8);
 689                 end if;
 690                 result(7 downto 0) := c_in(7 downto 0);
 691                 result_en := '1';
 692             when OP_ISEL =>
 693                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 694                 if e_in.cr(31-crbit) = '1' then
 695                     result := a_in;
 696                 else
 697                     result := b_in;
 698                 end if;
 699                 result_en := '1';
 700             when OP_CROP =>
 701                 cr_op := insn_cr(e_in.insn);
 702                 report "CR OP " & to_hstring(cr_op);
 703                 if cr_op(0) = '0' then -- MCRF
 704                     bf := insn_bf(e_in.insn);
 705                     bfa := insn_bfa(e_in.insn);
 706                     v.e.write_cr_enable := '1';
 707                     crnum := to_integer(unsigned(bf));
 708                     scrnum := to_integer(unsigned(bfa));
 709                     v.e.write_cr_mask := num_to_fxm(crnum);
 710                     for i in 0 to 7 loop
 711                         lo := (7-i)*4;
 712                         hi := lo + 3;
 713                         if i = scrnum then
 714                             newcrf := e_in.cr(hi downto lo);
 715                         end if;
 716                     end loop;
 717                     for i in 0 to 7 loop
 718                         lo := i*4;
 719                         hi := lo + 3;
 720                         v.e.write_cr_data(hi downto lo) := newcrf;
 721                     end loop;
 722                 else
 723                     v.e.write_cr_enable := '1';
 724                     bt := insn_bt(e_in.insn);
 725                     ba := insn_ba(e_in.insn);
 726                     bb := insn_bb(e_in.insn);
 727                     btnum := 31 - to_integer(unsigned(bt));
 728                     banum := 31 - to_integer(unsigned(ba));
 729                     bbnum := 31 - to_integer(unsigned(bb));
 730                     -- Bits 5-8 of cr_op give the truth table of the requested
 731                     -- logical operation
 732                     cr_operands := e_in.cr(banum) & e_in.cr(bbnum);
 733                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 734                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 735                     for i in 0 to 31 loop
 736                         if i = btnum then
 737                             v.e.write_cr_data(i) := crresult;
 738                         else
 739                             v.e.write_cr_data(i) := e_in.cr(i);
 740                         end if;
 741                     end loop;
 742                 end if;
 743             when OP_MFMSR =>
 744                 result := ctrl.msr;
 745                 result_en := '1';
 746             when OP_MFSPR =>
 747                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 748                     "=" & to_hstring(a_in);
 749                 result_en := '1';
 750                 if is_fast_spr(e_in.read_reg1) then
 751                     result := a_in;
 752                     if decode_spr_num(e_in.insn) = SPR_XER then
 753                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 754                         result(63 downto 32) := (others => '0');
 755                         result(63-32) := v.e.xerc.so;
 756                         result(63-33) := v.e.xerc.ov;
 757                         result(63-34) := v.e.xerc.ca;
 758                         result(63-35 downto 63-43) := "000000000";
 759                         result(63-44) := v.e.xerc.ov32;
 760                         result(63-45) := v.e.xerc.ca32;
 761                     end if;
 762                 else
 763                     case decode_spr_num(e_in.insn) is
 764                     when SPR_TB =>
 765                         result := ctrl.tb;
 766                     when SPR_DEC =>
 767                         result := ctrl.dec;
 768                     when 724 =>     -- LOG_ADDR SPR
 769                         result := log_wr_addr & r.log_addr_spr;
 770                     when 725 =>     -- LOG_DATA SPR
 771                         result := log_rd_data;
 772                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 773                     when others =>
 774                         -- mfspr from unimplemented SPRs should be a nop in
 775                         -- supervisor mode and a program interrupt for user mode
 776                         result := c_in;
 777                         if ctrl.msr(MSR_PR) = '1' then
 778                             illegal := '1';
 779                         end if;
 780                     end case;
 781                 end if;
 782             when OP_MFCR =>
 783                 if e_in.insn(20) = '0' then
 784                     -- mfcr
 785                     result := x"00000000" & e_in.cr;
 786                 else
 787                     -- mfocrf
 788                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 789                     result := (others => '0');
 790                     for i in 0 to 7 loop
 791                         lo := (7-i)*4;
 792                         hi := lo + 3;
 793                         if crnum = i then
 794                             result(hi downto lo) := e_in.cr(hi downto lo);
 795                         end if;
 796                     end loop;
 797                 end if;
 798                 result_en := '1';
 799             when OP_MTCRF =>
 800                 v.e.write_cr_enable := '1';
 801                 if e_in.insn(20) = '0' then
 802                     -- mtcrf
 803                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 804                 else
 805                     -- mtocrf: We require one hot priority encoding here
 806                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 807                     v.e.write_cr_mask := num_to_fxm(crnum);
 808                 end if;
 809                 v.e.write_cr_data := c_in(31 downto 0);
 810             when OP_MTMSRD =>
 811                 if e_in.insn(16) = '1' then
 812                     -- just update EE and RI
 813                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 814                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 815                 else
 816                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 817                     -- and 63 (LE) (IBM bit numbering)
 818                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 819                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 820                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 821                     if c_in(MSR_PR) = '1' then
 822                         ctrl_tmp.msr(MSR_EE) <= '1';
 823                         ctrl_tmp.msr(MSR_IR) <= '1';
 824                         ctrl_tmp.msr(MSR_DR) <= '1';
 825                     end if;
 826                 end if;
 827             when OP_MTSPR =>
 828                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 829                     "=" & to_hstring(c_in);
 830                 if is_fast_spr(e_in.write_reg) then
 831                     result := c_in;
 832                     result_en := '1';
 833                     if decode_spr_num(e_in.insn) = SPR_XER then
 834                         v.e.xerc.so := c_in(63-32);
 835                         v.e.xerc.ov := c_in(63-33);
 836                         v.e.xerc.ca := c_in(63-34);
 837                         v.e.xerc.ov32 := c_in(63-44);
 838                         v.e.xerc.ca32 := c_in(63-45);
 839                         v.e.write_xerc_enable := '1';
 840                     end if;
 841                 else
 842                     -- slow spr
 843                     case decode_spr_num(e_in.insn) is
 844                     when SPR_DEC =>
 845                         ctrl_tmp.dec <= c_in;
 846                     when 724 =>     -- LOG_ADDR SPR
 847                         v.log_addr_spr := c_in(31 downto 0);
 848                     when others =>
 849                         -- mtspr to unimplemented SPRs should be a nop in
 850                         -- supervisor mode and a program interrupt for user mode
 851                         if ctrl.msr(MSR_PR) = '1' then
 852                             illegal := '1';
 853                         end if;
 854                     end case;
 855                 end if;
 856             when OP_POPCNT =>
 857                 result := popcnt_result;
 858                 result_en := '1';
 859             when OP_PRTY =>
 860                 result := parity_result;
 861                 result_en := '1';
 862             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 863                 result := rotator_result;
 864                 if e_in.output_carry = '1' then
 865                     set_carry(v.e, rotator_carry, rotator_carry);
 866                 end if;
 867                 result_en := '1';
 868
 869             when OP_ISYNC =>
 870                 f_out.redirect <= '1';
 871                 f_out.redirect_nia <= next_nia;
 872
 873             when OP_ICBI =>
 874                 icache_inval <= '1';
 875
 876             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 877                 v.e.valid := '0';
 878                 v.mul_in_progress := '1';
 879                 stall_out <= '1';
 880                 x_to_multiply.valid <= '1';
 881
 882             when OP_DIV | OP_DIVE | OP_MOD =>
 883                 v.e.valid := '0';
 884                 v.div_in_progress := '1';
 885                 stall_out <= '1';
 886                 x_to_divider.valid <= '1';
 887
 888             when others =>
 889                 terminate_out <= '1';
 890                 report "illegal";
 891             end case;
 892
 893             v.e.rc := e_in.rc and e_in.valid;
 894
 895             -- Update LR on the next cycle after a branch link
 896             --
 897             -- WARNING: The LR update isn't tracked by our hazard tracker. This
 898             --          will work (well I hope) because it only happens on branches
 899             --          which will flush all decoded instructions. By the time
 900             --          fetch catches up, we'll have the new LR. This will
 901             --          *not* work properly however if we have a branch predictor,
 902             --          in which case the solution would probably be to keep a
 903             --          local cache of the updated LR in execute1 (flushed on
 904             --          exceptions) that is used instead of the value from
 905             --          decode when its content is valid.
 906             if e_in.lr = '1' then
 907                 v.lr_update := '1';
 908                 v.next_lr := next_nia;
 909                 v.e.valid := '0';
 910                 report "Delayed LR update to " & to_hstring(next_nia);
 911                 stall_out <= '1';
 912             end if;
 913
 914         elsif e_in.valid = '1' then
 915             -- instruction for other units, i.e. LDST
 916             v.ldst_nia := e_in.nia;
 917             v.e.valid := '0';
 918             if e_in.unit = LDST then
 919                 lv.valid := '1';
 920             end if;
 921
 922         elsif r.lr_update = '1' then
 923             result_en := '1';
 924             result := r.next_lr;
 925             v.e.write_reg := fast_spr_num(SPR_LR);
 926             v.e.valid := '1';
 927         elsif r.cntz_in_progress = '1' then
 928             -- cnt[lt]z always takes two cycles
 929             result := countzero_result;
 930             result_en := '1';
 931             v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 932             v.e.rc := v.slow_op_rc;
 933             v.e.xerc := v.slow_op_xerc;
 934             v.e.valid := '1';
 935         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 936             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
 937                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
 938                 if r.mul_in_progress = '1' then
 939                     overflow := '0';
 940                     case r.slow_op_insn is
 941                         when OP_MUL_H32 =>
 942                             result := multiply_to_x.result(63 downto 32) &
 943                                       multiply_to_x.result(63 downto 32);
 944                         when OP_MUL_H64 =>
 945                             result := multiply_to_x.result(127 downto 64);
 946                         when others =>
 947                             -- i.e. OP_MUL_L64
 948                             result := multiply_to_x.result(63 downto 0);
 949                             overflow := multiply_to_x.overflow;
 950                     end case;
 951                 else
 952                     result := divider_to_x.write_reg_data;
 953                     overflow := divider_to_x.overflow;
 954                 end if;
 955                 result_en := '1';
 956                 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 957                 v.e.rc := v.slow_op_rc;
 958                 v.e.xerc := v.slow_op_xerc;
 959                 v.e.write_xerc_enable := v.slow_op_oe;
 960                 -- We must test oe because the RC update code in writeback
 961                 -- will use the xerc value to set CR0:SO so we must not clobber
 962                 -- xerc if OE wasn't set.
 963                 if v.slow_op_oe = '1' then
 964                     v.e.xerc.ov := overflow;
 965                     v.e.xerc.ov32 := overflow;
 966                     v.e.xerc.so := v.slow_op_xerc.so or overflow;
 967                 end if;
 968                 v.e.valid := '1';
 969             else
 970                 stall_out <= '1';
 971                 v.mul_in_progress := r.mul_in_progress;
 972                 v.div_in_progress := r.div_in_progress;
 973             end if;
 974         end if;
 975
 976         if illegal = '1' then
 977             exception := '1';
 978             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 979             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 980             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
 981             -- set bit 44 to indicate we have an illegal
 982             ctrl_tmp.srr1(63 - 44) <= '1';
 983             report "illegal";
 984         end if;
 985         if exception = '1' then
 986             v.e.exc_write_enable := '1';
 987             if exception_nextpc = '1' then
 988                 v.e.exc_write_data := next_nia;
 989             end if;
 990             ctrl_tmp.irq_state <= WRITE_SRR1;
 991             v.e.valid := '1';
 992         end if;
 993
 994         v.e.write_data := result;
 995         v.e.write_enable := result_en;
 996
 997         -- generate DSI or DSegI for load/store exceptions
 998         -- or ISI or ISegI for instruction fetch exceptions
 999         if l_in.exception = '1' then
1000             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
1001             if l_in.instr_fault = '0' then
1002                 if l_in.segment_fault = '0' then
1003                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#300#, 64));
1004                 else
1005                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#380#, 64));
1006                 end if;
1007             else
1008                 if l_in.segment_fault = '0' then
1009                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1010                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1011                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1012                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1013                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#400#, 64));
1014                 else
1015                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#480#, 64));
1016                 end if;
1017             end if;
1018             v.e.exc_write_enable := '1';
1019             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1020             v.e.exc_write_data := r.ldst_nia;
1021             report "ldst exception writing srr0=" & to_hstring(r.ldst_nia);
1022             ctrl_tmp.irq_state <= WRITE_SRR1;
1023             v.e.valid := '1';   -- complete the original load or store
1024         end if;
1025
1026         -- Outputs to loadstore1 (async)
1027         lv.op := e_in.insn_type;
1028         lv.nia := e_in.nia;
1029         lv.addr1 := a_in;
1030         lv.addr2 := b_in;
1031         lv.data := c_in;
1032         lv.write_reg := gspr_to_gpr(e_in.write_reg);
1033         lv.length := e_in.data_len;
1034         lv.byte_reverse := e_in.byte_reverse;
1035         lv.sign_extend := e_in.sign_extend;
1036         lv.update := e_in.update;
1037         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1038         lv.xerc := v.e.xerc;
1039         lv.reserve := e_in.reserve;
1040         lv.rc := e_in.rc;
1041         lv.insn := e_in.insn;
1042         -- decode l*cix and st*cix instructions here
1043         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1044             e_in.insn(5 downto 1) = "10101" then
1045             lv.ci := '1';
1046         end if;
1047         lv.virt_mode := ctrl.msr(MSR_DR);
1048         lv.priv_mode := not ctrl.msr(MSR_PR);
1049
1050         -- Update registers
1051         rin <= v;
1052
1053         -- update outputs
1054         --f_out <= r.f;
1055         l_out <= lv;
1056         e_out <= r.e;
1057         flush_out <= f_out.redirect;
1058
1059         exception_log <= exception;
1060         irq_valid_log <= irq_valid;
1061     end process;
1062
1063     ex1_log : process(clk)
1064     begin
1065         if rising_edge(clk) then
1066             log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1067                         ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1068                         exception_log &
1069                         irq_valid_log &
1070                         std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1071                         "000" &
1072                         r.e.write_enable &
1073                         r.e.valid &
1074                         f_out.redirect &
1075                         stall_out &
1076                         flush_out;
1077         end if;
1078     end process;
1079     log_out <= log_data;
1080 end architecture behaviour;