2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.crhelpers.all;
10 use work.insn_helpers.all;
11 use work.ppc_fx_insns.all;
15 EX1_BYPASS : boolean := true;
16 -- Non-zero to enable log data collection
17 LOG_LENGTH : natural := 0
24 flush_out : out std_ulogic;
25 busy_out : out std_ulogic;
27 e_in : in Decode2ToExecute1Type;
28 l_in : in Loadstore1ToExecute1Type;
30 ext_irq_in : std_ulogic;
33 l_out : out Execute1ToLoadstore1Type;
34 f_out : out Execute1ToFetch1Type;
36 e_out : out Execute1ToWritebackType;
38 dbg_msr_out : out std_ulogic_vector(63 downto 0);
40 icache_inval : out std_ulogic;
41 terminate_out : out std_ulogic;
43 log_out : out std_ulogic_vector(14 downto 0);
44 log_rd_addr : out std_ulogic_vector(31 downto 0);
45 log_rd_data : in std_ulogic_vector(63 downto 0);
46 log_wr_addr : in std_ulogic_vector(31 downto 0)
50 architecture behaviour of execute1 is
51 type reg_type is record
52 e : Execute1ToWritebackType;
53 f : Execute1ToFetch1Type;
55 terminate: std_ulogic;
56 lr_update : std_ulogic;
57 next_lr : std_ulogic_vector(63 downto 0);
58 mul_in_progress : std_ulogic;
59 mul_finish : std_ulogic;
60 div_in_progress : std_ulogic;
61 cntz_in_progress : std_ulogic;
62 slow_op_insn : insn_type_t;
63 slow_op_dest : gpr_index_t;
64 slow_op_rc : std_ulogic;
65 slow_op_oe : std_ulogic;
66 slow_op_xerc : xer_common_t;
67 last_nia : std_ulogic_vector(63 downto 0);
68 log_addr_spr : std_ulogic_vector(31 downto 0);
70 constant reg_type_init : reg_type :=
71 (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
72 busy => '0', lr_update => '0', terminate => '0',
73 mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
74 slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
75 next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
77 signal r, rin : reg_type;
79 signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
80 signal cr_in : std_ulogic_vector(31 downto 0);
82 signal valid_in : std_ulogic;
83 signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
84 signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
85 signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
86 signal rot_sign_ext: std_ulogic;
87 signal rotator_result: std_ulogic_vector(63 downto 0);
88 signal rotator_carry: std_ulogic;
89 signal logical_result: std_ulogic_vector(63 downto 0);
90 signal countzero_result: std_ulogic_vector(63 downto 0);
93 signal x_to_multiply: MultiplyInputType;
94 signal multiply_to_x: MultiplyOutputType;
97 signal x_to_divider: Execute1ToDividerType;
98 signal divider_to_x: DividerToExecute1Type;
100 -- random number generator signals
101 signal random_raw : std_ulogic_vector(63 downto 0);
102 signal random_cond : std_ulogic_vector(63 downto 0);
103 signal random_err : std_ulogic;
105 -- signals for logging
106 signal exception_log : std_ulogic;
107 signal irq_valid_log : std_ulogic;
109 type privilege_level is (USER, SUPER);
110 type op_privilege_array is array(insn_type_t) of privilege_level;
111 constant op_privilege: op_privilege_array := (
120 function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
123 if op_privilege(op) = SUPER then
125 elsif op = OP_MFSPR or op = OP_MTSPR then
126 return insn(20) = '1';
132 procedure set_carry(e: inout Execute1ToWritebackType;
133 carry32 : in std_ulogic;
134 carry : in std_ulogic) is
136 e.xerc.ca32 := carry32;
138 e.write_xerc_enable := '1';
141 procedure set_ov(e: inout Execute1ToWritebackType;
143 ov32 : in std_ulogic) is
150 e.write_xerc_enable := '1';
153 function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
154 ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
156 return (ca xor msb_r) and not (msb_a xor msb_b);
159 function decode_input_carry(ic : carry_in_t;
160 xerc : xer_common_t) return std_ulogic is
174 function msr_copy(msr: std_ulogic_vector(63 downto 0))
175 return std_ulogic_vector is
176 variable msr_out: std_ulogic_vector(63 downto 0);
179 -- Defined MSR bits are classified as either full func-
180 -- tion or partial function. Full function MSR bits are
181 -- saved in SRR1 or HSRR1 when an interrupt other
182 -- than a System Call Vectored interrupt occurs and
183 -- restored by rfscv, rfid, or hrfid, while partial func-
184 -- tion MSR bits are not saved or restored.
185 -- Full function MSR bits lie in the range 0:32, 37:41, and
186 -- 48:63, and partial function MSR bits lie in the range
187 -- 33:36 and 42:47. (Note this is IBM bit numbering).
188 msr_out := (others => '0');
189 msr_out(63 downto 31) := msr(63 downto 31);
190 msr_out(26 downto 22) := msr(26 downto 22);
191 msr_out(15 downto 0) := msr(15 downto 0);
195 -- Tell vivado to keep the hierarchy for the random module so that the
196 -- net names in the xdc file match.
197 attribute keep_hierarchy : string;
198 attribute keep_hierarchy of random_0 : label is "yes";
202 rotator_0: entity work.rotator
206 shift => b_in(6 downto 0),
208 is_32bit => e_in.is_32bit,
209 right_shift => right_shift,
210 arith => e_in.is_signed,
211 clear_left => rot_clear_left,
212 clear_right => rot_clear_right,
213 sign_ext_rs => rot_sign_ext,
214 result => rotator_result,
215 carry_out => rotator_carry
218 logical_0: entity work.logical
222 op => e_in.insn_type,
223 invert_in => e_in.invert_a,
224 invert_out => e_in.invert_out,
225 result => logical_result,
226 datalen => e_in.data_len
229 countzero_0: entity work.zero_counter
233 count_right => e_in.insn(10),
234 is_32bit => e_in.is_32bit,
235 result => countzero_result
238 multiply_0: entity work.multiply
241 m_in => x_to_multiply,
242 m_out => multiply_to_x
245 divider_0: entity work.divider
249 d_in => x_to_divider,
250 d_out => divider_to_x
253 random_0: entity work.random
261 dbg_msr_out <= ctrl.msr;
262 log_rd_addr <= r.log_addr_spr;
264 a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
265 b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
266 c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
268 busy_out <= l_in.busy or r.busy;
269 valid_in <= e_in.valid and not busy_out;
271 terminate_out <= r.terminate;
273 execute1_0: process(clk)
275 if rising_edge(clk) then
278 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
279 ctrl.irq_state <= WRITE_SRR0;
283 assert not (r.lr_update = '1' and valid_in = '1')
284 report "LR update collision with valid in EX1"
286 if r.lr_update = '1' then
287 report "LR update to " & to_hstring(r.next_lr);
293 execute1_1: process(all)
294 variable v : reg_type;
295 variable a_inv : std_ulogic_vector(63 downto 0);
296 variable result : std_ulogic_vector(63 downto 0);
297 variable newcrf : std_ulogic_vector(3 downto 0);
298 variable sum_with_carry : std_ulogic_vector(64 downto 0);
299 variable result_en : std_ulogic;
300 variable crnum : crnum_t;
301 variable crbit : integer range 0 to 31;
302 variable scrnum : crnum_t;
303 variable lo, hi : integer;
304 variable sh, mb, me : std_ulogic_vector(5 downto 0);
305 variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
306 variable bo, bi : std_ulogic_vector(4 downto 0);
307 variable bf, bfa : std_ulogic_vector(2 downto 0);
308 variable cr_op : std_ulogic_vector(9 downto 0);
309 variable cr_operands : std_ulogic_vector(1 downto 0);
310 variable bt, ba, bb : std_ulogic_vector(4 downto 0);
311 variable btnum, banum, bbnum : integer range 0 to 31;
312 variable crresult : std_ulogic;
313 variable l : std_ulogic;
314 variable next_nia : std_ulogic_vector(63 downto 0);
315 variable carry_32, carry_64 : std_ulogic;
316 variable sign1, sign2 : std_ulogic;
317 variable abs1, abs2 : signed(63 downto 0);
318 variable overflow : std_ulogic;
319 variable zerohi, zerolo : std_ulogic;
320 variable msb_a, msb_b : std_ulogic;
321 variable a_lt : std_ulogic;
322 variable lv : Execute1ToLoadstore1Type;
323 variable irq_valid : std_ulogic;
324 variable exception : std_ulogic;
325 variable exception_nextpc : std_ulogic;
326 variable trapval : std_ulogic_vector(4 downto 0);
327 variable illegal : std_ulogic;
328 variable is_branch : std_ulogic;
329 variable taken_branch : std_ulogic;
330 variable abs_branch : std_ulogic;
331 variable spr_val : std_ulogic_vector(63 downto 0);
332 variable addend : std_ulogic_vector(127 downto 0);
334 result := (others => '0');
335 sum_with_carry := (others => '0');
337 newcrf := (others => '0');
343 v.e := Execute1ToWritebackInit;
344 lv := Execute1ToLoadstore1Init;
347 -- XER forwarding. To avoid having to track XER hazards, we
348 -- use the previously latched value.
350 -- If the XER was modified by a multiply or a divide, those are
351 -- single issue, we'll get the up to date value from decode2 from
352 -- the register file.
354 -- If it was modified by an instruction older than the previous
355 -- one in EX1, it will have also hit writeback and will be up
356 -- to date in decode2.
358 -- That leaves us with the case where it was updated by the previous
359 -- instruction in EX1. In that case, we can forward it back here.
361 -- This will break if we allow pipelining of multiply and divide,
362 -- but ideally, those should go via EX1 anyway and run as a state
363 -- machine from here.
365 -- One additional hazard to beware of is an XER:SO modifying instruction
366 -- in EX1 followed immediately by a store conditional. Due to our
367 -- writeback latency, the store will go down the LSU with the previous
368 -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
370 -- We will need to handle that if we ever make stcx. not single issue
372 -- We always pass a valid XER value downto writeback even when
373 -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
374 -- to work for RC instructions.
376 if r.e.write_xerc_enable = '1' then
377 v.e.xerc := r.e.xerc;
379 v.e.xerc := e_in.xerc;
384 if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
386 if r.e.write_cr_mask(i) = '1' then
387 cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
393 v.mul_in_progress := '0';
394 v.div_in_progress := '0';
395 v.cntz_in_progress := '0';
399 if e_in.invert_a = '0' then
404 sum_with_carry := ppc_adde(a_inv, b_in,
405 decode_input_carry(e_in.input_carry, v.e.xerc));
407 -- signals to multiply and divide units
410 if e_in.is_signed = '1' then
411 if e_in.is_32bit = '1' then
419 -- take absolute values
421 abs1 := signed(a_in);
423 abs1 := - signed(a_in);
426 abs2 := signed(b_in);
428 abs2 := - signed(b_in);
431 x_to_multiply <= MultiplyInputInit;
432 x_to_multiply.is_32bit <= e_in.is_32bit;
434 x_to_divider <= Execute1ToDividerInit;
435 x_to_divider.is_signed <= e_in.is_signed;
436 x_to_divider.is_32bit <= e_in.is_32bit;
437 if e_in.insn_type = OP_MOD then
438 x_to_divider.is_modulus <= '1';
441 addend := (others => '0');
442 if e_in.insn(26) = '0' then
443 -- integer multiply-add, major op 4 (if it is a multiply)
444 addend(63 downto 0) := c_in;
445 if e_in.is_signed = '1' then
446 addend(127 downto 64) := (others => c_in(63));
449 if (sign1 xor sign2) = '1' then
450 addend := not addend;
453 x_to_multiply.not_result <= sign1 xor sign2;
454 x_to_multiply.addend <= addend;
455 x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
456 if e_in.is_32bit = '0' then
458 x_to_multiply.data1 <= std_ulogic_vector(abs1);
459 x_to_multiply.data2 <= std_ulogic_vector(abs2);
460 if e_in.insn_type = OP_DIVE then
461 x_to_divider.is_extended <= '1';
463 x_to_divider.dividend <= std_ulogic_vector(abs1);
464 x_to_divider.divisor <= std_ulogic_vector(abs2);
467 x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
468 x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
469 x_to_divider.is_extended <= '0';
470 if e_in.insn_type = OP_DIVE then -- extended forms
471 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
473 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
475 x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
479 -- FIXME: run at 512MHz not core freq
480 ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
481 ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
484 if ctrl.msr(MSR_EE) = '1' then
485 if ctrl.dec(63) = '1' then
486 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
487 report "IRQ valid: DEC";
489 elsif ext_irq_in = '1' then
490 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
491 report "IRQ valid: External";
499 -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
500 v.f.virt_mode := ctrl.msr(MSR_IR);
501 v.f.priv_mode := not ctrl.msr(MSR_PR);
502 v.f.big_endian := not ctrl.msr(MSR_LE);
503 v.f.mode_32bit := not ctrl.msr(MSR_SF);
505 -- Next insn adder used in a couple of places
506 next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
508 -- rotator control signals
509 right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
510 rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
511 rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
512 rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
514 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
515 ctrl_tmp.irq_state <= WRITE_SRR0;
518 exception_nextpc := '0';
519 v.e.exc_write_enable := '0';
520 v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
521 v.e.exc_write_data := e_in.nia;
522 if valid_in = '1' then
523 v.last_nia := e_in.nia;
526 v.e.mode_32bit := not ctrl.msr(MSR_SF);
528 if ctrl.irq_state = WRITE_SRR1 then
529 v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
530 v.e.exc_write_data := ctrl.srr1;
531 v.e.exc_write_enable := '1';
532 ctrl_tmp.msr(MSR_SF) <= '1';
533 ctrl_tmp.msr(MSR_EE) <= '0';
534 ctrl_tmp.msr(MSR_PR) <= '0';
535 ctrl_tmp.msr(MSR_IR) <= '0';
536 ctrl_tmp.msr(MSR_DR) <= '0';
537 ctrl_tmp.msr(MSR_RI) <= '0';
538 ctrl_tmp.msr(MSR_LE) <= '1';
540 report "Writing SRR1: " & to_hstring(ctrl.srr1);
542 elsif irq_valid = '1' and valid_in = '1' then
543 -- we need two cycles to write srr0 and 1
544 -- will need more when we have to write HEIR
545 -- Don't deliver the interrupt until we have a valid instruction
546 -- coming in, so we have a valid NIA to put in SRR0.
549 elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
550 instr_is_privileged(e_in.insn_type, e_in.insn) then
551 -- generate a program interrupt
553 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
554 -- set bit 45 to indicate privileged instruction type interrupt
555 ctrl_tmp.srr1(63 - 45) <= '1';
556 report "privileged instruction";
558 elsif valid_in = '1' and e_in.unit = ALU then
560 report "execute nia " & to_hstring(e_in.nia);
563 v.e.write_reg := e_in.write_reg;
564 v.slow_op_insn := e_in.insn_type;
565 v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
566 v.slow_op_rc := e_in.rc;
567 v.slow_op_oe := e_in.oe;
568 v.slow_op_xerc := v.e.xerc;
570 case_0: case e_in.insn_type is
573 -- we need two cycles to write srr0 and 1
574 -- will need more when we have to write HEIR
577 -- check bit 1 of the instruction is 1 so we know this is sc;
578 -- 0 would mean scv, so generate an illegal instruction interrupt
579 -- we need two cycles to write srr0 and 1
580 if e_in.insn(1) = '1' then
582 exception_nextpc := '1';
583 v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
589 -- check bits 1-10 of the instruction to make sure it's attn
590 -- if not then it is illegal
591 if e_in.insn(10 downto 1) = "0100000000" then
599 when OP_ADD | OP_CMP | OP_TRAP =>
600 result := sum_with_carry(63 downto 0);
601 carry_32 := result(32) xor a_inv(32) xor b_in(32);
602 carry_64 := sum_with_carry(64);
603 if e_in.insn_type = OP_ADD then
604 if e_in.output_carry = '1' then
605 if e_in.input_carry /= OV then
606 set_carry(v.e, carry_32, carry_64);
608 v.e.xerc.ov := carry_64;
609 v.e.xerc.ov32 := carry_32;
610 v.e.write_xerc_enable := '1';
613 if e_in.oe = '1' then
615 calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
616 calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
620 -- trap, CMP and CMPL instructions
621 -- Note, we have done RB - RA, not RA - RB
622 if e_in.insn_type = OP_CMP then
623 l := insn_l(e_in.insn);
625 l := not e_in.is_32bit;
627 zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
628 zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
629 if zerolo = '1' and (l = '0' or zerohi = '1') then
642 if msb_a /= msb_b then
643 -- Subtraction might overflow, but
644 -- comparison is clear from MSB difference.
645 -- for signed, 0 is greater; for unsigned, 1 is greater
646 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
648 -- Subtraction cannot overflow since MSBs are equal.
649 -- carry = 1 indicates RA is smaller (signed or unsigned)
650 a_lt := (not l and carry_32) or (l and carry_64);
651 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
654 if e_in.insn_type = OP_CMP then
655 if e_in.is_signed = '1' then
656 newcrf := trapval(4 downto 2) & v.e.xerc.so;
658 newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
660 bf := insn_bf(e_in.insn);
661 crnum := to_integer(unsigned(bf));
662 v.e.write_cr_enable := '1';
663 v.e.write_cr_mask := num_to_fxm(crnum);
667 v.e.write_cr_data(hi downto lo) := newcrf;
670 -- trap instructions (tw, twi, td, tdi)
671 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
672 -- set bit 46 to say trap occurred
673 ctrl_tmp.srr1(63 - 46) <= '1';
674 if or (trapval and insn_to(e_in.insn)) = '1' then
675 -- generate trap-type program interrupt
682 result := (others => '0');
683 for i in 0 to 14 loop
686 if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
687 result(lo + 3 downto lo) := "0110";
690 if sum_with_carry(64) = '0' then
691 result(63 downto 60) := "0110";
695 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
696 bf := insn_bf(e_in.insn);
697 crnum := to_integer(unsigned(bf));
698 v.e.write_cr_enable := '1';
699 v.e.write_cr_mask := num_to_fxm(crnum);
700 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
701 newcrf & newcrf & newcrf & newcrf;
703 newcrf := ppc_cmpeqb(a_in, b_in);
704 bf := insn_bf(e_in.insn);
705 crnum := to_integer(unsigned(bf));
706 v.e.write_cr_enable := '1';
707 v.e.write_cr_mask := num_to_fxm(crnum);
708 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
709 newcrf & newcrf & newcrf & newcrf;
710 when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
712 result := logical_result;
717 abs_branch := insn_aa(e_in.insn);
720 bo := insn_bo(e_in.insn);
721 bi := insn_bi(e_in.insn);
722 if bo(4-2) = '0' then
723 result := std_ulogic_vector(unsigned(a_in) - 1);
725 v.e.write_reg := fast_spr_num(SPR_CTR);
728 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
729 abs_branch := insn_aa(e_in.insn);
732 -- read_data2 is target register (CTR, LR or TAR)
733 bo := insn_bo(e_in.insn);
734 bi := insn_bi(e_in.insn);
735 if bo(4-2) = '0' and e_in.insn(10) = '0' then
736 result := std_ulogic_vector(unsigned(a_in) - 1);
738 v.e.write_reg := fast_spr_num(SPR_CTR);
741 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
745 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
746 v.f.priv_mode := not a_in(MSR_PR);
747 v.f.big_endian := not a_in(MSR_LE);
748 v.f.mode_32bit := not a_in(MSR_SF);
749 -- Can't use msr_copy here because the partial function MSR
750 -- bits should be left unchanged, not zeroed.
751 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
752 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
753 ctrl_tmp.msr(15 downto 0) <= a_in(15 downto 0);
754 if a_in(MSR_PR) = '1' then
755 ctrl_tmp.msr(MSR_EE) <= '1';
756 ctrl_tmp.msr(MSR_IR) <= '1';
757 ctrl_tmp.msr(MSR_DR) <= '1';
759 -- mark this as a branch so CFAR gets updated
766 v.cntz_in_progress := '1';
769 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
770 if cr_in(31-crbit) = '1' then
777 cr_op := insn_cr(e_in.insn);
778 report "CR OP " & to_hstring(cr_op);
779 if cr_op(0) = '0' then -- MCRF
780 bf := insn_bf(e_in.insn);
781 bfa := insn_bfa(e_in.insn);
782 v.e.write_cr_enable := '1';
783 crnum := to_integer(unsigned(bf));
784 scrnum := to_integer(unsigned(bfa));
785 v.e.write_cr_mask := num_to_fxm(crnum);
790 newcrf := cr_in(hi downto lo);
796 v.e.write_cr_data(hi downto lo) := newcrf;
799 v.e.write_cr_enable := '1';
800 bt := insn_bt(e_in.insn);
801 ba := insn_ba(e_in.insn);
802 bb := insn_bb(e_in.insn);
803 btnum := 31 - to_integer(unsigned(bt));
804 banum := 31 - to_integer(unsigned(ba));
805 bbnum := 31 - to_integer(unsigned(bb));
806 -- Bits 5-8 of cr_op give the truth table of the requested
808 cr_operands := cr_in(banum) & cr_in(bbnum);
809 crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
810 v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
811 for i in 0 to 31 loop
813 v.e.write_cr_data(i) := crresult;
815 v.e.write_cr_data(i) := cr_in(i);
820 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
821 bf := insn_bf(e_in.insn);
822 crnum := to_integer(unsigned(bf));
823 v.e.write_cr_enable := '1';
824 v.e.write_cr_mask := num_to_fxm(crnum);
825 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
826 newcrf & newcrf & newcrf & newcrf;
828 if random_err = '0' then
829 case e_in.insn(17 downto 16) is
831 result := x"00000000" & random_cond(31 downto 0);
833 result := random_raw;
835 result := random_cond;
838 result := (others => '1');
845 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
846 "=" & to_hstring(a_in);
848 if is_fast_spr(e_in.read_reg1) then
850 if decode_spr_num(e_in.insn) = SPR_XER then
851 -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
852 result(63 downto 32) := (others => '0');
853 result(63-32) := v.e.xerc.so;
854 result(63-33) := v.e.xerc.ov;
855 result(63-34) := v.e.xerc.ca;
856 result(63-35 downto 63-43) := "000000000";
857 result(63-44) := v.e.xerc.ov32;
858 result(63-45) := v.e.xerc.ca32;
862 case decode_spr_num(e_in.insn) is
866 spr_val(63 downto 32) := (others => '0');
867 spr_val(31 downto 0) := ctrl.tb(63 downto 32);
871 spr_val := ctrl.cfar;
873 spr_val(63 downto 32) := (others => '0');
874 spr_val(31 downto 0) := PVR_MICROWATT;
875 when 724 => -- LOG_ADDR SPR
876 spr_val := log_wr_addr & r.log_addr_spr;
877 when 725 => -- LOG_DATA SPR
878 spr_val := log_rd_data;
879 v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
881 -- mfspr from unimplemented SPRs should be a nop in
882 -- supervisor mode and a program interrupt for user mode
883 if ctrl.msr(MSR_PR) = '1' then
890 if e_in.insn(20) = '0' then
892 result := x"00000000" & cr_in;
895 crnum := fxm_to_num(insn_fxm(e_in.insn));
896 result := (others => '0');
901 result(hi downto lo) := cr_in(hi downto lo);
907 v.e.write_cr_enable := '1';
908 if e_in.insn(20) = '0' then
910 v.e.write_cr_mask := insn_fxm(e_in.insn);
912 -- mtocrf: We require one hot priority encoding here
913 crnum := fxm_to_num(insn_fxm(e_in.insn));
914 v.e.write_cr_mask := num_to_fxm(crnum);
916 v.e.write_cr_data := c_in(31 downto 0);
918 if e_in.insn(16) = '1' then
919 -- just update EE and RI
920 ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
921 ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
923 -- Architecture says to leave out bits 3 (HV), 51 (ME)
924 -- and 63 (LE) (IBM bit numbering)
925 ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
926 ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
927 ctrl_tmp.msr(11 downto 1) <= c_in(11 downto 1);
928 if c_in(MSR_PR) = '1' then
929 ctrl_tmp.msr(MSR_EE) <= '1';
930 ctrl_tmp.msr(MSR_IR) <= '1';
931 ctrl_tmp.msr(MSR_DR) <= '1';
935 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
936 "=" & to_hstring(c_in);
937 if is_fast_spr(e_in.write_reg) then
940 if decode_spr_num(e_in.insn) = SPR_XER then
941 v.e.xerc.so := c_in(63-32);
942 v.e.xerc.ov := c_in(63-33);
943 v.e.xerc.ca := c_in(63-34);
944 v.e.xerc.ov32 := c_in(63-44);
945 v.e.xerc.ca32 := c_in(63-45);
946 v.e.write_xerc_enable := '1';
950 case decode_spr_num(e_in.insn) is
952 ctrl_tmp.dec <= c_in;
953 when 724 => -- LOG_ADDR SPR
954 v.log_addr_spr := c_in(31 downto 0);
956 -- mtspr to unimplemented SPRs should be a nop in
957 -- supervisor mode and a program interrupt for user mode
958 if ctrl.msr(MSR_PR) = '1' then
963 when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
964 result := rotator_result;
965 if e_in.output_carry = '1' then
966 set_carry(v.e, rotator_carry, rotator_carry);
970 bfa := insn_bfa(e_in.insn);
971 crbit := to_integer(unsigned(bfa)) * 4;
972 result := (others => '0');
973 if cr_in(31 - crbit) = '1' then
974 result := (others => '1');
975 elsif cr_in(30 - crbit) = '1' then
981 v.f.redirect_nia := next_nia;
986 when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
988 v.mul_in_progress := '1';
990 x_to_multiply.valid <= '1';
992 when OP_DIV | OP_DIVE | OP_MOD =>
994 v.div_in_progress := '1';
996 x_to_divider.valid <= '1';
1003 v.e.rc := e_in.rc and valid_in;
1005 -- Mispredicted branches cause a redirect
1006 if is_branch = '1' then
1007 if taken_branch = '1' then
1008 ctrl_tmp.cfar <= e_in.nia;
1010 if e_in.br_pred = '0' then
1011 if abs_branch = '1' then
1012 v.f.redirect_nia := b_in;
1014 v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
1017 v.f.redirect_nia := next_nia;
1019 if taken_branch /= e_in.br_pred then
1020 v.f.redirect := '1';
1024 -- Update LR on the next cycle after a branch link
1025 -- If we're not writing back anything else, we can write back LR
1026 -- this cycle, otherwise we take an extra cycle. We use the
1027 -- exc_write path since next_nia is written through that path
1029 if e_in.lr = '1' then
1030 if result_en = '0' then
1031 v.e.exc_write_enable := '1';
1032 v.e.exc_write_data := next_nia;
1033 v.e.exc_write_reg := fast_spr_num(SPR_LR);
1036 v.next_lr := next_nia;
1038 report "Delayed LR update to " & to_hstring(next_nia);
1043 elsif valid_in = '1' then
1044 -- instruction for other units, i.e. LDST
1045 if e_in.unit = LDST then
1049 elsif r.f.redirect = '1' then
1051 elsif r.lr_update = '1' then
1052 v.e.exc_write_enable := '1';
1053 v.e.exc_write_data := r.next_lr;
1054 v.e.exc_write_reg := fast_spr_num(SPR_LR);
1056 elsif r.cntz_in_progress = '1' then
1057 -- cnt[lt]z always takes two cycles
1058 result := countzero_result;
1060 v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1061 v.e.rc := r.slow_op_rc;
1062 v.e.xerc := r.slow_op_xerc;
1064 elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1065 if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1066 (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1067 if r.mul_in_progress = '1' then
1069 case r.slow_op_insn is
1071 result := multiply_to_x.result(63 downto 32) &
1072 multiply_to_x.result(63 downto 32);
1074 result := multiply_to_x.result(127 downto 64);
1077 result := multiply_to_x.result(63 downto 0);
1080 result := divider_to_x.write_reg_data;
1081 overflow := divider_to_x.overflow;
1083 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1084 -- have to wait until next cycle for overflow indication
1085 v.mul_finish := '1';
1089 v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1090 v.e.rc := r.slow_op_rc;
1091 v.e.xerc := r.slow_op_xerc;
1092 v.e.write_xerc_enable := r.slow_op_oe;
1093 -- We must test oe because the RC update code in writeback
1094 -- will use the xerc value to set CR0:SO so we must not clobber
1095 -- xerc if OE wasn't set.
1096 if r.slow_op_oe = '1' then
1097 v.e.xerc.ov := overflow;
1098 v.e.xerc.ov32 := overflow;
1099 v.e.xerc.so := r.slow_op_xerc.so or overflow;
1105 v.mul_in_progress := r.mul_in_progress;
1106 v.div_in_progress := r.div_in_progress;
1108 elsif r.mul_finish = '1' then
1109 result := r.e.write_data;
1111 v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1112 v.e.rc := r.slow_op_rc;
1113 v.e.xerc := r.slow_op_xerc;
1114 v.e.write_xerc_enable := r.slow_op_oe;
1115 v.e.xerc.ov := multiply_to_x.overflow;
1116 v.e.xerc.ov32 := multiply_to_x.overflow;
1117 v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1121 if illegal = '1' then
1123 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1124 -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1125 -- set bit 44 to indicate we have an illegal
1126 ctrl_tmp.srr1(63 - 44) <= '1';
1129 if exception = '1' then
1130 v.e.exc_write_enable := '1';
1131 if exception_nextpc = '1' then
1132 v.e.exc_write_data := next_nia;
1136 v.e.write_data := result;
1137 v.e.write_enable := result_en and not exception;
1139 -- generate DSI or DSegI for load/store exceptions
1140 -- or ISI or ISegI for instruction fetch exceptions
1141 if l_in.exception = '1' then
1142 if l_in.alignment = '1' then
1143 v.f.redirect_nia := std_logic_vector(to_unsigned(16#600#, 64));
1144 elsif l_in.instr_fault = '0' then
1145 if l_in.segment_fault = '0' then
1146 v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1148 v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1151 if l_in.segment_fault = '0' then
1152 ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1153 ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1154 ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1155 ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1156 v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1158 v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1161 v.e.exc_write_enable := '1';
1162 v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1163 v.e.exc_write_data := r.last_nia;
1164 report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1167 if exception = '1' or l_in.exception = '1' then
1168 ctrl_tmp.irq_state <= WRITE_SRR1;
1169 v.f.redirect := '1';
1170 v.f.virt_mode := '0';
1171 v.f.priv_mode := '1';
1172 -- XXX need an interrupt LE bit here, e.g. from LPCR
1173 v.f.big_endian := '0';
1174 v.f.mode_32bit := '0';
1177 if v.f.redirect = '1' then
1182 -- Outputs to loadstore1 (async)
1183 lv.op := e_in.insn_type;
1188 lv.write_reg := gspr_to_gpr(e_in.write_reg);
1189 lv.length := e_in.data_len;
1190 lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1191 lv.sign_extend := e_in.sign_extend;
1192 lv.update := e_in.update;
1193 lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1194 lv.xerc := v.e.xerc;
1195 lv.reserve := e_in.reserve;
1197 lv.insn := e_in.insn;
1198 -- decode l*cix and st*cix instructions here
1199 if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1200 e_in.insn(5 downto 1) = "10101" then
1203 lv.virt_mode := ctrl.msr(MSR_DR);
1204 lv.priv_mode := not ctrl.msr(MSR_PR);
1205 lv.mode_32bit := not ctrl.msr(MSR_SF);
1214 flush_out <= f_out.redirect;
1216 exception_log <= exception;
1217 irq_valid_log <= irq_valid;
1220 e1_log: if LOG_LENGTH > 0 generate
1221 signal log_data : std_ulogic_vector(14 downto 0);
1223 ex1_log : process(clk)
1225 if rising_edge(clk) then
1226 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1227 ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1230 std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1239 log_out <= log_data;
1241 end architecture behaviour;