execute2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.crhelpers.all;
   8 use work.ppc_fx_insns.all;
   9
  10 -- 2 cycle ALU
  11 -- We handle rc form instructions here
  12
  13 entity execute2 is
  14     port (
  15         clk   : in std_ulogic;
  16
  17         e_in  : in Execute1ToExecute2Type;
  18         e_out : out Execute2ToWritebackType
  19         );
  20 end execute2;
  21
  22 architecture behave of execute2 is
  23     signal r, rin : Execute2ToWritebackType;
  24 begin
  25     execute2_0: process(clk)
  26     begin
  27         if rising_edge(clk) then
  28             r <= rin;
  29         end if;
  30     end process;
  31
  32     execute2_1: process(all)
  33         variable v : Execute2ToWritebackType;
  34     begin
  35         v := rin;
  36
  37         v.valid := e_in.valid;
  38         v.write_enable := e_in.write_enable;
  39         v.write_reg := e_in.write_reg;
  40         v.write_data := e_in.write_data;
  41         v.write_cr_enable := e_in.write_cr_enable;
  42         v.write_cr_mask := e_in.write_cr_mask;
  43         v.write_cr_data := e_in.write_cr_data;
  44
  45         if e_in.valid = '1' and e_in.rc = '1' then
  46             v.write_cr_enable := '1';
  47             v.write_cr_mask := num_to_fxm(0);
  48             v.write_cr_data := ppc_cmpi('1', e_in.write_data, x"0000") & x"0000000";
  49         end if;
  50
  51         -- Update registers
  52         rin <= v;
  53
  54         -- Update outputs
  55         e_out <= r;
  56     end process;
  57 end;