73e409272bd136db75bde5090541a55c7ff9aa27
1 # generate add.il ilang file with: python3 add.py
4 from nmigen
import Elaboratable
, Signal
, Module
5 from nmigen
.cli
import rtlil
8 # clone with $ git clone gitolite3@git.libre-soc.org:c4m-jtag.git
9 # $ git clone gitolite3@git.libre-soc.org:nmigen-soc.git
10 # for each: $ python3 setup.py develop --user
12 from c4m
.nmigen
.jtag
.tap
import TAP
, IOType
15 class ADD(Elaboratable
):
16 def __init__(self
, width
):
17 self
.a
= Signal(width
)
18 self
.b
= Signal(width
)
19 self
.f
= Signal(width
)
22 self
.jtag
= TAP(ir_width
=3)
23 self
.jtag
.bus
.tck
.name
= 'tck'
24 self
.jtag
.bus
.tms
.name
= 'tms'
25 self
.jtag
.bus
.tdo
.name
= 'tdo'
26 self
.jtag
.bus
.tdi
.name
= 'tdi'
28 # have to create at least one shift register
29 self
.sr
= self
.jtag
.add_shiftreg(ircode
=4, length
=3)
32 self
.ios
= self
.jtag
.add_io(name
="test", iotype
=IOType
.In
)
34 def elaborate(self
, platform
):
37 m
.submodules
.jtag
= jtag
= self
.jtag
38 m
.d
.comb
+= self
.sr
.i
.eq(self
.sr
.o
) # loopback test
41 m
.d
.sync
+= self
.f
.eq(self
.a
+ self
.b
)
46 def create_ilang(dut
, ports
, test_name
):
47 vl
= rtlil
.convert(dut
, name
=test_name
, ports
=ports
)
48 with
open("%s.il" % test_name
, "w") as f
:
51 if __name__
== "__main__":
53 create_ilang(alu
, [alu
.a
, alu
.b
, alu
.f
,
57 alu
.jtag
.bus
.tdi
], "add")