rename ls180sram4k to ls180

[soclayout.git] / experiments5 / alu_hier_altered.vst

-- =======================================================================
-- Coriolis Structural VHDL Driver
-- Generated on Feb 28, 2020, 20:44
-- 
-- To be interoperable with Alliance, it uses it's special VHDL subset.
-- ("man vhdl" under Alliance for more informations)
-- =======================================================================

entity alu_hier_altered is
  port ( clk : in bit
       ; op  : in bit
       ; rst : in bit
       ; a   : in bit_vector(15 downto 0)
       ; b   : in bit_vector(15 downto 0)
       ; o   : out bit_vector(15 downto 0)
       ; vdd : in bit
       ; vss : in bit
       );
end alu_hier_altered;

architecture structural of alu_hier_altered is

  component add
    port ( a   : in bit_vector(15 downto 0)
         ; b   : in bit_vector(15 downto 0)
         ; o   : out bit_vector(15 downto 0)
         ; vdd : in bit
         ; vss : in bit
         );
  end component;

  component no2_x1
    port ( i0  : in bit
         ; i1  : in bit
         ; nq  : out bit
         ; vdd : in bit
         ; vss : in bit
         );
  end component;

  component sub
    port ( a   : in bit_vector(15 downto 0)
         ; b   : in bit_vector(15 downto 0)
         ; o   : out bit_vector(15 downto 0)
         ; vdd : in bit
         ; vss : in bit
         );
  end component;

  component nmx2_x1
    port ( cmd : in bit
         ; i0  : in bit
         ; i1  : in bit
         ; nq  : out bit
         ; vdd : in bit
         ; vss : in bit
         );
  end component;

  component sff1_x4
    port ( ck  : in bit
         ; i   : in bit
         ; q   : out bit
         ; vdd : in bit
         ; vss : in bit
         );
  end component;

  signal abc_828_new_n51 :  bit;
  signal abc_828_new_n53 :  bit;
  signal abc_828_new_n55 :  bit;
  signal abc_828_new_n57 :  bit;
  signal abc_828_new_n59 :  bit;
  signal abc_828_new_n61 :  bit;
  signal abc_828_new_n63 :  bit;
  signal abc_828_new_n65 :  bit;
  signal abc_828_new_n67 :  bit;
  signal abc_828_new_n69 :  bit;
  signal abc_828_new_n71 :  bit;
  signal abc_828_new_n73 :  bit;
  signal abc_828_new_n75 :  bit;
  signal abc_828_new_n77 :  bit;
  signal abc_828_new_n79 :  bit;
  signal abc_828_new_n81 :  bit;
  signal blockagenet     :  bit;
  signal add_o           :  bit_vector(15 downto 0);
  signal o_next          :  bit_vector(15 downto 0);
  signal sub_o           :  bit_vector(15 downto 0);


begin

  subckt_0_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(0)
           , i1  => sub_o(0)
           , nq  => abc_828_new_n51
           , vdd => vdd
           , vss => vss
           );

  subckt_28_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(14)
           , i1  => sub_o(14)
           , nq  => abc_828_new_n79
           , vdd => vdd
           , vss => vss
           );

  subckt_31_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n81
           , i1  => rst
           , nq  => o_next(15)
           , vdd => vdd
           , vss => vss
           );

  subckt_36_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(4)
           , q   => o(4)
           , vdd => vdd
           , vss => vss
           );

  subckt_44_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(12)
           , q   => o(12)
           , vdd => vdd
           , vss => vss
           );

  subckt_14_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(7)
           , i1  => sub_o(7)
           , nq  => abc_828_new_n65
           , vdd => vdd
           , vss => vss
           );

  subckt_21_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n71
           , i1  => rst
           , nq  => o_next(10)
           , vdd => vdd
           , vss => vss
           );

  subckt_22_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(11)
           , i1  => sub_o(11)
           , nq  => abc_828_new_n73
           , vdd => vdd
           , vss => vss
           );

  subckt_23_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n73
           , i1  => rst
           , nq  => o_next(11)
           , vdd => vdd
           , vss => vss
           );

  subckt_35_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(3)
           , q   => o(3)
           , vdd => vdd
           , vss => vss
           );

  subckt_30_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(15)
           , i1  => sub_o(15)
           , nq  => abc_828_new_n81
           , vdd => vdd
           , vss => vss
           );

  subckt_29_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n79
           , i1  => rst
           , nq  => o_next(14)
           , vdd => vdd
           , vss => vss
           );

  subckt_27_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n77
           , i1  => rst
           , nq  => o_next(13)
           , vdd => vdd
           , vss => vss
           );

  subckt_25_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n75
           , i1  => rst
           , nq  => o_next(12)
           , vdd => vdd
           , vss => vss
           );

  subckt_4_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(2)
           , i1  => sub_o(2)
           , nq  => abc_828_new_n55
           , vdd => vdd
           , vss => vss
           );

  subckt_1_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n51
           , i1  => rst
           , nq  => o_next(0)
           , vdd => vdd
           , vss => vss
           );

  subckt_43_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(11)
           , q   => o(11)
           , vdd => vdd
           , vss => vss
           );

  subckt_15_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n65
           , i1  => rst
           , nq  => o_next(7)
           , vdd => vdd
           , vss => vss
           );

  subckt_18_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(9)
           , i1  => sub_o(9)
           , nq  => abc_828_new_n69
           , vdd => vdd
           , vss => vss
           );

  subckt_13_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n63
           , i1  => rst
           , nq  => o_next(6)
           , vdd => vdd
           , vss => vss
           );

  subckt_11_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n61
           , i1  => rst
           , nq  => o_next(5)
           , vdd => vdd
           , vss => vss
           );

  subckt_3_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n53
           , i1  => rst
           , nq  => o_next(1)
           , vdd => vdd
           , vss => vss
           );

  subckt_5_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n55
           , i1  => rst
           , nq  => o_next(2)
           , vdd => vdd
           , vss => vss
           );

  subckt_7_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n57
           , i1  => rst
           , nq  => o_next(3)
           , vdd => vdd
           , vss => vss
           );

  subckt_26_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(13)
           , i1  => sub_o(13)
           , nq  => abc_828_new_n77
           , vdd => vdd
           , vss => vss
           );

  subckt_34_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(2)
           , q   => o(2)
           , vdd => vdd
           , vss => vss
           );

  subckt_47_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(15)
           , q   => o(15)
           , vdd => vdd
           , vss => vss
           );

  subckt_42_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(10)
           , q   => o(10)
           , vdd => vdd
           , vss => vss
           );

  subckt_20_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(10)
           , i1  => sub_o(10)
           , nq  => abc_828_new_n71
           , vdd => vdd
           , vss => vss
           );

  subckt_19_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n69
           , i1  => rst
           , nq  => o_next(9)
           , vdd => vdd
           , vss => vss
           );

  subckt_17_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n67
           , i1  => rst
           , nq  => o_next(8)
           , vdd => vdd
           , vss => vss
           );

  subckt_12_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(6)
           , i1  => sub_o(6)
           , nq  => abc_828_new_n63
           , vdd => vdd
           , vss => vss
           );

  subckt_9_no2_x1 : no2_x1
  port map ( i0  => abc_828_new_n59
           , i1  => rst
           , nq  => o_next(4)
           , vdd => vdd
           , vss => vss
           );

  subckt_39_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(7)
           , q   => o(7)
           , vdd => vdd
           , vss => vss
           );

  subckt_41_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(9)
           , q   => o(9)
           , vdd => vdd
           , vss => vss
           );

  subckt_2_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(1)
           , i1  => sub_o(1)
           , nq  => abc_828_new_n53
           , vdd => vdd
           , vss => vss
           );

  subckt_8_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(4)
           , i1  => sub_o(4)
           , nq  => abc_828_new_n59
           , vdd => vdd
           , vss => vss
           );

  subckt_33_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(1)
           , q   => o(1)
           , vdd => vdd
           , vss => vss
           );

  subckt_38_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(6)
           , q   => o(6)
           , vdd => vdd
           , vss => vss
           );

  subckt_32_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(0)
           , q   => o(0)
           , vdd => vdd
           , vss => vss
           );

  subckt_24_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(12)
           , i1  => sub_o(12)
           , nq  => abc_828_new_n75
           , vdd => vdd
           , vss => vss
           );

  subckt_16_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(8)
           , i1  => sub_o(8)
           , nq  => abc_828_new_n67
           , vdd => vdd
           , vss => vss
           );

  subckt_46_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(14)
           , q   => o(14)
           , vdd => vdd
           , vss => vss
           );

  subckt_40_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(8)
           , q   => o(8)
           , vdd => vdd
           , vss => vss
           );

  subckt_37_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(5)
           , q   => o(5)
           , vdd => vdd
           , vss => vss
           );

  subckt_10_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(5)
           , i1  => sub_o(5)
           , nq  => abc_828_new_n61
           , vdd => vdd
           , vss => vss
           );

  subckt_6_nmx2_x1 : nmx2_x1
  port map ( cmd => op
           , i0  => add_o(3)
           , i1  => sub_o(3)
           , nq  => abc_828_new_n57
           , vdd => vdd
           , vss => vss
           );

  subckt_45_sff1_x4 : sff1_x4
  port map ( ck  => clk
           , i   => o_next(13)
           , q   => o(13)
           , vdd => vdd
           , vss => vss
           );

end structural;