1 attribute \generator "nMigen"
2 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu0.war_l"
4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5 wire width 8 input 0 \s
6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7 wire width 8 input 1 \r
8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
9 wire width 8 output 2 \qn
10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
11 wire width 1 input 3 \rst
12 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
13 wire width 1 input 4 \clk
14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
17 wire width 8 \q_int$next
18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
22 parameter \A_SIGNED 1'0
23 parameter \A_WIDTH 4'1000
24 parameter \Y_WIDTH 4'1000
28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
32 parameter \A_SIGNED 1'0
33 parameter \A_WIDTH 4'1000
34 parameter \B_SIGNED 1'0
35 parameter \B_WIDTH 4'1000
36 parameter \Y_WIDTH 4'1000
41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
45 parameter \A_SIGNED 1'0
46 parameter \A_WIDTH 4'1000
47 parameter \B_SIGNED 1'0
48 parameter \B_WIDTH 4'1000
49 parameter \Y_WIDTH 4'1000
55 assign \q_int$next \q_int
57 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
60 assign \q_int$next 8'00000000
63 update \q_int 8'00000000
65 update \q_int \q_int$next
67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
73 parameter \A_SIGNED 1'0
74 parameter \A_WIDTH 4'1000
75 parameter \Y_WIDTH 4'1000
79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
83 parameter \A_SIGNED 1'0
84 parameter \A_WIDTH 4'1000
85 parameter \B_SIGNED 1'0
86 parameter \B_WIDTH 4'1000
87 parameter \Y_WIDTH 4'1000
92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
96 parameter \A_SIGNED 1'0
97 parameter \A_WIDTH 4'1000
98 parameter \B_SIGNED 1'0
99 parameter \B_WIDTH 4'1000
100 parameter \Y_WIDTH 4'1000
110 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
114 parameter \A_SIGNED 1'0
115 parameter \A_WIDTH 4'1000
116 parameter \Y_WIDTH 4'1000
121 assign \qn 8'00000000
125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
131 parameter \A_SIGNED 1'0
132 parameter \A_WIDTH 4'1000
133 parameter \B_SIGNED 1'0
134 parameter \B_WIDTH 4'1000
135 parameter \Y_WIDTH 4'1000
141 assign \qlq 8'00000000
146 attribute \generator "nMigen"
147 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu0.raw_l"
149 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
150 wire width 8 input 0 \s
151 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
152 wire width 8 input 1 \r
153 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
154 wire width 8 output 2 \qn
155 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
156 wire width 1 input 3 \rst
157 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
158 wire width 1 input 4 \clk
159 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
161 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
162 wire width 8 \q_int$next
163 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
165 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
167 parameter \A_SIGNED 1'0
168 parameter \A_WIDTH 4'1000
169 parameter \Y_WIDTH 4'1000
173 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
177 parameter \A_SIGNED 1'0
178 parameter \A_WIDTH 4'1000
179 parameter \B_SIGNED 1'0
180 parameter \B_WIDTH 4'1000
181 parameter \Y_WIDTH 4'1000
186 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
188 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
190 parameter \A_SIGNED 1'0
191 parameter \A_WIDTH 4'1000
192 parameter \B_SIGNED 1'0
193 parameter \B_WIDTH 4'1000
194 parameter \Y_WIDTH 4'1000
200 assign \q_int$next \q_int
201 assign \q_int$next $5
202 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
205 assign \q_int$next 8'00000000
208 update \q_int 8'00000000
210 update \q_int \q_int$next
212 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
214 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
216 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
218 parameter \A_SIGNED 1'0
219 parameter \A_WIDTH 4'1000
220 parameter \Y_WIDTH 4'1000
224 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
226 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
228 parameter \A_SIGNED 1'0
229 parameter \A_WIDTH 4'1000
230 parameter \B_SIGNED 1'0
231 parameter \B_WIDTH 4'1000
232 parameter \Y_WIDTH 4'1000
237 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
239 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
241 parameter \A_SIGNED 1'0
242 parameter \A_WIDTH 4'1000
243 parameter \B_SIGNED 1'0
244 parameter \B_WIDTH 4'1000
245 parameter \Y_WIDTH 4'1000
255 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
257 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
259 parameter \A_SIGNED 1'0
260 parameter \A_WIDTH 4'1000
261 parameter \Y_WIDTH 4'1000
266 assign \qn 8'00000000
270 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
272 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
274 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
276 parameter \A_SIGNED 1'0
277 parameter \A_WIDTH 4'1000
278 parameter \B_SIGNED 1'0
279 parameter \B_WIDTH 4'1000
280 parameter \Y_WIDTH 4'1000
286 assign \qlq 8'00000000
291 attribute \generator "nMigen"
292 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu0"
294 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
295 wire width 8 input 0 \load_hit_i
296 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
297 wire width 8 input 1 \stwd_hit_i
298 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
299 wire width 8 input 2 \load_v_i
300 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
301 wire width 8 input 3 \stor_v_i
302 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
303 wire width 1 input 4 \issue_i
304 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
305 wire width 1 input 5 \go_die_i
306 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
307 wire width 1 output 6 \ld_hold_st_o
308 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
309 wire width 1 output 7 \st_hold_ld_o
310 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
311 wire width 1 input 8 \load_h_i
312 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
313 wire width 1 input 9 \stor_h_i
314 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
315 wire width 1 input 10 \rst
316 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
317 wire width 1 input 11 \clk
318 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
319 wire width 8 \war_l_s
320 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
321 wire width 8 \war_l_r
322 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
323 wire width 8 \war_l_qn
327 connect \qn \war_l_qn
331 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
332 wire width 8 \raw_l_s
333 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
334 wire width 8 \raw_l_r
335 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
336 wire width 8 \raw_l_qn
340 connect \qn \raw_l_qn
344 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
346 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
348 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
350 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
352 parameter \A_SIGNED 1'0
353 parameter \A_WIDTH 4'1000
354 parameter \B_SIGNED 1'0
355 parameter \B_WIDTH 1'1
356 parameter \Y_WIDTH 4'1000
357 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
367 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
369 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
371 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
373 parameter \A_SIGNED 1'0
374 parameter \A_WIDTH 4'1000
375 parameter \B_SIGNED 1'0
376 parameter \B_WIDTH 4'1000
377 parameter \Y_WIDTH 4'1000
378 connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
383 assign \i_s_l 8'00000000
387 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
389 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
391 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
395 parameter \A_SIGNED 1'0
396 parameter \A_WIDTH 4'1000
397 parameter \B_SIGNED 1'0
398 parameter \B_WIDTH 1'1
399 parameter \Y_WIDTH 4'1000
400 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
410 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
416 parameter \A_SIGNED 1'0
417 parameter \A_WIDTH 4'1000
418 parameter \B_SIGNED 1'0
419 parameter \B_WIDTH 4'1000
420 parameter \Y_WIDTH 4'1000
421 connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
426 assign \i_l_s 8'00000000
431 assign \war_l_s 8'00000000
432 assign \war_l_s \i_s_l
435 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
437 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
439 parameter \A_SIGNED 1'0
440 parameter \A_WIDTH 4'1000
441 parameter \Y_WIDTH 4'1000
445 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
447 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
449 parameter \A_SIGNED 1'0
450 parameter \A_WIDTH 4'1000
451 parameter \B_SIGNED 1'0
452 parameter \B_WIDTH 4'1000
453 parameter \Y_WIDTH 4'1000
454 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
459 assign \war_l_r 8'11111111
464 assign \raw_l_s 8'00000000
465 assign \raw_l_s \i_s_l
468 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
470 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
472 parameter \A_SIGNED 1'0
473 parameter \A_WIDTH 4'1000
474 parameter \Y_WIDTH 4'1000
478 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
480 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
482 parameter \A_SIGNED 1'0
483 parameter \A_WIDTH 4'1000
484 parameter \B_SIGNED 1'0
485 parameter \B_WIDTH 4'1000
486 parameter \Y_WIDTH 4'1000
487 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
492 assign \raw_l_r 8'11111111
496 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
498 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
500 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
502 parameter \A_SIGNED 1'0
503 parameter \A_WIDTH 4'1000
504 parameter \B_SIGNED 1'0
505 parameter \B_WIDTH 4'1000
506 parameter \Y_WIDTH 4'1000
508 connect \B \load_hit_i
511 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
512 cell $reduce_bool $22
513 parameter \A_SIGNED 1'0
514 parameter \A_WIDTH 4'1000
515 parameter \Y_WIDTH 1'1
520 assign \ld_hold_st_o 1'0
521 assign \ld_hold_st_o $19
524 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
526 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
528 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
530 parameter \A_SIGNED 1'0
531 parameter \A_WIDTH 4'1000
532 parameter \B_SIGNED 1'0
533 parameter \B_WIDTH 4'1000
534 parameter \Y_WIDTH 4'1000
536 connect \B \stwd_hit_i
539 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
540 cell $reduce_bool $26
541 parameter \A_SIGNED 1'0
542 parameter \A_WIDTH 4'1000
543 parameter \Y_WIDTH 1'1
548 assign \st_hold_ld_o 1'0
549 assign \st_hold_ld_o $23
553 attribute \generator "nMigen"
554 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu1.war_l"
556 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
557 wire width 1 input 0 \rst
558 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
559 wire width 1 input 1 \clk
560 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
561 wire width 8 input 2 \s
562 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
563 wire width 8 input 3 \r
564 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
565 wire width 8 output 4 \qn
566 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
568 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
569 wire width 8 \q_int$next
570 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
572 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
574 parameter \A_SIGNED 1'0
575 parameter \A_WIDTH 4'1000
576 parameter \Y_WIDTH 4'1000
580 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
582 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
584 parameter \A_SIGNED 1'0
585 parameter \A_WIDTH 4'1000
586 parameter \B_SIGNED 1'0
587 parameter \B_WIDTH 4'1000
588 parameter \Y_WIDTH 4'1000
593 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
595 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
597 parameter \A_SIGNED 1'0
598 parameter \A_WIDTH 4'1000
599 parameter \B_SIGNED 1'0
600 parameter \B_WIDTH 4'1000
601 parameter \Y_WIDTH 4'1000
607 assign \q_int$next \q_int
608 assign \q_int$next $5
609 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
612 assign \q_int$next 8'00000000
615 update \q_int 8'00000000
617 update \q_int \q_int$next
619 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
621 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
623 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
625 parameter \A_SIGNED 1'0
626 parameter \A_WIDTH 4'1000
627 parameter \Y_WIDTH 4'1000
631 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
633 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
635 parameter \A_SIGNED 1'0
636 parameter \A_WIDTH 4'1000
637 parameter \B_SIGNED 1'0
638 parameter \B_WIDTH 4'1000
639 parameter \Y_WIDTH 4'1000
644 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
646 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
648 parameter \A_SIGNED 1'0
649 parameter \A_WIDTH 4'1000
650 parameter \B_SIGNED 1'0
651 parameter \B_WIDTH 4'1000
652 parameter \Y_WIDTH 4'1000
662 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
664 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
666 parameter \A_SIGNED 1'0
667 parameter \A_WIDTH 4'1000
668 parameter \Y_WIDTH 4'1000
673 assign \qn 8'00000000
677 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
679 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
681 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
683 parameter \A_SIGNED 1'0
684 parameter \A_WIDTH 4'1000
685 parameter \B_SIGNED 1'0
686 parameter \B_WIDTH 4'1000
687 parameter \Y_WIDTH 4'1000
693 assign \qlq 8'00000000
698 attribute \generator "nMigen"
699 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu1.raw_l"
701 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
702 wire width 1 input 0 \rst
703 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
704 wire width 1 input 1 \clk
705 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
706 wire width 8 input 2 \s
707 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
708 wire width 8 input 3 \r
709 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
710 wire width 8 output 4 \qn
711 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
713 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
714 wire width 8 \q_int$next
715 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
717 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
719 parameter \A_SIGNED 1'0
720 parameter \A_WIDTH 4'1000
721 parameter \Y_WIDTH 4'1000
725 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
727 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
729 parameter \A_SIGNED 1'0
730 parameter \A_WIDTH 4'1000
731 parameter \B_SIGNED 1'0
732 parameter \B_WIDTH 4'1000
733 parameter \Y_WIDTH 4'1000
738 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
740 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
742 parameter \A_SIGNED 1'0
743 parameter \A_WIDTH 4'1000
744 parameter \B_SIGNED 1'0
745 parameter \B_WIDTH 4'1000
746 parameter \Y_WIDTH 4'1000
752 assign \q_int$next \q_int
753 assign \q_int$next $5
754 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
757 assign \q_int$next 8'00000000
760 update \q_int 8'00000000
762 update \q_int \q_int$next
764 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
766 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
768 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
770 parameter \A_SIGNED 1'0
771 parameter \A_WIDTH 4'1000
772 parameter \Y_WIDTH 4'1000
776 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
778 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
780 parameter \A_SIGNED 1'0
781 parameter \A_WIDTH 4'1000
782 parameter \B_SIGNED 1'0
783 parameter \B_WIDTH 4'1000
784 parameter \Y_WIDTH 4'1000
789 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
791 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
793 parameter \A_SIGNED 1'0
794 parameter \A_WIDTH 4'1000
795 parameter \B_SIGNED 1'0
796 parameter \B_WIDTH 4'1000
797 parameter \Y_WIDTH 4'1000
807 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
809 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
811 parameter \A_SIGNED 1'0
812 parameter \A_WIDTH 4'1000
813 parameter \Y_WIDTH 4'1000
818 assign \qn 8'00000000
822 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
824 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
826 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
828 parameter \A_SIGNED 1'0
829 parameter \A_WIDTH 4'1000
830 parameter \B_SIGNED 1'0
831 parameter \B_WIDTH 4'1000
832 parameter \Y_WIDTH 4'1000
838 assign \qlq 8'00000000
843 attribute \generator "nMigen"
844 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu1"
846 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
847 wire width 8 input 0 \load_hit_i
848 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
849 wire width 8 input 1 \stwd_hit_i
850 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
851 wire width 8 input 2 \load_v_i
852 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
853 wire width 8 input 3 \stor_v_i
854 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
855 wire width 1 input 4 \issue_i
856 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
857 wire width 1 input 5 \go_die_i
858 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
859 wire width 1 output 6 \ld_hold_st_o
860 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
861 wire width 1 output 7 \st_hold_ld_o
862 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
863 wire width 1 input 8 \load_h_i
864 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
865 wire width 1 input 9 \stor_h_i
866 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
867 wire width 1 input 10 \rst
868 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
869 wire width 1 input 11 \clk
870 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
871 wire width 8 \war_l_s
872 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
873 wire width 8 \war_l_r
874 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
875 wire width 8 \war_l_qn
881 connect \qn \war_l_qn
883 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
884 wire width 8 \raw_l_s
885 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
886 wire width 8 \raw_l_r
887 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
888 wire width 8 \raw_l_qn
894 connect \qn \raw_l_qn
896 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
898 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
900 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
902 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
904 parameter \A_SIGNED 1'0
905 parameter \A_WIDTH 4'1000
906 parameter \B_SIGNED 1'0
907 parameter \B_WIDTH 1'1
908 parameter \Y_WIDTH 4'1000
909 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
919 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
921 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
923 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
925 parameter \A_SIGNED 1'0
926 parameter \A_WIDTH 4'1000
927 parameter \B_SIGNED 1'0
928 parameter \B_WIDTH 4'1000
929 parameter \Y_WIDTH 4'1000
930 connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
935 assign \i_s_l 8'00000000
939 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
941 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
943 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
945 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
947 parameter \A_SIGNED 1'0
948 parameter \A_WIDTH 4'1000
949 parameter \B_SIGNED 1'0
950 parameter \B_WIDTH 1'1
951 parameter \Y_WIDTH 4'1000
952 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
962 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
964 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
966 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
968 parameter \A_SIGNED 1'0
969 parameter \A_WIDTH 4'1000
970 parameter \B_SIGNED 1'0
971 parameter \B_WIDTH 4'1000
972 parameter \Y_WIDTH 4'1000
973 connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
978 assign \i_l_s 8'00000000
983 assign \war_l_s 8'00000000
984 assign \war_l_s \i_s_l
987 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
989 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
991 parameter \A_SIGNED 1'0
992 parameter \A_WIDTH 4'1000
993 parameter \Y_WIDTH 4'1000
997 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
999 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1001 parameter \A_SIGNED 1'0
1002 parameter \A_WIDTH 4'1000
1003 parameter \B_SIGNED 1'0
1004 parameter \B_WIDTH 4'1000
1005 parameter \Y_WIDTH 4'1000
1006 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
1011 assign \war_l_r 8'11111111
1016 assign \raw_l_s 8'00000000
1017 assign \raw_l_s \i_s_l
1020 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1022 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1024 parameter \A_SIGNED 1'0
1025 parameter \A_WIDTH 4'1000
1026 parameter \Y_WIDTH 4'1000
1027 connect \A \stor_v_i
1030 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1032 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1034 parameter \A_SIGNED 1'0
1035 parameter \A_WIDTH 4'1000
1036 parameter \B_SIGNED 1'0
1037 parameter \B_WIDTH 4'1000
1038 parameter \Y_WIDTH 4'1000
1039 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
1044 assign \raw_l_r 8'11111111
1048 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1050 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1052 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1054 parameter \A_SIGNED 1'0
1055 parameter \A_WIDTH 4'1000
1056 parameter \B_SIGNED 1'0
1057 parameter \B_WIDTH 4'1000
1058 parameter \Y_WIDTH 4'1000
1059 connect \A \war_l_qn
1060 connect \B \load_hit_i
1063 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1064 cell $reduce_bool $22
1065 parameter \A_SIGNED 1'0
1066 parameter \A_WIDTH 4'1000
1067 parameter \Y_WIDTH 1'1
1072 assign \ld_hold_st_o 1'0
1073 assign \ld_hold_st_o $19
1076 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1078 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1080 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1082 parameter \A_SIGNED 1'0
1083 parameter \A_WIDTH 4'1000
1084 parameter \B_SIGNED 1'0
1085 parameter \B_WIDTH 4'1000
1086 parameter \Y_WIDTH 4'1000
1087 connect \A \raw_l_qn
1088 connect \B \stwd_hit_i
1091 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1092 cell $reduce_bool $26
1093 parameter \A_SIGNED 1'0
1094 parameter \A_WIDTH 4'1000
1095 parameter \Y_WIDTH 1'1
1100 assign \st_hold_ld_o 1'0
1101 assign \st_hold_ld_o $23
1105 attribute \generator "nMigen"
1106 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu2.war_l"
1108 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1109 wire width 1 input 0 \rst
1110 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1111 wire width 1 input 1 \clk
1112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1113 wire width 8 input 2 \s
1114 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1115 wire width 8 input 3 \r
1116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1117 wire width 8 output 4 \qn
1118 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1121 wire width 8 \q_int$next
1122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1124 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1126 parameter \A_SIGNED 1'0
1127 parameter \A_WIDTH 4'1000
1128 parameter \Y_WIDTH 4'1000
1132 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1134 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1136 parameter \A_SIGNED 1'0
1137 parameter \A_WIDTH 4'1000
1138 parameter \B_SIGNED 1'0
1139 parameter \B_WIDTH 4'1000
1140 parameter \Y_WIDTH 4'1000
1145 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1147 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1149 parameter \A_SIGNED 1'0
1150 parameter \A_WIDTH 4'1000
1151 parameter \B_SIGNED 1'0
1152 parameter \B_WIDTH 4'1000
1153 parameter \Y_WIDTH 4'1000
1159 assign \q_int$next \q_int
1160 assign \q_int$next $5
1161 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1164 assign \q_int$next 8'00000000
1167 update \q_int 8'00000000
1169 update \q_int \q_int$next
1171 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1173 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1177 parameter \A_SIGNED 1'0
1178 parameter \A_WIDTH 4'1000
1179 parameter \Y_WIDTH 4'1000
1183 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1185 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1187 parameter \A_SIGNED 1'0
1188 parameter \A_WIDTH 4'1000
1189 parameter \B_SIGNED 1'0
1190 parameter \B_WIDTH 4'1000
1191 parameter \Y_WIDTH 4'1000
1196 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1198 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1200 parameter \A_SIGNED 1'0
1201 parameter \A_WIDTH 4'1000
1202 parameter \B_SIGNED 1'0
1203 parameter \B_WIDTH 4'1000
1204 parameter \Y_WIDTH 4'1000
1210 assign \q 8'00000000
1214 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1216 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1218 parameter \A_SIGNED 1'0
1219 parameter \A_WIDTH 4'1000
1220 parameter \Y_WIDTH 4'1000
1225 assign \qn 8'00000000
1229 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1231 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1233 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1235 parameter \A_SIGNED 1'0
1236 parameter \A_WIDTH 4'1000
1237 parameter \B_SIGNED 1'0
1238 parameter \B_WIDTH 4'1000
1239 parameter \Y_WIDTH 4'1000
1245 assign \qlq 8'00000000
1250 attribute \generator "nMigen"
1251 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu2.raw_l"
1253 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1254 wire width 1 input 0 \rst
1255 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1256 wire width 1 input 1 \clk
1257 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1258 wire width 8 input 2 \s
1259 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1260 wire width 8 input 3 \r
1261 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1262 wire width 8 output 4 \qn
1263 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1265 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1266 wire width 8 \q_int$next
1267 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1269 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1271 parameter \A_SIGNED 1'0
1272 parameter \A_WIDTH 4'1000
1273 parameter \Y_WIDTH 4'1000
1277 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1279 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1281 parameter \A_SIGNED 1'0
1282 parameter \A_WIDTH 4'1000
1283 parameter \B_SIGNED 1'0
1284 parameter \B_WIDTH 4'1000
1285 parameter \Y_WIDTH 4'1000
1290 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1292 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1294 parameter \A_SIGNED 1'0
1295 parameter \A_WIDTH 4'1000
1296 parameter \B_SIGNED 1'0
1297 parameter \B_WIDTH 4'1000
1298 parameter \Y_WIDTH 4'1000
1304 assign \q_int$next \q_int
1305 assign \q_int$next $5
1306 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1309 assign \q_int$next 8'00000000
1312 update \q_int 8'00000000
1314 update \q_int \q_int$next
1316 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1318 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1320 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1322 parameter \A_SIGNED 1'0
1323 parameter \A_WIDTH 4'1000
1324 parameter \Y_WIDTH 4'1000
1328 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1330 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1332 parameter \A_SIGNED 1'0
1333 parameter \A_WIDTH 4'1000
1334 parameter \B_SIGNED 1'0
1335 parameter \B_WIDTH 4'1000
1336 parameter \Y_WIDTH 4'1000
1341 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1343 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1345 parameter \A_SIGNED 1'0
1346 parameter \A_WIDTH 4'1000
1347 parameter \B_SIGNED 1'0
1348 parameter \B_WIDTH 4'1000
1349 parameter \Y_WIDTH 4'1000
1355 assign \q 8'00000000
1359 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1361 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1363 parameter \A_SIGNED 1'0
1364 parameter \A_WIDTH 4'1000
1365 parameter \Y_WIDTH 4'1000
1370 assign \qn 8'00000000
1374 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1376 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1378 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1380 parameter \A_SIGNED 1'0
1381 parameter \A_WIDTH 4'1000
1382 parameter \B_SIGNED 1'0
1383 parameter \B_WIDTH 4'1000
1384 parameter \Y_WIDTH 4'1000
1390 assign \qlq 8'00000000
1395 attribute \generator "nMigen"
1396 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu2"
1398 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
1399 wire width 8 input 0 \load_hit_i
1400 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
1401 wire width 8 input 1 \stwd_hit_i
1402 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
1403 wire width 8 input 2 \load_v_i
1404 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
1405 wire width 8 input 3 \stor_v_i
1406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
1407 wire width 1 input 4 \issue_i
1408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
1409 wire width 1 input 5 \go_die_i
1410 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
1411 wire width 1 output 6 \ld_hold_st_o
1412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
1413 wire width 1 output 7 \st_hold_ld_o
1414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
1415 wire width 1 input 8 \load_h_i
1416 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
1417 wire width 1 input 9 \stor_h_i
1418 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1419 wire width 1 input 10 \rst
1420 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1421 wire width 1 input 11 \clk
1422 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1423 wire width 8 \war_l_s
1424 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1425 wire width 8 \war_l_r
1426 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1427 wire width 8 \war_l_qn
1428 cell \war_l$3 \war_l
1433 connect \qn \war_l_qn
1435 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1436 wire width 8 \raw_l_s
1437 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1438 wire width 8 \raw_l_r
1439 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1440 wire width 8 \raw_l_qn
1441 cell \raw_l$4 \raw_l
1446 connect \qn \raw_l_qn
1448 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
1450 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
1452 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
1454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
1456 parameter \A_SIGNED 1'0
1457 parameter \A_WIDTH 4'1000
1458 parameter \B_SIGNED 1'0
1459 parameter \B_WIDTH 1'1
1460 parameter \Y_WIDTH 4'1000
1461 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
1462 connect \B \stor_h_i
1471 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
1473 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
1475 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
1477 parameter \A_SIGNED 1'0
1478 parameter \A_WIDTH 4'1000
1479 parameter \B_SIGNED 1'0
1480 parameter \B_WIDTH 4'1000
1481 parameter \Y_WIDTH 4'1000
1482 connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
1483 connect \B \load_v_i
1487 assign \i_s_l 8'00000000
1491 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
1493 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
1495 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
1497 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
1499 parameter \A_SIGNED 1'0
1500 parameter \A_WIDTH 4'1000
1501 parameter \B_SIGNED 1'0
1502 parameter \B_WIDTH 1'1
1503 parameter \Y_WIDTH 4'1000
1504 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
1505 connect \B \load_h_i
1514 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
1516 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
1518 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
1520 parameter \A_SIGNED 1'0
1521 parameter \A_WIDTH 4'1000
1522 parameter \B_SIGNED 1'0
1523 parameter \B_WIDTH 4'1000
1524 parameter \Y_WIDTH 4'1000
1525 connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
1526 connect \B \stor_v_i
1530 assign \i_l_s 8'00000000
1535 assign \war_l_s 8'00000000
1536 assign \war_l_s \i_s_l
1539 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1541 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1543 parameter \A_SIGNED 1'0
1544 parameter \A_WIDTH 4'1000
1545 parameter \Y_WIDTH 4'1000
1546 connect \A \load_v_i
1549 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1551 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
1553 parameter \A_SIGNED 1'0
1554 parameter \A_WIDTH 4'1000
1555 parameter \B_SIGNED 1'0
1556 parameter \B_WIDTH 4'1000
1557 parameter \Y_WIDTH 4'1000
1558 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
1563 assign \war_l_r 8'11111111
1568 assign \raw_l_s 8'00000000
1569 assign \raw_l_s \i_s_l
1572 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1574 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1576 parameter \A_SIGNED 1'0
1577 parameter \A_WIDTH 4'1000
1578 parameter \Y_WIDTH 4'1000
1579 connect \A \stor_v_i
1582 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1584 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
1586 parameter \A_SIGNED 1'0
1587 parameter \A_WIDTH 4'1000
1588 parameter \B_SIGNED 1'0
1589 parameter \B_WIDTH 4'1000
1590 parameter \Y_WIDTH 4'1000
1591 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
1596 assign \raw_l_r 8'11111111
1600 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1602 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1604 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1606 parameter \A_SIGNED 1'0
1607 parameter \A_WIDTH 4'1000
1608 parameter \B_SIGNED 1'0
1609 parameter \B_WIDTH 4'1000
1610 parameter \Y_WIDTH 4'1000
1611 connect \A \war_l_qn
1612 connect \B \load_hit_i
1615 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
1616 cell $reduce_bool $22
1617 parameter \A_SIGNED 1'0
1618 parameter \A_WIDTH 4'1000
1619 parameter \Y_WIDTH 1'1
1624 assign \ld_hold_st_o 1'0
1625 assign \ld_hold_st_o $19
1628 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1630 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1632 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1634 parameter \A_SIGNED 1'0
1635 parameter \A_WIDTH 4'1000
1636 parameter \B_SIGNED 1'0
1637 parameter \B_WIDTH 4'1000
1638 parameter \Y_WIDTH 4'1000
1639 connect \A \raw_l_qn
1640 connect \B \stwd_hit_i
1643 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
1644 cell $reduce_bool $26
1645 parameter \A_SIGNED 1'0
1646 parameter \A_WIDTH 4'1000
1647 parameter \Y_WIDTH 1'1
1652 assign \st_hold_ld_o 1'0
1653 assign \st_hold_ld_o $23
1657 attribute \generator "nMigen"
1658 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu3.war_l"
1660 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1661 wire width 1 input 0 \rst
1662 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1663 wire width 1 input 1 \clk
1664 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1665 wire width 8 input 2 \s
1666 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1667 wire width 8 input 3 \r
1668 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1669 wire width 8 output 4 \qn
1670 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1672 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1673 wire width 8 \q_int$next
1674 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1676 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1678 parameter \A_SIGNED 1'0
1679 parameter \A_WIDTH 4'1000
1680 parameter \Y_WIDTH 4'1000
1684 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1686 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1688 parameter \A_SIGNED 1'0
1689 parameter \A_WIDTH 4'1000
1690 parameter \B_SIGNED 1'0
1691 parameter \B_WIDTH 4'1000
1692 parameter \Y_WIDTH 4'1000
1697 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1699 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1701 parameter \A_SIGNED 1'0
1702 parameter \A_WIDTH 4'1000
1703 parameter \B_SIGNED 1'0
1704 parameter \B_WIDTH 4'1000
1705 parameter \Y_WIDTH 4'1000
1711 assign \q_int$next \q_int
1712 assign \q_int$next $5
1713 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1716 assign \q_int$next 8'00000000
1719 update \q_int 8'00000000
1721 update \q_int \q_int$next
1723 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1725 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1727 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1729 parameter \A_SIGNED 1'0
1730 parameter \A_WIDTH 4'1000
1731 parameter \Y_WIDTH 4'1000
1735 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1737 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1739 parameter \A_SIGNED 1'0
1740 parameter \A_WIDTH 4'1000
1741 parameter \B_SIGNED 1'0
1742 parameter \B_WIDTH 4'1000
1743 parameter \Y_WIDTH 4'1000
1748 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1750 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1752 parameter \A_SIGNED 1'0
1753 parameter \A_WIDTH 4'1000
1754 parameter \B_SIGNED 1'0
1755 parameter \B_WIDTH 4'1000
1756 parameter \Y_WIDTH 4'1000
1762 assign \q 8'00000000
1766 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1768 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1770 parameter \A_SIGNED 1'0
1771 parameter \A_WIDTH 4'1000
1772 parameter \Y_WIDTH 4'1000
1777 assign \qn 8'00000000
1781 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1783 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1785 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1787 parameter \A_SIGNED 1'0
1788 parameter \A_WIDTH 4'1000
1789 parameter \B_SIGNED 1'0
1790 parameter \B_WIDTH 4'1000
1791 parameter \Y_WIDTH 4'1000
1797 assign \qlq 8'00000000
1802 attribute \generator "nMigen"
1803 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu3.raw_l"
1805 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1806 wire width 1 input 0 \rst
1807 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1808 wire width 1 input 1 \clk
1809 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1810 wire width 8 input 2 \s
1811 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1812 wire width 8 input 3 \r
1813 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1814 wire width 8 output 4 \qn
1815 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1817 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
1818 wire width 8 \q_int$next
1819 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1821 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1823 parameter \A_SIGNED 1'0
1824 parameter \A_WIDTH 4'1000
1825 parameter \Y_WIDTH 4'1000
1829 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1831 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1833 parameter \A_SIGNED 1'0
1834 parameter \A_WIDTH 4'1000
1835 parameter \B_SIGNED 1'0
1836 parameter \B_WIDTH 4'1000
1837 parameter \Y_WIDTH 4'1000
1842 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1844 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
1846 parameter \A_SIGNED 1'0
1847 parameter \A_WIDTH 4'1000
1848 parameter \B_SIGNED 1'0
1849 parameter \B_WIDTH 4'1000
1850 parameter \Y_WIDTH 4'1000
1856 assign \q_int$next \q_int
1857 assign \q_int$next $5
1858 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
1861 assign \q_int$next 8'00000000
1864 update \q_int 8'00000000
1866 update \q_int \q_int$next
1868 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
1870 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1872 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1874 parameter \A_SIGNED 1'0
1875 parameter \A_WIDTH 4'1000
1876 parameter \Y_WIDTH 4'1000
1880 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1882 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1884 parameter \A_SIGNED 1'0
1885 parameter \A_WIDTH 4'1000
1886 parameter \B_SIGNED 1'0
1887 parameter \B_WIDTH 4'1000
1888 parameter \Y_WIDTH 4'1000
1893 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1895 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
1897 parameter \A_SIGNED 1'0
1898 parameter \A_WIDTH 4'1000
1899 parameter \B_SIGNED 1'0
1900 parameter \B_WIDTH 4'1000
1901 parameter \Y_WIDTH 4'1000
1907 assign \q 8'00000000
1911 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1913 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
1915 parameter \A_SIGNED 1'0
1916 parameter \A_WIDTH 4'1000
1917 parameter \Y_WIDTH 4'1000
1922 assign \qn 8'00000000
1926 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
1928 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1930 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
1932 parameter \A_SIGNED 1'0
1933 parameter \A_WIDTH 4'1000
1934 parameter \B_SIGNED 1'0
1935 parameter \B_WIDTH 4'1000
1936 parameter \Y_WIDTH 4'1000
1942 assign \qlq 8'00000000
1947 attribute \generator "nMigen"
1948 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu3"
1950 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
1951 wire width 8 input 0 \load_hit_i
1952 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
1953 wire width 8 input 1 \stwd_hit_i
1954 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
1955 wire width 8 input 2 \load_v_i
1956 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
1957 wire width 8 input 3 \stor_v_i
1958 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
1959 wire width 1 input 4 \issue_i
1960 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
1961 wire width 1 input 5 \go_die_i
1962 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
1963 wire width 1 output 6 \ld_hold_st_o
1964 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
1965 wire width 1 output 7 \st_hold_ld_o
1966 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
1967 wire width 1 input 8 \load_h_i
1968 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
1969 wire width 1 input 9 \stor_h_i
1970 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1971 wire width 1 input 10 \rst
1972 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
1973 wire width 1 input 11 \clk
1974 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1975 wire width 8 \war_l_s
1976 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1977 wire width 8 \war_l_r
1978 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1979 wire width 8 \war_l_qn
1980 cell \war_l$5 \war_l
1985 connect \qn \war_l_qn
1987 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
1988 wire width 8 \raw_l_s
1989 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
1990 wire width 8 \raw_l_r
1991 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
1992 wire width 8 \raw_l_qn
1993 cell \raw_l$6 \raw_l
1998 connect \qn \raw_l_qn
2000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
2002 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2004 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2006 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2008 parameter \A_SIGNED 1'0
2009 parameter \A_WIDTH 4'1000
2010 parameter \B_SIGNED 1'0
2011 parameter \B_WIDTH 1'1
2012 parameter \Y_WIDTH 4'1000
2013 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
2014 connect \B \stor_h_i
2023 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
2025 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
2027 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
2029 parameter \A_SIGNED 1'0
2030 parameter \A_WIDTH 4'1000
2031 parameter \B_SIGNED 1'0
2032 parameter \B_WIDTH 4'1000
2033 parameter \Y_WIDTH 4'1000
2034 connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
2035 connect \B \load_v_i
2039 assign \i_s_l 8'00000000
2043 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
2045 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2047 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2049 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2051 parameter \A_SIGNED 1'0
2052 parameter \A_WIDTH 4'1000
2053 parameter \B_SIGNED 1'0
2054 parameter \B_WIDTH 1'1
2055 parameter \Y_WIDTH 4'1000
2056 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
2057 connect \B \load_h_i
2066 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
2068 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
2070 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
2072 parameter \A_SIGNED 1'0
2073 parameter \A_WIDTH 4'1000
2074 parameter \B_SIGNED 1'0
2075 parameter \B_WIDTH 4'1000
2076 parameter \Y_WIDTH 4'1000
2077 connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
2078 connect \B \stor_v_i
2082 assign \i_l_s 8'00000000
2087 assign \war_l_s 8'00000000
2088 assign \war_l_s \i_s_l
2091 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2093 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2095 parameter \A_SIGNED 1'0
2096 parameter \A_WIDTH 4'1000
2097 parameter \Y_WIDTH 4'1000
2098 connect \A \load_v_i
2101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2105 parameter \A_SIGNED 1'0
2106 parameter \A_WIDTH 4'1000
2107 parameter \B_SIGNED 1'0
2108 parameter \B_WIDTH 4'1000
2109 parameter \Y_WIDTH 4'1000
2110 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
2115 assign \war_l_r 8'11111111
2120 assign \raw_l_s 8'00000000
2121 assign \raw_l_s \i_s_l
2124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2128 parameter \A_SIGNED 1'0
2129 parameter \A_WIDTH 4'1000
2130 parameter \Y_WIDTH 4'1000
2131 connect \A \stor_v_i
2134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2138 parameter \A_SIGNED 1'0
2139 parameter \A_WIDTH 4'1000
2140 parameter \B_SIGNED 1'0
2141 parameter \B_WIDTH 4'1000
2142 parameter \Y_WIDTH 4'1000
2143 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
2148 assign \raw_l_r 8'11111111
2152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2158 parameter \A_SIGNED 1'0
2159 parameter \A_WIDTH 4'1000
2160 parameter \B_SIGNED 1'0
2161 parameter \B_WIDTH 4'1000
2162 parameter \Y_WIDTH 4'1000
2163 connect \A \war_l_qn
2164 connect \B \load_hit_i
2167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2168 cell $reduce_bool $22
2169 parameter \A_SIGNED 1'0
2170 parameter \A_WIDTH 4'1000
2171 parameter \Y_WIDTH 1'1
2176 assign \ld_hold_st_o 1'0
2177 assign \ld_hold_st_o $19
2180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2186 parameter \A_SIGNED 1'0
2187 parameter \A_WIDTH 4'1000
2188 parameter \B_SIGNED 1'0
2189 parameter \B_WIDTH 4'1000
2190 parameter \Y_WIDTH 4'1000
2191 connect \A \raw_l_qn
2192 connect \B \stwd_hit_i
2195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2196 cell $reduce_bool $26
2197 parameter \A_SIGNED 1'0
2198 parameter \A_WIDTH 4'1000
2199 parameter \Y_WIDTH 1'1
2204 assign \st_hold_ld_o 1'0
2205 assign \st_hold_ld_o $23
2209 attribute \generator "nMigen"
2210 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu4.war_l"
2212 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2213 wire width 1 input 0 \rst
2214 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2215 wire width 1 input 1 \clk
2216 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2217 wire width 8 input 2 \s
2218 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2219 wire width 8 input 3 \r
2220 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2221 wire width 8 output 4 \qn
2222 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2224 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2225 wire width 8 \q_int$next
2226 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2228 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2230 parameter \A_SIGNED 1'0
2231 parameter \A_WIDTH 4'1000
2232 parameter \Y_WIDTH 4'1000
2236 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2238 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2240 parameter \A_SIGNED 1'0
2241 parameter \A_WIDTH 4'1000
2242 parameter \B_SIGNED 1'0
2243 parameter \B_WIDTH 4'1000
2244 parameter \Y_WIDTH 4'1000
2249 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2251 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2253 parameter \A_SIGNED 1'0
2254 parameter \A_WIDTH 4'1000
2255 parameter \B_SIGNED 1'0
2256 parameter \B_WIDTH 4'1000
2257 parameter \Y_WIDTH 4'1000
2263 assign \q_int$next \q_int
2264 assign \q_int$next $5
2265 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2268 assign \q_int$next 8'00000000
2271 update \q_int 8'00000000
2273 update \q_int \q_int$next
2275 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2277 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2279 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2281 parameter \A_SIGNED 1'0
2282 parameter \A_WIDTH 4'1000
2283 parameter \Y_WIDTH 4'1000
2287 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2289 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2291 parameter \A_SIGNED 1'0
2292 parameter \A_WIDTH 4'1000
2293 parameter \B_SIGNED 1'0
2294 parameter \B_WIDTH 4'1000
2295 parameter \Y_WIDTH 4'1000
2300 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2302 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2304 parameter \A_SIGNED 1'0
2305 parameter \A_WIDTH 4'1000
2306 parameter \B_SIGNED 1'0
2307 parameter \B_WIDTH 4'1000
2308 parameter \Y_WIDTH 4'1000
2314 assign \q 8'00000000
2318 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2320 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2322 parameter \A_SIGNED 1'0
2323 parameter \A_WIDTH 4'1000
2324 parameter \Y_WIDTH 4'1000
2329 assign \qn 8'00000000
2333 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2335 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2337 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2339 parameter \A_SIGNED 1'0
2340 parameter \A_WIDTH 4'1000
2341 parameter \B_SIGNED 1'0
2342 parameter \B_WIDTH 4'1000
2343 parameter \Y_WIDTH 4'1000
2349 assign \qlq 8'00000000
2354 attribute \generator "nMigen"
2355 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu4.raw_l"
2357 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2358 wire width 1 input 0 \rst
2359 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2360 wire width 1 input 1 \clk
2361 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2362 wire width 8 input 2 \s
2363 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2364 wire width 8 input 3 \r
2365 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2366 wire width 8 output 4 \qn
2367 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2369 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2370 wire width 8 \q_int$next
2371 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2373 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2375 parameter \A_SIGNED 1'0
2376 parameter \A_WIDTH 4'1000
2377 parameter \Y_WIDTH 4'1000
2381 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2383 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2385 parameter \A_SIGNED 1'0
2386 parameter \A_WIDTH 4'1000
2387 parameter \B_SIGNED 1'0
2388 parameter \B_WIDTH 4'1000
2389 parameter \Y_WIDTH 4'1000
2394 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2396 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2398 parameter \A_SIGNED 1'0
2399 parameter \A_WIDTH 4'1000
2400 parameter \B_SIGNED 1'0
2401 parameter \B_WIDTH 4'1000
2402 parameter \Y_WIDTH 4'1000
2408 assign \q_int$next \q_int
2409 assign \q_int$next $5
2410 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2413 assign \q_int$next 8'00000000
2416 update \q_int 8'00000000
2418 update \q_int \q_int$next
2420 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2422 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2424 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2426 parameter \A_SIGNED 1'0
2427 parameter \A_WIDTH 4'1000
2428 parameter \Y_WIDTH 4'1000
2432 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2434 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2436 parameter \A_SIGNED 1'0
2437 parameter \A_WIDTH 4'1000
2438 parameter \B_SIGNED 1'0
2439 parameter \B_WIDTH 4'1000
2440 parameter \Y_WIDTH 4'1000
2445 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2447 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2449 parameter \A_SIGNED 1'0
2450 parameter \A_WIDTH 4'1000
2451 parameter \B_SIGNED 1'0
2452 parameter \B_WIDTH 4'1000
2453 parameter \Y_WIDTH 4'1000
2459 assign \q 8'00000000
2463 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2465 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2467 parameter \A_SIGNED 1'0
2468 parameter \A_WIDTH 4'1000
2469 parameter \Y_WIDTH 4'1000
2474 assign \qn 8'00000000
2478 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2480 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2482 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2484 parameter \A_SIGNED 1'0
2485 parameter \A_WIDTH 4'1000
2486 parameter \B_SIGNED 1'0
2487 parameter \B_WIDTH 4'1000
2488 parameter \Y_WIDTH 4'1000
2494 assign \qlq 8'00000000
2499 attribute \generator "nMigen"
2500 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu4"
2502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
2503 wire width 8 input 0 \load_hit_i
2504 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
2505 wire width 8 input 1 \stwd_hit_i
2506 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
2507 wire width 8 input 2 \load_v_i
2508 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
2509 wire width 8 input 3 \stor_v_i
2510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
2511 wire width 1 input 4 \issue_i
2512 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
2513 wire width 1 input 5 \go_die_i
2514 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
2515 wire width 1 output 6 \ld_hold_st_o
2516 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
2517 wire width 1 output 7 \st_hold_ld_o
2518 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
2519 wire width 1 input 8 \load_h_i
2520 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
2521 wire width 1 input 9 \stor_h_i
2522 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2523 wire width 1 input 10 \rst
2524 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2525 wire width 1 input 11 \clk
2526 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2527 wire width 8 \war_l_s
2528 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2529 wire width 8 \war_l_r
2530 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2531 wire width 8 \war_l_qn
2532 cell \war_l$7 \war_l
2537 connect \qn \war_l_qn
2539 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2540 wire width 8 \raw_l_s
2541 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2542 wire width 8 \raw_l_r
2543 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2544 wire width 8 \raw_l_qn
2545 cell \raw_l$8 \raw_l
2550 connect \qn \raw_l_qn
2552 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
2554 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2556 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2558 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
2560 parameter \A_SIGNED 1'0
2561 parameter \A_WIDTH 4'1000
2562 parameter \B_SIGNED 1'0
2563 parameter \B_WIDTH 1'1
2564 parameter \Y_WIDTH 4'1000
2565 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
2566 connect \B \stor_h_i
2575 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
2577 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
2579 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
2581 parameter \A_SIGNED 1'0
2582 parameter \A_WIDTH 4'1000
2583 parameter \B_SIGNED 1'0
2584 parameter \B_WIDTH 4'1000
2585 parameter \Y_WIDTH 4'1000
2586 connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
2587 connect \B \load_v_i
2591 assign \i_s_l 8'00000000
2595 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
2597 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2599 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2601 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
2603 parameter \A_SIGNED 1'0
2604 parameter \A_WIDTH 4'1000
2605 parameter \B_SIGNED 1'0
2606 parameter \B_WIDTH 1'1
2607 parameter \Y_WIDTH 4'1000
2608 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
2609 connect \B \load_h_i
2618 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
2620 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
2622 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
2624 parameter \A_SIGNED 1'0
2625 parameter \A_WIDTH 4'1000
2626 parameter \B_SIGNED 1'0
2627 parameter \B_WIDTH 4'1000
2628 parameter \Y_WIDTH 4'1000
2629 connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
2630 connect \B \stor_v_i
2634 assign \i_l_s 8'00000000
2639 assign \war_l_s 8'00000000
2640 assign \war_l_s \i_s_l
2643 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2645 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2647 parameter \A_SIGNED 1'0
2648 parameter \A_WIDTH 4'1000
2649 parameter \Y_WIDTH 4'1000
2650 connect \A \load_v_i
2653 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2655 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
2657 parameter \A_SIGNED 1'0
2658 parameter \A_WIDTH 4'1000
2659 parameter \B_SIGNED 1'0
2660 parameter \B_WIDTH 4'1000
2661 parameter \Y_WIDTH 4'1000
2662 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
2667 assign \war_l_r 8'11111111
2672 assign \raw_l_s 8'00000000
2673 assign \raw_l_s \i_s_l
2676 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2678 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2680 parameter \A_SIGNED 1'0
2681 parameter \A_WIDTH 4'1000
2682 parameter \Y_WIDTH 4'1000
2683 connect \A \stor_v_i
2686 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2688 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
2690 parameter \A_SIGNED 1'0
2691 parameter \A_WIDTH 4'1000
2692 parameter \B_SIGNED 1'0
2693 parameter \B_WIDTH 4'1000
2694 parameter \Y_WIDTH 4'1000
2695 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
2700 assign \raw_l_r 8'11111111
2704 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2706 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2708 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2710 parameter \A_SIGNED 1'0
2711 parameter \A_WIDTH 4'1000
2712 parameter \B_SIGNED 1'0
2713 parameter \B_WIDTH 4'1000
2714 parameter \Y_WIDTH 4'1000
2715 connect \A \war_l_qn
2716 connect \B \load_hit_i
2719 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
2720 cell $reduce_bool $22
2721 parameter \A_SIGNED 1'0
2722 parameter \A_WIDTH 4'1000
2723 parameter \Y_WIDTH 1'1
2728 assign \ld_hold_st_o 1'0
2729 assign \ld_hold_st_o $19
2732 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2734 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2736 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2738 parameter \A_SIGNED 1'0
2739 parameter \A_WIDTH 4'1000
2740 parameter \B_SIGNED 1'0
2741 parameter \B_WIDTH 4'1000
2742 parameter \Y_WIDTH 4'1000
2743 connect \A \raw_l_qn
2744 connect \B \stwd_hit_i
2747 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
2748 cell $reduce_bool $26
2749 parameter \A_SIGNED 1'0
2750 parameter \A_WIDTH 4'1000
2751 parameter \Y_WIDTH 1'1
2756 assign \st_hold_ld_o 1'0
2757 assign \st_hold_ld_o $23
2761 attribute \generator "nMigen"
2762 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu5.war_l"
2764 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2765 wire width 1 input 0 \rst
2766 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2767 wire width 1 input 1 \clk
2768 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2769 wire width 8 input 2 \s
2770 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2771 wire width 8 input 3 \r
2772 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2773 wire width 8 output 4 \qn
2774 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2776 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2777 wire width 8 \q_int$next
2778 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2780 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2782 parameter \A_SIGNED 1'0
2783 parameter \A_WIDTH 4'1000
2784 parameter \Y_WIDTH 4'1000
2788 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2790 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2792 parameter \A_SIGNED 1'0
2793 parameter \A_WIDTH 4'1000
2794 parameter \B_SIGNED 1'0
2795 parameter \B_WIDTH 4'1000
2796 parameter \Y_WIDTH 4'1000
2801 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2803 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2805 parameter \A_SIGNED 1'0
2806 parameter \A_WIDTH 4'1000
2807 parameter \B_SIGNED 1'0
2808 parameter \B_WIDTH 4'1000
2809 parameter \Y_WIDTH 4'1000
2815 assign \q_int$next \q_int
2816 assign \q_int$next $5
2817 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2820 assign \q_int$next 8'00000000
2823 update \q_int 8'00000000
2825 update \q_int \q_int$next
2827 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2829 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2831 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2833 parameter \A_SIGNED 1'0
2834 parameter \A_WIDTH 4'1000
2835 parameter \Y_WIDTH 4'1000
2839 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2841 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2843 parameter \A_SIGNED 1'0
2844 parameter \A_WIDTH 4'1000
2845 parameter \B_SIGNED 1'0
2846 parameter \B_WIDTH 4'1000
2847 parameter \Y_WIDTH 4'1000
2852 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2854 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2856 parameter \A_SIGNED 1'0
2857 parameter \A_WIDTH 4'1000
2858 parameter \B_SIGNED 1'0
2859 parameter \B_WIDTH 4'1000
2860 parameter \Y_WIDTH 4'1000
2866 assign \q 8'00000000
2870 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2872 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
2874 parameter \A_SIGNED 1'0
2875 parameter \A_WIDTH 4'1000
2876 parameter \Y_WIDTH 4'1000
2881 assign \qn 8'00000000
2885 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
2887 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2889 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
2891 parameter \A_SIGNED 1'0
2892 parameter \A_WIDTH 4'1000
2893 parameter \B_SIGNED 1'0
2894 parameter \B_WIDTH 4'1000
2895 parameter \Y_WIDTH 4'1000
2901 assign \qlq 8'00000000
2906 attribute \generator "nMigen"
2907 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu5.raw_l"
2909 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2910 wire width 1 input 0 \rst
2911 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
2912 wire width 1 input 1 \clk
2913 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
2914 wire width 8 input 2 \s
2915 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
2916 wire width 8 input 3 \r
2917 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
2918 wire width 8 output 4 \qn
2919 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2921 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
2922 wire width 8 \q_int$next
2923 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2925 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2927 parameter \A_SIGNED 1'0
2928 parameter \A_WIDTH 4'1000
2929 parameter \Y_WIDTH 4'1000
2933 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2935 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2937 parameter \A_SIGNED 1'0
2938 parameter \A_WIDTH 4'1000
2939 parameter \B_SIGNED 1'0
2940 parameter \B_WIDTH 4'1000
2941 parameter \Y_WIDTH 4'1000
2946 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2948 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
2950 parameter \A_SIGNED 1'0
2951 parameter \A_WIDTH 4'1000
2952 parameter \B_SIGNED 1'0
2953 parameter \B_WIDTH 4'1000
2954 parameter \Y_WIDTH 4'1000
2960 assign \q_int$next \q_int
2961 assign \q_int$next $5
2962 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
2965 assign \q_int$next 8'00000000
2968 update \q_int 8'00000000
2970 update \q_int \q_int$next
2972 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
2974 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2976 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2978 parameter \A_SIGNED 1'0
2979 parameter \A_WIDTH 4'1000
2980 parameter \Y_WIDTH 4'1000
2984 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2986 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2988 parameter \A_SIGNED 1'0
2989 parameter \A_WIDTH 4'1000
2990 parameter \B_SIGNED 1'0
2991 parameter \B_WIDTH 4'1000
2992 parameter \Y_WIDTH 4'1000
2997 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
2999 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3001 parameter \A_SIGNED 1'0
3002 parameter \A_WIDTH 4'1000
3003 parameter \B_SIGNED 1'0
3004 parameter \B_WIDTH 4'1000
3005 parameter \Y_WIDTH 4'1000
3011 assign \q 8'00000000
3015 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3017 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3019 parameter \A_SIGNED 1'0
3020 parameter \A_WIDTH 4'1000
3021 parameter \Y_WIDTH 4'1000
3026 assign \qn 8'00000000
3030 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
3032 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3034 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3036 parameter \A_SIGNED 1'0
3037 parameter \A_WIDTH 4'1000
3038 parameter \B_SIGNED 1'0
3039 parameter \B_WIDTH 4'1000
3040 parameter \Y_WIDTH 4'1000
3046 assign \qlq 8'00000000
3051 attribute \generator "nMigen"
3052 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu5"
3054 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
3055 wire width 8 input 0 \load_hit_i
3056 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
3057 wire width 8 input 1 \stwd_hit_i
3058 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
3059 wire width 8 input 2 \load_v_i
3060 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
3061 wire width 8 input 3 \stor_v_i
3062 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
3063 wire width 1 input 4 \issue_i
3064 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
3065 wire width 1 input 5 \go_die_i
3066 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
3067 wire width 1 output 6 \ld_hold_st_o
3068 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
3069 wire width 1 output 7 \st_hold_ld_o
3070 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
3071 wire width 1 input 8 \load_h_i
3072 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
3073 wire width 1 input 9 \stor_h_i
3074 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3075 wire width 1 input 10 \rst
3076 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3077 wire width 1 input 11 \clk
3078 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3079 wire width 8 \war_l_s
3080 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3081 wire width 8 \war_l_r
3082 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3083 wire width 8 \war_l_qn
3084 cell \war_l$9 \war_l
3089 connect \qn \war_l_qn
3091 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3092 wire width 8 \raw_l_s
3093 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3094 wire width 8 \raw_l_r
3095 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3096 wire width 8 \raw_l_qn
3097 cell \raw_l$10 \raw_l
3102 connect \qn \raw_l_qn
3104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
3106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3112 parameter \A_SIGNED 1'0
3113 parameter \A_WIDTH 4'1000
3114 parameter \B_SIGNED 1'0
3115 parameter \B_WIDTH 1'1
3116 parameter \Y_WIDTH 4'1000
3117 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
3118 connect \B \stor_h_i
3127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
3129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
3131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
3133 parameter \A_SIGNED 1'0
3134 parameter \A_WIDTH 4'1000
3135 parameter \B_SIGNED 1'0
3136 parameter \B_WIDTH 4'1000
3137 parameter \Y_WIDTH 4'1000
3138 connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
3139 connect \B \load_v_i
3143 assign \i_s_l 8'00000000
3147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
3149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3155 parameter \A_SIGNED 1'0
3156 parameter \A_WIDTH 4'1000
3157 parameter \B_SIGNED 1'0
3158 parameter \B_WIDTH 1'1
3159 parameter \Y_WIDTH 4'1000
3160 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
3161 connect \B \load_h_i
3170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
3172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
3174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
3176 parameter \A_SIGNED 1'0
3177 parameter \A_WIDTH 4'1000
3178 parameter \B_SIGNED 1'0
3179 parameter \B_WIDTH 4'1000
3180 parameter \Y_WIDTH 4'1000
3181 connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
3182 connect \B \stor_v_i
3186 assign \i_l_s 8'00000000
3191 assign \war_l_s 8'00000000
3192 assign \war_l_s \i_s_l
3195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3199 parameter \A_SIGNED 1'0
3200 parameter \A_WIDTH 4'1000
3201 parameter \Y_WIDTH 4'1000
3202 connect \A \load_v_i
3205 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3207 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3209 parameter \A_SIGNED 1'0
3210 parameter \A_WIDTH 4'1000
3211 parameter \B_SIGNED 1'0
3212 parameter \B_WIDTH 4'1000
3213 parameter \Y_WIDTH 4'1000
3214 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
3219 assign \war_l_r 8'11111111
3224 assign \raw_l_s 8'00000000
3225 assign \raw_l_s \i_s_l
3228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3230 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3232 parameter \A_SIGNED 1'0
3233 parameter \A_WIDTH 4'1000
3234 parameter \Y_WIDTH 4'1000
3235 connect \A \stor_v_i
3238 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3240 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3242 parameter \A_SIGNED 1'0
3243 parameter \A_WIDTH 4'1000
3244 parameter \B_SIGNED 1'0
3245 parameter \B_WIDTH 4'1000
3246 parameter \Y_WIDTH 4'1000
3247 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
3252 assign \raw_l_r 8'11111111
3256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3258 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3260 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3262 parameter \A_SIGNED 1'0
3263 parameter \A_WIDTH 4'1000
3264 parameter \B_SIGNED 1'0
3265 parameter \B_WIDTH 4'1000
3266 parameter \Y_WIDTH 4'1000
3267 connect \A \war_l_qn
3268 connect \B \load_hit_i
3271 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3272 cell $reduce_bool $22
3273 parameter \A_SIGNED 1'0
3274 parameter \A_WIDTH 4'1000
3275 parameter \Y_WIDTH 1'1
3280 assign \ld_hold_st_o 1'0
3281 assign \ld_hold_st_o $19
3284 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3286 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3288 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3290 parameter \A_SIGNED 1'0
3291 parameter \A_WIDTH 4'1000
3292 parameter \B_SIGNED 1'0
3293 parameter \B_WIDTH 4'1000
3294 parameter \Y_WIDTH 4'1000
3295 connect \A \raw_l_qn
3296 connect \B \stwd_hit_i
3299 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3300 cell $reduce_bool $26
3301 parameter \A_SIGNED 1'0
3302 parameter \A_WIDTH 4'1000
3303 parameter \Y_WIDTH 1'1
3308 assign \st_hold_ld_o 1'0
3309 assign \st_hold_ld_o $23
3313 attribute \generator "nMigen"
3314 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu6.war_l"
3316 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3317 wire width 1 input 0 \rst
3318 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3319 wire width 1 input 1 \clk
3320 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3321 wire width 8 input 2 \s
3322 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3323 wire width 8 input 3 \r
3324 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3325 wire width 8 output 4 \qn
3326 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3328 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3329 wire width 8 \q_int$next
3330 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3332 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3334 parameter \A_SIGNED 1'0
3335 parameter \A_WIDTH 4'1000
3336 parameter \Y_WIDTH 4'1000
3340 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3342 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3344 parameter \A_SIGNED 1'0
3345 parameter \A_WIDTH 4'1000
3346 parameter \B_SIGNED 1'0
3347 parameter \B_WIDTH 4'1000
3348 parameter \Y_WIDTH 4'1000
3353 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3355 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3357 parameter \A_SIGNED 1'0
3358 parameter \A_WIDTH 4'1000
3359 parameter \B_SIGNED 1'0
3360 parameter \B_WIDTH 4'1000
3361 parameter \Y_WIDTH 4'1000
3367 assign \q_int$next \q_int
3368 assign \q_int$next $5
3369 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
3372 assign \q_int$next 8'00000000
3375 update \q_int 8'00000000
3377 update \q_int \q_int$next
3379 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
3381 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3383 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3385 parameter \A_SIGNED 1'0
3386 parameter \A_WIDTH 4'1000
3387 parameter \Y_WIDTH 4'1000
3391 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3393 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3395 parameter \A_SIGNED 1'0
3396 parameter \A_WIDTH 4'1000
3397 parameter \B_SIGNED 1'0
3398 parameter \B_WIDTH 4'1000
3399 parameter \Y_WIDTH 4'1000
3404 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3406 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3408 parameter \A_SIGNED 1'0
3409 parameter \A_WIDTH 4'1000
3410 parameter \B_SIGNED 1'0
3411 parameter \B_WIDTH 4'1000
3412 parameter \Y_WIDTH 4'1000
3418 assign \q 8'00000000
3422 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3424 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3426 parameter \A_SIGNED 1'0
3427 parameter \A_WIDTH 4'1000
3428 parameter \Y_WIDTH 4'1000
3433 assign \qn 8'00000000
3437 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
3439 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3441 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3443 parameter \A_SIGNED 1'0
3444 parameter \A_WIDTH 4'1000
3445 parameter \B_SIGNED 1'0
3446 parameter \B_WIDTH 4'1000
3447 parameter \Y_WIDTH 4'1000
3453 assign \qlq 8'00000000
3458 attribute \generator "nMigen"
3459 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu6.raw_l"
3461 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3462 wire width 1 input 0 \rst
3463 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3464 wire width 1 input 1 \clk
3465 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3466 wire width 8 input 2 \s
3467 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3468 wire width 8 input 3 \r
3469 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3470 wire width 8 output 4 \qn
3471 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3473 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3474 wire width 8 \q_int$next
3475 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3477 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3479 parameter \A_SIGNED 1'0
3480 parameter \A_WIDTH 4'1000
3481 parameter \Y_WIDTH 4'1000
3485 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3487 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3489 parameter \A_SIGNED 1'0
3490 parameter \A_WIDTH 4'1000
3491 parameter \B_SIGNED 1'0
3492 parameter \B_WIDTH 4'1000
3493 parameter \Y_WIDTH 4'1000
3498 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3500 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3502 parameter \A_SIGNED 1'0
3503 parameter \A_WIDTH 4'1000
3504 parameter \B_SIGNED 1'0
3505 parameter \B_WIDTH 4'1000
3506 parameter \Y_WIDTH 4'1000
3512 assign \q_int$next \q_int
3513 assign \q_int$next $5
3514 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
3517 assign \q_int$next 8'00000000
3520 update \q_int 8'00000000
3522 update \q_int \q_int$next
3524 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
3526 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3528 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3530 parameter \A_SIGNED 1'0
3531 parameter \A_WIDTH 4'1000
3532 parameter \Y_WIDTH 4'1000
3536 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3538 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3540 parameter \A_SIGNED 1'0
3541 parameter \A_WIDTH 4'1000
3542 parameter \B_SIGNED 1'0
3543 parameter \B_WIDTH 4'1000
3544 parameter \Y_WIDTH 4'1000
3549 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3551 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3553 parameter \A_SIGNED 1'0
3554 parameter \A_WIDTH 4'1000
3555 parameter \B_SIGNED 1'0
3556 parameter \B_WIDTH 4'1000
3557 parameter \Y_WIDTH 4'1000
3563 assign \q 8'00000000
3567 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3569 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3571 parameter \A_SIGNED 1'0
3572 parameter \A_WIDTH 4'1000
3573 parameter \Y_WIDTH 4'1000
3578 assign \qn 8'00000000
3582 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
3584 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3586 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3588 parameter \A_SIGNED 1'0
3589 parameter \A_WIDTH 4'1000
3590 parameter \B_SIGNED 1'0
3591 parameter \B_WIDTH 4'1000
3592 parameter \Y_WIDTH 4'1000
3598 assign \qlq 8'00000000
3603 attribute \generator "nMigen"
3604 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu6"
3606 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
3607 wire width 8 input 0 \load_hit_i
3608 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
3609 wire width 8 input 1 \stwd_hit_i
3610 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
3611 wire width 8 input 2 \load_v_i
3612 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
3613 wire width 8 input 3 \stor_v_i
3614 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
3615 wire width 1 input 4 \issue_i
3616 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
3617 wire width 1 input 5 \go_die_i
3618 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
3619 wire width 1 output 6 \ld_hold_st_o
3620 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
3621 wire width 1 output 7 \st_hold_ld_o
3622 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
3623 wire width 1 input 8 \load_h_i
3624 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
3625 wire width 1 input 9 \stor_h_i
3626 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3627 wire width 1 input 10 \rst
3628 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3629 wire width 1 input 11 \clk
3630 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3631 wire width 8 \war_l_s
3632 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3633 wire width 8 \war_l_r
3634 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3635 wire width 8 \war_l_qn
3636 cell \war_l$11 \war_l
3641 connect \qn \war_l_qn
3643 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3644 wire width 8 \raw_l_s
3645 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3646 wire width 8 \raw_l_r
3647 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3648 wire width 8 \raw_l_qn
3649 cell \raw_l$12 \raw_l
3654 connect \qn \raw_l_qn
3656 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
3658 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3660 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3662 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
3664 parameter \A_SIGNED 1'0
3665 parameter \A_WIDTH 4'1000
3666 parameter \B_SIGNED 1'0
3667 parameter \B_WIDTH 1'1
3668 parameter \Y_WIDTH 4'1000
3669 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
3670 connect \B \stor_h_i
3679 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
3681 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
3683 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
3685 parameter \A_SIGNED 1'0
3686 parameter \A_WIDTH 4'1000
3687 parameter \B_SIGNED 1'0
3688 parameter \B_WIDTH 4'1000
3689 parameter \Y_WIDTH 4'1000
3690 connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
3691 connect \B \load_v_i
3695 assign \i_s_l 8'00000000
3699 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
3701 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3703 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3705 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
3707 parameter \A_SIGNED 1'0
3708 parameter \A_WIDTH 4'1000
3709 parameter \B_SIGNED 1'0
3710 parameter \B_WIDTH 1'1
3711 parameter \Y_WIDTH 4'1000
3712 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
3713 connect \B \load_h_i
3722 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
3724 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
3726 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
3728 parameter \A_SIGNED 1'0
3729 parameter \A_WIDTH 4'1000
3730 parameter \B_SIGNED 1'0
3731 parameter \B_WIDTH 4'1000
3732 parameter \Y_WIDTH 4'1000
3733 connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
3734 connect \B \stor_v_i
3738 assign \i_l_s 8'00000000
3743 assign \war_l_s 8'00000000
3744 assign \war_l_s \i_s_l
3747 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3749 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3751 parameter \A_SIGNED 1'0
3752 parameter \A_WIDTH 4'1000
3753 parameter \Y_WIDTH 4'1000
3754 connect \A \load_v_i
3757 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3759 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
3761 parameter \A_SIGNED 1'0
3762 parameter \A_WIDTH 4'1000
3763 parameter \B_SIGNED 1'0
3764 parameter \B_WIDTH 4'1000
3765 parameter \Y_WIDTH 4'1000
3766 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
3771 assign \war_l_r 8'11111111
3776 assign \raw_l_s 8'00000000
3777 assign \raw_l_s \i_s_l
3780 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3782 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3784 parameter \A_SIGNED 1'0
3785 parameter \A_WIDTH 4'1000
3786 parameter \Y_WIDTH 4'1000
3787 connect \A \stor_v_i
3790 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3792 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
3794 parameter \A_SIGNED 1'0
3795 parameter \A_WIDTH 4'1000
3796 parameter \B_SIGNED 1'0
3797 parameter \B_WIDTH 4'1000
3798 parameter \Y_WIDTH 4'1000
3799 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
3804 assign \raw_l_r 8'11111111
3808 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3810 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3812 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3814 parameter \A_SIGNED 1'0
3815 parameter \A_WIDTH 4'1000
3816 parameter \B_SIGNED 1'0
3817 parameter \B_WIDTH 4'1000
3818 parameter \Y_WIDTH 4'1000
3819 connect \A \war_l_qn
3820 connect \B \load_hit_i
3823 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
3824 cell $reduce_bool $22
3825 parameter \A_SIGNED 1'0
3826 parameter \A_WIDTH 4'1000
3827 parameter \Y_WIDTH 1'1
3832 assign \ld_hold_st_o 1'0
3833 assign \ld_hold_st_o $19
3836 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3838 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3840 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3842 parameter \A_SIGNED 1'0
3843 parameter \A_WIDTH 4'1000
3844 parameter \B_SIGNED 1'0
3845 parameter \B_WIDTH 4'1000
3846 parameter \Y_WIDTH 4'1000
3847 connect \A \raw_l_qn
3848 connect \B \stwd_hit_i
3851 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
3852 cell $reduce_bool $26
3853 parameter \A_SIGNED 1'0
3854 parameter \A_WIDTH 4'1000
3855 parameter \Y_WIDTH 1'1
3860 assign \st_hold_ld_o 1'0
3861 assign \st_hold_ld_o $23
3865 attribute \generator "nMigen"
3866 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu7.war_l"
3868 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3869 wire width 1 input 0 \rst
3870 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
3871 wire width 1 input 1 \clk
3872 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
3873 wire width 8 input 2 \s
3874 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
3875 wire width 8 input 3 \r
3876 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
3877 wire width 8 output 4 \qn
3878 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3880 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
3881 wire width 8 \q_int$next
3882 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3884 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3886 parameter \A_SIGNED 1'0
3887 parameter \A_WIDTH 4'1000
3888 parameter \Y_WIDTH 4'1000
3892 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3894 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3896 parameter \A_SIGNED 1'0
3897 parameter \A_WIDTH 4'1000
3898 parameter \B_SIGNED 1'0
3899 parameter \B_WIDTH 4'1000
3900 parameter \Y_WIDTH 4'1000
3905 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3907 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
3909 parameter \A_SIGNED 1'0
3910 parameter \A_WIDTH 4'1000
3911 parameter \B_SIGNED 1'0
3912 parameter \B_WIDTH 4'1000
3913 parameter \Y_WIDTH 4'1000
3919 assign \q_int$next \q_int
3920 assign \q_int$next $5
3921 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
3924 assign \q_int$next 8'00000000
3927 update \q_int 8'00000000
3929 update \q_int \q_int$next
3931 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
3933 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3935 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3937 parameter \A_SIGNED 1'0
3938 parameter \A_WIDTH 4'1000
3939 parameter \Y_WIDTH 4'1000
3943 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3945 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3947 parameter \A_SIGNED 1'0
3948 parameter \A_WIDTH 4'1000
3949 parameter \B_SIGNED 1'0
3950 parameter \B_WIDTH 4'1000
3951 parameter \Y_WIDTH 4'1000
3956 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3958 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
3960 parameter \A_SIGNED 1'0
3961 parameter \A_WIDTH 4'1000
3962 parameter \B_SIGNED 1'0
3963 parameter \B_WIDTH 4'1000
3964 parameter \Y_WIDTH 4'1000
3970 assign \q 8'00000000
3974 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3976 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
3978 parameter \A_SIGNED 1'0
3979 parameter \A_WIDTH 4'1000
3980 parameter \Y_WIDTH 4'1000
3985 assign \qn 8'00000000
3989 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
3991 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3993 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
3995 parameter \A_SIGNED 1'0
3996 parameter \A_WIDTH 4'1000
3997 parameter \B_SIGNED 1'0
3998 parameter \B_WIDTH 4'1000
3999 parameter \Y_WIDTH 4'1000
4005 assign \qlq 8'00000000
4010 attribute \generator "nMigen"
4011 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu7.raw_l"
4013 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4014 wire width 1 input 0 \rst
4015 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4016 wire width 1 input 1 \clk
4017 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
4018 wire width 8 input 2 \s
4019 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
4020 wire width 8 input 3 \r
4021 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
4022 wire width 8 output 4 \qn
4023 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
4025 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
4026 wire width 8 \q_int$next
4027 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4029 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4031 parameter \A_SIGNED 1'0
4032 parameter \A_WIDTH 4'1000
4033 parameter \Y_WIDTH 4'1000
4037 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4039 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4041 parameter \A_SIGNED 1'0
4042 parameter \A_WIDTH 4'1000
4043 parameter \B_SIGNED 1'0
4044 parameter \B_WIDTH 4'1000
4045 parameter \Y_WIDTH 4'1000
4050 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4052 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4054 parameter \A_SIGNED 1'0
4055 parameter \A_WIDTH 4'1000
4056 parameter \B_SIGNED 1'0
4057 parameter \B_WIDTH 4'1000
4058 parameter \Y_WIDTH 4'1000
4064 assign \q_int$next \q_int
4065 assign \q_int$next $5
4066 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
4069 assign \q_int$next 8'00000000
4072 update \q_int 8'00000000
4074 update \q_int \q_int$next
4076 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
4078 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4080 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4082 parameter \A_SIGNED 1'0
4083 parameter \A_WIDTH 4'1000
4084 parameter \Y_WIDTH 4'1000
4088 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4090 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4092 parameter \A_SIGNED 1'0
4093 parameter \A_WIDTH 4'1000
4094 parameter \B_SIGNED 1'0
4095 parameter \B_WIDTH 4'1000
4096 parameter \Y_WIDTH 4'1000
4101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
4105 parameter \A_SIGNED 1'0
4106 parameter \A_WIDTH 4'1000
4107 parameter \B_SIGNED 1'0
4108 parameter \B_WIDTH 4'1000
4109 parameter \Y_WIDTH 4'1000
4115 assign \q 8'00000000
4119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
4121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
4123 parameter \A_SIGNED 1'0
4124 parameter \A_WIDTH 4'1000
4125 parameter \Y_WIDTH 4'1000
4130 assign \qn 8'00000000
4134 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
4136 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
4138 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
4140 parameter \A_SIGNED 1'0
4141 parameter \A_WIDTH 4'1000
4142 parameter \B_SIGNED 1'0
4143 parameter \B_WIDTH 4'1000
4144 parameter \Y_WIDTH 4'1000
4150 assign \qlq 8'00000000
4155 attribute \generator "nMigen"
4156 attribute \nmigen.hierarchy "top.ldstdeps.dm_fu7"
4158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4159 wire width 8 input 0 \load_hit_i
4160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4161 wire width 8 input 1 \stwd_hit_i
4162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4163 wire width 8 input 2 \load_v_i
4164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4165 wire width 8 input 3 \stor_v_i
4166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4167 wire width 1 input 4 \issue_i
4168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4169 wire width 1 input 5 \go_die_i
4170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4171 wire width 1 output 6 \ld_hold_st_o
4172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4173 wire width 1 output 7 \st_hold_ld_o
4174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4175 wire width 1 input 8 \load_h_i
4176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4177 wire width 1 input 9 \stor_h_i
4178 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4179 wire width 1 input 10 \rst
4180 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4181 wire width 1 input 11 \clk
4182 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
4183 wire width 8 \war_l_s
4184 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
4185 wire width 8 \war_l_r
4186 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
4187 wire width 8 \war_l_qn
4188 cell \war_l$13 \war_l
4193 connect \qn \war_l_qn
4195 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
4196 wire width 8 \raw_l_s
4197 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
4198 wire width 8 \raw_l_r
4199 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
4200 wire width 8 \raw_l_qn
4201 cell \raw_l$14 \raw_l
4206 connect \qn \raw_l_qn
4208 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:47"
4210 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
4212 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
4214 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:49"
4216 parameter \A_SIGNED 1'0
4217 parameter \A_WIDTH 4'1000
4218 parameter \B_SIGNED 1'0
4219 parameter \B_WIDTH 1'1
4220 parameter \Y_WIDTH 4'1000
4221 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
4222 connect \B \stor_h_i
4231 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:48"
4233 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
4235 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:50"
4237 parameter \A_SIGNED 1'0
4238 parameter \A_WIDTH 4'1000
4239 parameter \B_SIGNED 1'0
4240 parameter \B_WIDTH 4'1000
4241 parameter \Y_WIDTH 4'1000
4242 connect \A { \i_s \i_s \i_s \i_s \i_s \i_s \i_s \i_s }
4243 connect \B \load_v_i
4247 assign \i_s_l 8'00000000
4251 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:53"
4253 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
4255 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
4257 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:55"
4259 parameter \A_SIGNED 1'0
4260 parameter \A_WIDTH 4'1000
4261 parameter \B_SIGNED 1'0
4262 parameter \B_WIDTH 1'1
4263 parameter \Y_WIDTH 4'1000
4264 connect \A { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
4265 connect \B \load_h_i
4274 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:54"
4276 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
4278 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:56"
4280 parameter \A_SIGNED 1'0
4281 parameter \A_WIDTH 4'1000
4282 parameter \B_SIGNED 1'0
4283 parameter \B_WIDTH 4'1000
4284 parameter \Y_WIDTH 4'1000
4285 connect \A { \i_l \i_l \i_l \i_l \i_l \i_l \i_l \i_l }
4286 connect \B \stor_v_i
4290 assign \i_l_s 8'00000000
4295 assign \war_l_s 8'00000000
4296 assign \war_l_s \i_s_l
4299 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
4301 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
4303 parameter \A_SIGNED 1'0
4304 parameter \A_WIDTH 4'1000
4305 parameter \Y_WIDTH 4'1000
4306 connect \A \load_v_i
4309 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
4311 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:60"
4313 parameter \A_SIGNED 1'0
4314 parameter \A_WIDTH 4'1000
4315 parameter \B_SIGNED 1'0
4316 parameter \B_WIDTH 4'1000
4317 parameter \Y_WIDTH 4'1000
4318 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
4323 assign \war_l_r 8'11111111
4328 assign \raw_l_s 8'00000000
4329 assign \raw_l_s \i_s_l
4332 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
4334 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
4336 parameter \A_SIGNED 1'0
4337 parameter \A_WIDTH 4'1000
4338 parameter \Y_WIDTH 4'1000
4339 connect \A \stor_v_i
4342 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
4344 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:64"
4346 parameter \A_SIGNED 1'0
4347 parameter \A_WIDTH 4'1000
4348 parameter \B_SIGNED 1'0
4349 parameter \B_WIDTH 4'1000
4350 parameter \Y_WIDTH 4'1000
4351 connect \A { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
4356 assign \raw_l_r 8'11111111
4360 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
4362 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
4364 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
4366 parameter \A_SIGNED 1'0
4367 parameter \A_WIDTH 4'1000
4368 parameter \B_SIGNED 1'0
4369 parameter \B_WIDTH 4'1000
4370 parameter \Y_WIDTH 4'1000
4371 connect \A \war_l_qn
4372 connect \B \load_hit_i
4375 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:67"
4376 cell $reduce_bool $22
4377 parameter \A_SIGNED 1'0
4378 parameter \A_WIDTH 4'1000
4379 parameter \Y_WIDTH 1'1
4384 assign \ld_hold_st_o 1'0
4385 assign \ld_hold_st_o $19
4388 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
4390 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
4392 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
4394 parameter \A_SIGNED 1'0
4395 parameter \A_WIDTH 4'1000
4396 parameter \B_SIGNED 1'0
4397 parameter \B_WIDTH 4'1000
4398 parameter \Y_WIDTH 4'1000
4399 connect \A \raw_l_qn
4400 connect \B \stwd_hit_i
4403 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:68"
4404 cell $reduce_bool $26
4405 parameter \A_SIGNED 1'0
4406 parameter \A_WIDTH 4'1000
4407 parameter \Y_WIDTH 1'1
4412 assign \st_hold_ld_o 1'0
4413 assign \st_hold_ld_o $23
4417 attribute \generator "nMigen"
4418 attribute \nmigen.hierarchy "top.ldstdeps"
4420 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:51"
4421 wire width 8 input 0 \ld_pend_i
4422 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:52"
4423 wire width 8 input 1 \st_pend_i
4424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:53"
4425 wire width 8 input 2 \issue_i
4426 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:56"
4427 wire width 8 input 3 \load_hit_i
4428 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:58"
4429 wire width 8 input 4 \stwd_hit_i
4430 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:54"
4431 wire width 8 input 5 \go_die_i
4432 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:62"
4433 wire width 8 output 6 \ld_hold_st_o
4434 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:64"
4435 wire width 8 output 7 \st_hold_ld_o
4436 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4437 wire width 1 input 8 \rst
4438 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4439 wire width 1 input 9 \clk
4440 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4441 wire width 8 \dm_fu0_load_hit_i
4442 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4443 wire width 8 \dm_fu0_stwd_hit_i
4444 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4445 wire width 8 \dm_fu0_load_v_i
4446 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4447 wire width 8 \dm_fu0_stor_v_i
4448 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4449 wire width 1 \dm_fu0_issue_i
4450 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4451 wire width 1 \dm_fu0_go_die_i
4452 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4453 wire width 1 \dm_fu0_ld_hold_st_o
4454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4455 wire width 1 \dm_fu0_st_hold_ld_o
4456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4457 wire width 1 \dm_fu0_load_h_i
4458 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4459 wire width 1 \dm_fu0_stor_h_i
4460 cell \dm_fu0 \dm_fu0
4461 connect \load_hit_i \dm_fu0_load_hit_i
4462 connect \stwd_hit_i \dm_fu0_stwd_hit_i
4463 connect \load_v_i \dm_fu0_load_v_i
4464 connect \stor_v_i \dm_fu0_stor_v_i
4465 connect \issue_i \dm_fu0_issue_i
4466 connect \go_die_i \dm_fu0_go_die_i
4467 connect \ld_hold_st_o \dm_fu0_ld_hold_st_o
4468 connect \st_hold_ld_o \dm_fu0_st_hold_ld_o
4469 connect \load_h_i \dm_fu0_load_h_i
4470 connect \stor_h_i \dm_fu0_stor_h_i
4474 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4475 wire width 8 \dm_fu1_load_hit_i
4476 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4477 wire width 8 \dm_fu1_stwd_hit_i
4478 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4479 wire width 8 \dm_fu1_load_v_i
4480 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4481 wire width 8 \dm_fu1_stor_v_i
4482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4483 wire width 1 \dm_fu1_issue_i
4484 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4485 wire width 1 \dm_fu1_go_die_i
4486 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4487 wire width 1 \dm_fu1_ld_hold_st_o
4488 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4489 wire width 1 \dm_fu1_st_hold_ld_o
4490 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4491 wire width 1 \dm_fu1_load_h_i
4492 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4493 wire width 1 \dm_fu1_stor_h_i
4494 cell \dm_fu1 \dm_fu1
4495 connect \load_hit_i \dm_fu1_load_hit_i
4496 connect \stwd_hit_i \dm_fu1_stwd_hit_i
4497 connect \load_v_i \dm_fu1_load_v_i
4498 connect \stor_v_i \dm_fu1_stor_v_i
4499 connect \issue_i \dm_fu1_issue_i
4500 connect \go_die_i \dm_fu1_go_die_i
4501 connect \ld_hold_st_o \dm_fu1_ld_hold_st_o
4502 connect \st_hold_ld_o \dm_fu1_st_hold_ld_o
4503 connect \load_h_i \dm_fu1_load_h_i
4504 connect \stor_h_i \dm_fu1_stor_h_i
4508 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4509 wire width 8 \dm_fu2_load_hit_i
4510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4511 wire width 8 \dm_fu2_stwd_hit_i
4512 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4513 wire width 8 \dm_fu2_load_v_i
4514 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4515 wire width 8 \dm_fu2_stor_v_i
4516 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4517 wire width 1 \dm_fu2_issue_i
4518 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4519 wire width 1 \dm_fu2_go_die_i
4520 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4521 wire width 1 \dm_fu2_ld_hold_st_o
4522 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4523 wire width 1 \dm_fu2_st_hold_ld_o
4524 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4525 wire width 1 \dm_fu2_load_h_i
4526 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4527 wire width 1 \dm_fu2_stor_h_i
4528 cell \dm_fu2 \dm_fu2
4529 connect \load_hit_i \dm_fu2_load_hit_i
4530 connect \stwd_hit_i \dm_fu2_stwd_hit_i
4531 connect \load_v_i \dm_fu2_load_v_i
4532 connect \stor_v_i \dm_fu2_stor_v_i
4533 connect \issue_i \dm_fu2_issue_i
4534 connect \go_die_i \dm_fu2_go_die_i
4535 connect \ld_hold_st_o \dm_fu2_ld_hold_st_o
4536 connect \st_hold_ld_o \dm_fu2_st_hold_ld_o
4537 connect \load_h_i \dm_fu2_load_h_i
4538 connect \stor_h_i \dm_fu2_stor_h_i
4542 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4543 wire width 8 \dm_fu3_load_hit_i
4544 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4545 wire width 8 \dm_fu3_stwd_hit_i
4546 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4547 wire width 8 \dm_fu3_load_v_i
4548 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4549 wire width 8 \dm_fu3_stor_v_i
4550 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4551 wire width 1 \dm_fu3_issue_i
4552 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4553 wire width 1 \dm_fu3_go_die_i
4554 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4555 wire width 1 \dm_fu3_ld_hold_st_o
4556 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4557 wire width 1 \dm_fu3_st_hold_ld_o
4558 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4559 wire width 1 \dm_fu3_load_h_i
4560 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4561 wire width 1 \dm_fu3_stor_h_i
4562 cell \dm_fu3 \dm_fu3
4563 connect \load_hit_i \dm_fu3_load_hit_i
4564 connect \stwd_hit_i \dm_fu3_stwd_hit_i
4565 connect \load_v_i \dm_fu3_load_v_i
4566 connect \stor_v_i \dm_fu3_stor_v_i
4567 connect \issue_i \dm_fu3_issue_i
4568 connect \go_die_i \dm_fu3_go_die_i
4569 connect \ld_hold_st_o \dm_fu3_ld_hold_st_o
4570 connect \st_hold_ld_o \dm_fu3_st_hold_ld_o
4571 connect \load_h_i \dm_fu3_load_h_i
4572 connect \stor_h_i \dm_fu3_stor_h_i
4576 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4577 wire width 8 \dm_fu4_load_hit_i
4578 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4579 wire width 8 \dm_fu4_stwd_hit_i
4580 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4581 wire width 8 \dm_fu4_load_v_i
4582 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4583 wire width 8 \dm_fu4_stor_v_i
4584 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4585 wire width 1 \dm_fu4_issue_i
4586 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4587 wire width 1 \dm_fu4_go_die_i
4588 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4589 wire width 1 \dm_fu4_ld_hold_st_o
4590 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4591 wire width 1 \dm_fu4_st_hold_ld_o
4592 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4593 wire width 1 \dm_fu4_load_h_i
4594 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4595 wire width 1 \dm_fu4_stor_h_i
4596 cell \dm_fu4 \dm_fu4
4597 connect \load_hit_i \dm_fu4_load_hit_i
4598 connect \stwd_hit_i \dm_fu4_stwd_hit_i
4599 connect \load_v_i \dm_fu4_load_v_i
4600 connect \stor_v_i \dm_fu4_stor_v_i
4601 connect \issue_i \dm_fu4_issue_i
4602 connect \go_die_i \dm_fu4_go_die_i
4603 connect \ld_hold_st_o \dm_fu4_ld_hold_st_o
4604 connect \st_hold_ld_o \dm_fu4_st_hold_ld_o
4605 connect \load_h_i \dm_fu4_load_h_i
4606 connect \stor_h_i \dm_fu4_stor_h_i
4610 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4611 wire width 8 \dm_fu5_load_hit_i
4612 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4613 wire width 8 \dm_fu5_stwd_hit_i
4614 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4615 wire width 8 \dm_fu5_load_v_i
4616 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4617 wire width 8 \dm_fu5_stor_v_i
4618 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4619 wire width 1 \dm_fu5_issue_i
4620 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4621 wire width 1 \dm_fu5_go_die_i
4622 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4623 wire width 1 \dm_fu5_ld_hold_st_o
4624 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4625 wire width 1 \dm_fu5_st_hold_ld_o
4626 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4627 wire width 1 \dm_fu5_load_h_i
4628 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4629 wire width 1 \dm_fu5_stor_h_i
4630 cell \dm_fu5 \dm_fu5
4631 connect \load_hit_i \dm_fu5_load_hit_i
4632 connect \stwd_hit_i \dm_fu5_stwd_hit_i
4633 connect \load_v_i \dm_fu5_load_v_i
4634 connect \stor_v_i \dm_fu5_stor_v_i
4635 connect \issue_i \dm_fu5_issue_i
4636 connect \go_die_i \dm_fu5_go_die_i
4637 connect \ld_hold_st_o \dm_fu5_ld_hold_st_o
4638 connect \st_hold_ld_o \dm_fu5_st_hold_ld_o
4639 connect \load_h_i \dm_fu5_load_h_i
4640 connect \stor_h_i \dm_fu5_stor_h_i
4644 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4645 wire width 8 \dm_fu6_load_hit_i
4646 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4647 wire width 8 \dm_fu6_stwd_hit_i
4648 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4649 wire width 8 \dm_fu6_load_v_i
4650 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4651 wire width 8 \dm_fu6_stor_v_i
4652 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4653 wire width 1 \dm_fu6_issue_i
4654 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4655 wire width 1 \dm_fu6_go_die_i
4656 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4657 wire width 1 \dm_fu6_ld_hold_st_o
4658 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4659 wire width 1 \dm_fu6_st_hold_ld_o
4660 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4661 wire width 1 \dm_fu6_load_h_i
4662 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4663 wire width 1 \dm_fu6_stor_h_i
4664 cell \dm_fu6 \dm_fu6
4665 connect \load_hit_i \dm_fu6_load_hit_i
4666 connect \stwd_hit_i \dm_fu6_stwd_hit_i
4667 connect \load_v_i \dm_fu6_load_v_i
4668 connect \stor_v_i \dm_fu6_stor_v_i
4669 connect \issue_i \dm_fu6_issue_i
4670 connect \go_die_i \dm_fu6_go_die_i
4671 connect \ld_hold_st_o \dm_fu6_ld_hold_st_o
4672 connect \st_hold_ld_o \dm_fu6_st_hold_ld_o
4673 connect \load_h_i \dm_fu6_load_h_i
4674 connect \stor_h_i \dm_fu6_stor_h_i
4678 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:30"
4679 wire width 8 \dm_fu7_load_hit_i
4680 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:31"
4681 wire width 8 \dm_fu7_stwd_hit_i
4682 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:23"
4683 wire width 8 \dm_fu7_load_v_i
4684 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:24"
4685 wire width 8 \dm_fu7_stor_v_i
4686 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:25"
4687 wire width 1 \dm_fu7_issue_i
4688 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:26"
4689 wire width 1 \dm_fu7_go_die_i
4690 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:34"
4691 wire width 1 \dm_fu7_ld_hold_st_o
4692 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:35"
4693 wire width 1 \dm_fu7_st_hold_ld_o
4694 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:21"
4695 wire width 1 \dm_fu7_load_h_i
4696 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_dep_cell.py:22"
4697 wire width 1 \dm_fu7_stor_h_i
4698 cell \dm_fu7 \dm_fu7
4699 connect \load_hit_i \dm_fu7_load_hit_i
4700 connect \stwd_hit_i \dm_fu7_stwd_hit_i
4701 connect \load_v_i \dm_fu7_load_v_i
4702 connect \stor_v_i \dm_fu7_stor_v_i
4703 connect \issue_i \dm_fu7_issue_i
4704 connect \go_die_i \dm_fu7_go_die_i
4705 connect \ld_hold_st_o \dm_fu7_ld_hold_st_o
4706 connect \st_hold_ld_o \dm_fu7_st_hold_ld_o
4707 connect \load_h_i \dm_fu7_load_h_i
4708 connect \stor_h_i \dm_fu7_stor_h_i
4713 assign \dm_fu0_load_hit_i 8'00000000
4714 assign \dm_fu0_load_hit_i \load_hit_i
4718 assign \dm_fu0_stwd_hit_i 8'00000000
4719 assign \dm_fu0_stwd_hit_i \stwd_hit_i
4723 assign \dm_fu0_load_v_i 8'00000000
4724 assign \dm_fu0_load_v_i \ld_pend_i
4728 assign \dm_fu0_stor_v_i 8'00000000
4729 assign \dm_fu0_stor_v_i \st_pend_i
4733 assign \dm_fu1_load_hit_i 8'00000000
4734 assign \dm_fu1_load_hit_i \load_hit_i
4738 assign \dm_fu1_stwd_hit_i 8'00000000
4739 assign \dm_fu1_stwd_hit_i \stwd_hit_i
4743 assign \dm_fu1_load_v_i 8'00000000
4744 assign \dm_fu1_load_v_i \ld_pend_i
4748 assign \dm_fu1_stor_v_i 8'00000000
4749 assign \dm_fu1_stor_v_i \st_pend_i
4753 assign \dm_fu2_load_hit_i 8'00000000
4754 assign \dm_fu2_load_hit_i \load_hit_i
4758 assign \dm_fu2_stwd_hit_i 8'00000000
4759 assign \dm_fu2_stwd_hit_i \stwd_hit_i
4763 assign \dm_fu2_load_v_i 8'00000000
4764 assign \dm_fu2_load_v_i \ld_pend_i
4768 assign \dm_fu2_stor_v_i 8'00000000
4769 assign \dm_fu2_stor_v_i \st_pend_i
4773 assign \dm_fu3_load_hit_i 8'00000000
4774 assign \dm_fu3_load_hit_i \load_hit_i
4778 assign \dm_fu3_stwd_hit_i 8'00000000
4779 assign \dm_fu3_stwd_hit_i \stwd_hit_i
4783 assign \dm_fu3_load_v_i 8'00000000
4784 assign \dm_fu3_load_v_i \ld_pend_i
4788 assign \dm_fu3_stor_v_i 8'00000000
4789 assign \dm_fu3_stor_v_i \st_pend_i
4793 assign \dm_fu4_load_hit_i 8'00000000
4794 assign \dm_fu4_load_hit_i \load_hit_i
4798 assign \dm_fu4_stwd_hit_i 8'00000000
4799 assign \dm_fu4_stwd_hit_i \stwd_hit_i
4803 assign \dm_fu4_load_v_i 8'00000000
4804 assign \dm_fu4_load_v_i \ld_pend_i
4808 assign \dm_fu4_stor_v_i 8'00000000
4809 assign \dm_fu4_stor_v_i \st_pend_i
4813 assign \dm_fu5_load_hit_i 8'00000000
4814 assign \dm_fu5_load_hit_i \load_hit_i
4818 assign \dm_fu5_stwd_hit_i 8'00000000
4819 assign \dm_fu5_stwd_hit_i \stwd_hit_i
4823 assign \dm_fu5_load_v_i 8'00000000
4824 assign \dm_fu5_load_v_i \ld_pend_i
4828 assign \dm_fu5_stor_v_i 8'00000000
4829 assign \dm_fu5_stor_v_i \st_pend_i
4833 assign \dm_fu6_load_hit_i 8'00000000
4834 assign \dm_fu6_load_hit_i \load_hit_i
4838 assign \dm_fu6_stwd_hit_i 8'00000000
4839 assign \dm_fu6_stwd_hit_i \stwd_hit_i
4843 assign \dm_fu6_load_v_i 8'00000000
4844 assign \dm_fu6_load_v_i \ld_pend_i
4848 assign \dm_fu6_stor_v_i 8'00000000
4849 assign \dm_fu6_stor_v_i \st_pend_i
4853 assign \dm_fu7_load_hit_i 8'00000000
4854 assign \dm_fu7_load_hit_i \load_hit_i
4858 assign \dm_fu7_stwd_hit_i 8'00000000
4859 assign \dm_fu7_stwd_hit_i \stwd_hit_i
4863 assign \dm_fu7_load_v_i 8'00000000
4864 assign \dm_fu7_load_v_i \ld_pend_i
4868 assign \dm_fu7_stor_v_i 8'00000000
4869 assign \dm_fu7_stor_v_i \st_pend_i
4873 assign \dm_fu0_issue_i 1'0
4874 assign \dm_fu1_issue_i 1'0
4875 assign \dm_fu2_issue_i 1'0
4876 assign \dm_fu3_issue_i 1'0
4877 assign \dm_fu4_issue_i 1'0
4878 assign \dm_fu5_issue_i 1'0
4879 assign \dm_fu6_issue_i 1'0
4880 assign \dm_fu7_issue_i 1'0
4881 assign { \dm_fu7_issue_i \dm_fu6_issue_i \dm_fu5_issue_i \dm_fu4_issue_i \dm_fu3_issue_i \dm_fu2_issue_i \dm_fu1_issue_i \dm_fu0_issue_i } \issue_i
4885 assign \dm_fu0_go_die_i 1'0
4886 assign \dm_fu1_go_die_i 1'0
4887 assign \dm_fu2_go_die_i 1'0
4888 assign \dm_fu3_go_die_i 1'0
4889 assign \dm_fu4_go_die_i 1'0
4890 assign \dm_fu5_go_die_i 1'0
4891 assign \dm_fu6_go_die_i 1'0
4892 assign \dm_fu7_go_die_i 1'0
4893 assign { \dm_fu7_go_die_i \dm_fu6_go_die_i \dm_fu5_go_die_i \dm_fu4_go_die_i \dm_fu3_go_die_i \dm_fu2_go_die_i \dm_fu1_go_die_i \dm_fu0_go_die_i } \go_die_i
4897 assign \ld_hold_st_o 8'00000000
4898 assign \ld_hold_st_o { \dm_fu7_ld_hold_st_o \dm_fu6_ld_hold_st_o \dm_fu5_ld_hold_st_o \dm_fu4_ld_hold_st_o \dm_fu3_ld_hold_st_o \dm_fu2_ld_hold_st_o \dm_fu1_ld_hold_st_o \dm_fu0_ld_hold_st_o }
4902 assign \st_hold_ld_o 8'00000000
4903 assign \st_hold_ld_o { \dm_fu7_st_hold_ld_o \dm_fu6_st_hold_ld_o \dm_fu5_st_hold_ld_o \dm_fu4_st_hold_ld_o \dm_fu3_st_hold_ld_o \dm_fu2_st_hold_ld_o \dm_fu1_st_hold_ld_o \dm_fu0_st_hold_ld_o }
4907 assign \dm_fu0_load_h_i 1'0
4908 assign \dm_fu1_load_h_i 1'0
4909 assign \dm_fu2_load_h_i 1'0
4910 assign \dm_fu3_load_h_i 1'0
4911 assign \dm_fu4_load_h_i 1'0
4912 assign \dm_fu5_load_h_i 1'0
4913 assign \dm_fu6_load_h_i 1'0
4914 assign \dm_fu7_load_h_i 1'0
4915 assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4916 assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4917 assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4918 assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4919 assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4920 assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4921 assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4922 assign { \dm_fu7_load_h_i \dm_fu6_load_h_i \dm_fu5_load_h_i \dm_fu4_load_h_i \dm_fu3_load_h_i \dm_fu2_load_h_i \dm_fu1_load_h_i \dm_fu0_load_h_i } \ld_pend_i
4926 assign \dm_fu0_stor_h_i 1'0
4927 assign \dm_fu1_stor_h_i 1'0
4928 assign \dm_fu2_stor_h_i 1'0
4929 assign \dm_fu3_stor_h_i 1'0
4930 assign \dm_fu4_stor_h_i 1'0
4931 assign \dm_fu5_stor_h_i 1'0
4932 assign \dm_fu6_stor_h_i 1'0
4933 assign \dm_fu7_stor_h_i 1'0
4934 assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4935 assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4936 assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4937 assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4938 assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4939 assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4940 assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4941 assign { \dm_fu7_stor_h_i \dm_fu6_stor_h_i \dm_fu5_stor_h_i \dm_fu4_stor_h_i \dm_fu3_stor_h_i \dm_fu2_stor_h_i \dm_fu1_stor_h_i \dm_fu0_stor_h_i } \st_pend_i
4945 attribute \generator "nMigen"
4946 attribute \nmigen.hierarchy "top.fumemdeps.dm0.st_c"
4948 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4949 wire width 1 input 0 \rst
4950 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
4951 wire width 1 input 1 \clk
4952 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
4953 wire width 8 input 2 \s
4954 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
4955 wire width 8 input 3 \r
4956 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
4957 wire width 8 output 4 \qlq
4958 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
4960 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
4961 wire width 8 \q_int$next
4962 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4964 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4966 parameter \A_SIGNED 1'0
4967 parameter \A_WIDTH 4'1000
4968 parameter \Y_WIDTH 4'1000
4972 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4974 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4976 parameter \A_SIGNED 1'0
4977 parameter \A_WIDTH 4'1000
4978 parameter \B_SIGNED 1'0
4979 parameter \B_WIDTH 4'1000
4980 parameter \Y_WIDTH 4'1000
4985 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4987 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
4989 parameter \A_SIGNED 1'0
4990 parameter \A_WIDTH 4'1000
4991 parameter \B_SIGNED 1'0
4992 parameter \B_WIDTH 4'1000
4993 parameter \Y_WIDTH 4'1000
4999 assign \q_int$next \q_int
5000 assign \q_int$next $5
5001 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
5004 assign \q_int$next 8'00000000
5007 update \q_int 8'00000000
5009 update \q_int \q_int$next
5011 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
5013 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5015 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5017 parameter \A_SIGNED 1'0
5018 parameter \A_WIDTH 4'1000
5019 parameter \Y_WIDTH 4'1000
5023 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5025 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5027 parameter \A_SIGNED 1'0
5028 parameter \A_WIDTH 4'1000
5029 parameter \B_SIGNED 1'0
5030 parameter \B_WIDTH 4'1000
5031 parameter \Y_WIDTH 4'1000
5036 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5038 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5040 parameter \A_SIGNED 1'0
5041 parameter \A_WIDTH 4'1000
5042 parameter \B_SIGNED 1'0
5043 parameter \B_WIDTH 4'1000
5044 parameter \Y_WIDTH 4'1000
5050 assign \q 8'00000000
5054 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
5056 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5058 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5060 parameter \A_SIGNED 1'0
5061 parameter \A_WIDTH 4'1000
5062 parameter \Y_WIDTH 4'1000
5067 assign \qn 8'00000000
5071 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5073 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5075 parameter \A_SIGNED 1'0
5076 parameter \A_WIDTH 4'1000
5077 parameter \B_SIGNED 1'0
5078 parameter \B_WIDTH 4'1000
5079 parameter \Y_WIDTH 4'1000
5085 assign \qlq 8'00000000
5090 attribute \generator "nMigen"
5091 attribute \nmigen.hierarchy "top.fumemdeps.dm0.ld_c"
5093 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5094 wire width 1 input 0 \rst
5095 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5096 wire width 1 input 1 \clk
5097 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5098 wire width 8 input 2 \s
5099 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5100 wire width 8 input 3 \r
5101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5102 wire width 8 output 4 \qlq
5103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5106 wire width 8 \q_int$next
5107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5111 parameter \A_SIGNED 1'0
5112 parameter \A_WIDTH 4'1000
5113 parameter \Y_WIDTH 4'1000
5117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5121 parameter \A_SIGNED 1'0
5122 parameter \A_WIDTH 4'1000
5123 parameter \B_SIGNED 1'0
5124 parameter \B_WIDTH 4'1000
5125 parameter \Y_WIDTH 4'1000
5130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5132 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5134 parameter \A_SIGNED 1'0
5135 parameter \A_WIDTH 4'1000
5136 parameter \B_SIGNED 1'0
5137 parameter \B_WIDTH 4'1000
5138 parameter \Y_WIDTH 4'1000
5144 assign \q_int$next \q_int
5145 assign \q_int$next $5
5146 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
5149 assign \q_int$next 8'00000000
5152 update \q_int 8'00000000
5154 update \q_int \q_int$next
5156 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
5158 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5160 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5162 parameter \A_SIGNED 1'0
5163 parameter \A_WIDTH 4'1000
5164 parameter \Y_WIDTH 4'1000
5168 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5170 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5172 parameter \A_SIGNED 1'0
5173 parameter \A_WIDTH 4'1000
5174 parameter \B_SIGNED 1'0
5175 parameter \B_WIDTH 4'1000
5176 parameter \Y_WIDTH 4'1000
5181 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5183 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5185 parameter \A_SIGNED 1'0
5186 parameter \A_WIDTH 4'1000
5187 parameter \B_SIGNED 1'0
5188 parameter \B_WIDTH 4'1000
5189 parameter \Y_WIDTH 4'1000
5195 assign \q 8'00000000
5199 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
5201 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5203 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5205 parameter \A_SIGNED 1'0
5206 parameter \A_WIDTH 4'1000
5207 parameter \Y_WIDTH 4'1000
5212 assign \qn 8'00000000
5216 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5218 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5220 parameter \A_SIGNED 1'0
5221 parameter \A_WIDTH 4'1000
5222 parameter \B_SIGNED 1'0
5223 parameter \B_WIDTH 4'1000
5224 parameter \Y_WIDTH 4'1000
5230 assign \qlq 8'00000000
5235 attribute \generator "nMigen"
5236 attribute \nmigen.hierarchy "top.fumemdeps.dm0"
5238 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5239 wire width 1 input 0 \rst
5240 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5241 wire width 1 input 1 \clk
5242 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
5243 wire width 8 output 2 \st_wait_o
5244 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
5245 wire width 8 output 3 \ld_wait_o
5246 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
5247 wire width 8 input 4 \issue_i
5248 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
5249 wire width 8 input 5 \go_st_i
5250 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
5251 wire width 8 input 6 \go_ld_i
5252 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
5253 wire width 8 input 7 \go_die_i
5254 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
5255 wire width 8 input 8 \st_pend_i
5256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
5257 wire width 8 input 9 \ld_pend_i
5258 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5259 wire width 8 \st_c_s
5260 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5261 wire width 8 \st_c_r
5262 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5263 wire width 8 \st_c_qlq
5269 connect \qlq \st_c_qlq
5271 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5272 wire width 8 \ld_c_s
5273 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5274 wire width 8 \ld_c_r
5275 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5276 wire width 8 \ld_c_qlq
5282 connect \qlq \ld_c_qlq
5284 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
5286 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
5288 parameter \A_SIGNED 1'0
5289 parameter \A_WIDTH 4'1000
5290 parameter \B_SIGNED 1'0
5291 parameter \B_WIDTH 4'1000
5292 parameter \Y_WIDTH 4'1000
5294 connect \B \st_pend_i
5297 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5299 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5301 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5303 parameter \A_SIGNED 1'0
5304 parameter \A_WIDTH 4'1000
5305 parameter \B_SIGNED 1'0
5306 parameter \B_WIDTH 4'1000
5307 parameter \Y_WIDTH 4'1000
5309 connect \B \st_pend_i
5312 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5314 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5316 parameter \A_SIGNED 1'1
5317 parameter \A_WIDTH 4'1000
5318 parameter \B_SIGNED 1'1
5319 parameter \B_WIDTH 4'1000
5320 parameter \Y_WIDTH 4'1001
5322 connect \B 8'11111110
5327 assign \st_c_s 8'00000000
5329 assign \st_c_s $3 [7:0]
5332 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
5334 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
5336 parameter \A_SIGNED 1'0
5337 parameter \A_WIDTH 4'1000
5338 parameter \B_SIGNED 1'0
5339 parameter \B_WIDTH 4'1000
5340 parameter \Y_WIDTH 4'1000
5342 connect \B \ld_pend_i
5345 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5347 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5349 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5351 parameter \A_SIGNED 1'0
5352 parameter \A_WIDTH 4'1000
5353 parameter \B_SIGNED 1'0
5354 parameter \B_WIDTH 4'1000
5355 parameter \Y_WIDTH 4'1000
5357 connect \B \ld_pend_i
5360 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5362 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5364 parameter \A_SIGNED 1'1
5365 parameter \A_WIDTH 4'1000
5366 parameter \B_SIGNED 1'1
5367 parameter \B_WIDTH 4'1000
5368 parameter \Y_WIDTH 4'1001
5370 connect \B 8'11111110
5375 assign \ld_c_s 8'00000000
5377 assign \ld_c_s $10 [7:0]
5380 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
5382 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
5384 parameter \A_SIGNED 1'0
5385 parameter \A_WIDTH 4'1000
5386 parameter \B_SIGNED 1'0
5387 parameter \B_WIDTH 4'1000
5388 parameter \Y_WIDTH 4'1000
5390 connect \B \go_die_i
5394 assign \ld_c_r 8'11111111
5398 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
5400 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
5402 parameter \A_SIGNED 1'0
5403 parameter \A_WIDTH 4'1000
5404 parameter \B_SIGNED 1'0
5405 parameter \B_WIDTH 4'1000
5406 parameter \Y_WIDTH 4'1000
5408 connect \B \go_die_i
5412 assign \st_c_r 8'11111111
5416 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5418 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5420 parameter \A_SIGNED 1'0
5421 parameter \A_WIDTH 4'1000
5422 parameter \Y_WIDTH 4'1000
5426 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5428 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5430 parameter \A_SIGNED 1'0
5431 parameter \A_WIDTH 4'1000
5432 parameter \B_SIGNED 1'0
5433 parameter \B_WIDTH 4'1000
5434 parameter \Y_WIDTH 4'1000
5435 connect \A \st_c_qlq
5440 assign \st_wait_o 8'00000000
5441 assign \st_wait_o $21
5444 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5446 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5448 parameter \A_SIGNED 1'0
5449 parameter \A_WIDTH 4'1000
5450 parameter \Y_WIDTH 4'1000
5454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5458 parameter \A_SIGNED 1'0
5459 parameter \A_WIDTH 4'1000
5460 parameter \B_SIGNED 1'0
5461 parameter \B_WIDTH 4'1000
5462 parameter \Y_WIDTH 4'1000
5463 connect \A \ld_c_qlq
5468 assign \ld_wait_o 8'00000000
5469 assign \ld_wait_o $25
5473 attribute \generator "nMigen"
5474 attribute \nmigen.hierarchy "top.fumemdeps.dm1.st_c"
5476 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5477 wire width 1 input 0 \rst
5478 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5479 wire width 1 input 1 \clk
5480 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5481 wire width 8 input 2 \s
5482 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5483 wire width 8 input 3 \r
5484 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5485 wire width 8 output 4 \qlq
5486 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5488 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5489 wire width 8 \q_int$next
5490 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5492 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5494 parameter \A_SIGNED 1'0
5495 parameter \A_WIDTH 4'1000
5496 parameter \Y_WIDTH 4'1000
5500 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5502 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5504 parameter \A_SIGNED 1'0
5505 parameter \A_WIDTH 4'1000
5506 parameter \B_SIGNED 1'0
5507 parameter \B_WIDTH 4'1000
5508 parameter \Y_WIDTH 4'1000
5513 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5515 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5517 parameter \A_SIGNED 1'0
5518 parameter \A_WIDTH 4'1000
5519 parameter \B_SIGNED 1'0
5520 parameter \B_WIDTH 4'1000
5521 parameter \Y_WIDTH 4'1000
5527 assign \q_int$next \q_int
5528 assign \q_int$next $5
5529 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
5532 assign \q_int$next 8'00000000
5535 update \q_int 8'00000000
5537 update \q_int \q_int$next
5539 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
5541 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5543 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5545 parameter \A_SIGNED 1'0
5546 parameter \A_WIDTH 4'1000
5547 parameter \Y_WIDTH 4'1000
5551 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5553 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5555 parameter \A_SIGNED 1'0
5556 parameter \A_WIDTH 4'1000
5557 parameter \B_SIGNED 1'0
5558 parameter \B_WIDTH 4'1000
5559 parameter \Y_WIDTH 4'1000
5564 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5566 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5568 parameter \A_SIGNED 1'0
5569 parameter \A_WIDTH 4'1000
5570 parameter \B_SIGNED 1'0
5571 parameter \B_WIDTH 4'1000
5572 parameter \Y_WIDTH 4'1000
5578 assign \q 8'00000000
5582 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
5584 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5586 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5588 parameter \A_SIGNED 1'0
5589 parameter \A_WIDTH 4'1000
5590 parameter \Y_WIDTH 4'1000
5595 assign \qn 8'00000000
5599 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5601 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5603 parameter \A_SIGNED 1'0
5604 parameter \A_WIDTH 4'1000
5605 parameter \B_SIGNED 1'0
5606 parameter \B_WIDTH 4'1000
5607 parameter \Y_WIDTH 4'1000
5613 assign \qlq 8'00000000
5618 attribute \generator "nMigen"
5619 attribute \nmigen.hierarchy "top.fumemdeps.dm1.ld_c"
5621 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5622 wire width 1 input 0 \rst
5623 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5624 wire width 1 input 1 \clk
5625 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5626 wire width 8 input 2 \s
5627 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5628 wire width 8 input 3 \r
5629 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5630 wire width 8 output 4 \qlq
5631 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5633 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
5634 wire width 8 \q_int$next
5635 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5637 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5639 parameter \A_SIGNED 1'0
5640 parameter \A_WIDTH 4'1000
5641 parameter \Y_WIDTH 4'1000
5645 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5647 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5649 parameter \A_SIGNED 1'0
5650 parameter \A_WIDTH 4'1000
5651 parameter \B_SIGNED 1'0
5652 parameter \B_WIDTH 4'1000
5653 parameter \Y_WIDTH 4'1000
5658 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5660 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
5662 parameter \A_SIGNED 1'0
5663 parameter \A_WIDTH 4'1000
5664 parameter \B_SIGNED 1'0
5665 parameter \B_WIDTH 4'1000
5666 parameter \Y_WIDTH 4'1000
5672 assign \q_int$next \q_int
5673 assign \q_int$next $5
5674 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
5677 assign \q_int$next 8'00000000
5680 update \q_int 8'00000000
5682 update \q_int \q_int$next
5684 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
5686 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5688 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5690 parameter \A_SIGNED 1'0
5691 parameter \A_WIDTH 4'1000
5692 parameter \Y_WIDTH 4'1000
5696 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5698 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5700 parameter \A_SIGNED 1'0
5701 parameter \A_WIDTH 4'1000
5702 parameter \B_SIGNED 1'0
5703 parameter \B_WIDTH 4'1000
5704 parameter \Y_WIDTH 4'1000
5709 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5711 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
5713 parameter \A_SIGNED 1'0
5714 parameter \A_WIDTH 4'1000
5715 parameter \B_SIGNED 1'0
5716 parameter \B_WIDTH 4'1000
5717 parameter \Y_WIDTH 4'1000
5723 assign \q 8'00000000
5727 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
5729 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5731 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
5733 parameter \A_SIGNED 1'0
5734 parameter \A_WIDTH 4'1000
5735 parameter \Y_WIDTH 4'1000
5740 assign \qn 8'00000000
5744 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5746 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
5748 parameter \A_SIGNED 1'0
5749 parameter \A_WIDTH 4'1000
5750 parameter \B_SIGNED 1'0
5751 parameter \B_WIDTH 4'1000
5752 parameter \Y_WIDTH 4'1000
5758 assign \qlq 8'00000000
5763 attribute \generator "nMigen"
5764 attribute \nmigen.hierarchy "top.fumemdeps.dm1"
5766 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5767 wire width 1 input 0 \rst
5768 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
5769 wire width 1 input 1 \clk
5770 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
5771 wire width 8 output 2 \st_wait_o
5772 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
5773 wire width 8 output 3 \ld_wait_o
5774 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
5775 wire width 8 input 4 \issue_i
5776 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
5777 wire width 8 input 5 \go_st_i
5778 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
5779 wire width 8 input 6 \go_ld_i
5780 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
5781 wire width 8 input 7 \go_die_i
5782 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
5783 wire width 8 input 8 \st_pend_i
5784 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
5785 wire width 8 input 9 \ld_pend_i
5786 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5787 wire width 8 \st_c_s
5788 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5789 wire width 8 \st_c_r
5790 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5791 wire width 8 \st_c_qlq
5797 connect \qlq \st_c_qlq
5799 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
5800 wire width 8 \ld_c_s
5801 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
5802 wire width 8 \ld_c_r
5803 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
5804 wire width 8 \ld_c_qlq
5810 connect \qlq \ld_c_qlq
5812 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
5814 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
5816 parameter \A_SIGNED 1'0
5817 parameter \A_WIDTH 4'1000
5818 parameter \B_SIGNED 1'0
5819 parameter \B_WIDTH 4'1000
5820 parameter \Y_WIDTH 4'1000
5822 connect \B \st_pend_i
5825 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5827 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5829 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5831 parameter \A_SIGNED 1'0
5832 parameter \A_WIDTH 4'1000
5833 parameter \B_SIGNED 1'0
5834 parameter \B_WIDTH 4'1000
5835 parameter \Y_WIDTH 4'1000
5837 connect \B \st_pend_i
5840 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5842 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
5844 parameter \A_SIGNED 1'1
5845 parameter \A_WIDTH 4'1000
5846 parameter \B_SIGNED 1'1
5847 parameter \B_WIDTH 4'1000
5848 parameter \Y_WIDTH 4'1001
5850 connect \B 8'11111101
5855 assign \st_c_s 8'00000000
5857 assign \st_c_s $3 [7:0]
5860 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
5862 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
5864 parameter \A_SIGNED 1'0
5865 parameter \A_WIDTH 4'1000
5866 parameter \B_SIGNED 1'0
5867 parameter \B_WIDTH 4'1000
5868 parameter \Y_WIDTH 4'1000
5870 connect \B \ld_pend_i
5873 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5875 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5877 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5879 parameter \A_SIGNED 1'0
5880 parameter \A_WIDTH 4'1000
5881 parameter \B_SIGNED 1'0
5882 parameter \B_WIDTH 4'1000
5883 parameter \Y_WIDTH 4'1000
5885 connect \B \ld_pend_i
5888 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5890 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
5892 parameter \A_SIGNED 1'1
5893 parameter \A_WIDTH 4'1000
5894 parameter \B_SIGNED 1'1
5895 parameter \B_WIDTH 4'1000
5896 parameter \Y_WIDTH 4'1001
5898 connect \B 8'11111101
5903 assign \ld_c_s 8'00000000
5905 assign \ld_c_s $10 [7:0]
5908 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
5910 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
5912 parameter \A_SIGNED 1'0
5913 parameter \A_WIDTH 4'1000
5914 parameter \B_SIGNED 1'0
5915 parameter \B_WIDTH 4'1000
5916 parameter \Y_WIDTH 4'1000
5918 connect \B \go_die_i
5922 assign \ld_c_r 8'11111111
5926 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
5928 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
5930 parameter \A_SIGNED 1'0
5931 parameter \A_WIDTH 4'1000
5932 parameter \B_SIGNED 1'0
5933 parameter \B_WIDTH 4'1000
5934 parameter \Y_WIDTH 4'1000
5936 connect \B \go_die_i
5940 assign \st_c_r 8'11111111
5944 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5946 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5948 parameter \A_SIGNED 1'0
5949 parameter \A_WIDTH 4'1000
5950 parameter \Y_WIDTH 4'1000
5954 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5956 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
5958 parameter \A_SIGNED 1'0
5959 parameter \A_WIDTH 4'1000
5960 parameter \B_SIGNED 1'0
5961 parameter \B_WIDTH 4'1000
5962 parameter \Y_WIDTH 4'1000
5963 connect \A \st_c_qlq
5968 assign \st_wait_o 8'00000000
5969 assign \st_wait_o $21
5972 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5974 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5976 parameter \A_SIGNED 1'0
5977 parameter \A_WIDTH 4'1000
5978 parameter \Y_WIDTH 4'1000
5982 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5984 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
5986 parameter \A_SIGNED 1'0
5987 parameter \A_WIDTH 4'1000
5988 parameter \B_SIGNED 1'0
5989 parameter \B_WIDTH 4'1000
5990 parameter \Y_WIDTH 4'1000
5991 connect \A \ld_c_qlq
5996 assign \ld_wait_o 8'00000000
5997 assign \ld_wait_o $25
6001 attribute \generator "nMigen"
6002 attribute \nmigen.hierarchy "top.fumemdeps.dm2.st_c"
6004 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6005 wire width 1 input 0 \rst
6006 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6007 wire width 1 input 1 \clk
6008 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6009 wire width 8 input 2 \s
6010 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6011 wire width 8 input 3 \r
6012 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6013 wire width 8 output 4 \qlq
6014 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6016 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6017 wire width 8 \q_int$next
6018 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6020 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6022 parameter \A_SIGNED 1'0
6023 parameter \A_WIDTH 4'1000
6024 parameter \Y_WIDTH 4'1000
6028 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6030 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6032 parameter \A_SIGNED 1'0
6033 parameter \A_WIDTH 4'1000
6034 parameter \B_SIGNED 1'0
6035 parameter \B_WIDTH 4'1000
6036 parameter \Y_WIDTH 4'1000
6041 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6043 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6045 parameter \A_SIGNED 1'0
6046 parameter \A_WIDTH 4'1000
6047 parameter \B_SIGNED 1'0
6048 parameter \B_WIDTH 4'1000
6049 parameter \Y_WIDTH 4'1000
6055 assign \q_int$next \q_int
6056 assign \q_int$next $5
6057 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
6060 assign \q_int$next 8'00000000
6063 update \q_int 8'00000000
6065 update \q_int \q_int$next
6067 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
6069 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6071 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6073 parameter \A_SIGNED 1'0
6074 parameter \A_WIDTH 4'1000
6075 parameter \Y_WIDTH 4'1000
6079 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6081 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6083 parameter \A_SIGNED 1'0
6084 parameter \A_WIDTH 4'1000
6085 parameter \B_SIGNED 1'0
6086 parameter \B_WIDTH 4'1000
6087 parameter \Y_WIDTH 4'1000
6092 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6094 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6096 parameter \A_SIGNED 1'0
6097 parameter \A_WIDTH 4'1000
6098 parameter \B_SIGNED 1'0
6099 parameter \B_WIDTH 4'1000
6100 parameter \Y_WIDTH 4'1000
6106 assign \q 8'00000000
6110 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
6112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6114 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6116 parameter \A_SIGNED 1'0
6117 parameter \A_WIDTH 4'1000
6118 parameter \Y_WIDTH 4'1000
6123 assign \qn 8'00000000
6127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6131 parameter \A_SIGNED 1'0
6132 parameter \A_WIDTH 4'1000
6133 parameter \B_SIGNED 1'0
6134 parameter \B_WIDTH 4'1000
6135 parameter \Y_WIDTH 4'1000
6141 assign \qlq 8'00000000
6146 attribute \generator "nMigen"
6147 attribute \nmigen.hierarchy "top.fumemdeps.dm2.ld_c"
6149 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6150 wire width 1 input 0 \rst
6151 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6152 wire width 1 input 1 \clk
6153 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6154 wire width 8 input 2 \s
6155 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6156 wire width 8 input 3 \r
6157 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6158 wire width 8 output 4 \qlq
6159 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6161 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6162 wire width 8 \q_int$next
6163 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6165 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6167 parameter \A_SIGNED 1'0
6168 parameter \A_WIDTH 4'1000
6169 parameter \Y_WIDTH 4'1000
6173 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6177 parameter \A_SIGNED 1'0
6178 parameter \A_WIDTH 4'1000
6179 parameter \B_SIGNED 1'0
6180 parameter \B_WIDTH 4'1000
6181 parameter \Y_WIDTH 4'1000
6186 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6188 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6190 parameter \A_SIGNED 1'0
6191 parameter \A_WIDTH 4'1000
6192 parameter \B_SIGNED 1'0
6193 parameter \B_WIDTH 4'1000
6194 parameter \Y_WIDTH 4'1000
6200 assign \q_int$next \q_int
6201 assign \q_int$next $5
6202 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
6205 assign \q_int$next 8'00000000
6208 update \q_int 8'00000000
6210 update \q_int \q_int$next
6212 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
6214 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6216 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6218 parameter \A_SIGNED 1'0
6219 parameter \A_WIDTH 4'1000
6220 parameter \Y_WIDTH 4'1000
6224 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6226 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6228 parameter \A_SIGNED 1'0
6229 parameter \A_WIDTH 4'1000
6230 parameter \B_SIGNED 1'0
6231 parameter \B_WIDTH 4'1000
6232 parameter \Y_WIDTH 4'1000
6237 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6239 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6241 parameter \A_SIGNED 1'0
6242 parameter \A_WIDTH 4'1000
6243 parameter \B_SIGNED 1'0
6244 parameter \B_WIDTH 4'1000
6245 parameter \Y_WIDTH 4'1000
6251 assign \q 8'00000000
6255 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
6257 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6259 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6261 parameter \A_SIGNED 1'0
6262 parameter \A_WIDTH 4'1000
6263 parameter \Y_WIDTH 4'1000
6268 assign \qn 8'00000000
6272 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6274 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6276 parameter \A_SIGNED 1'0
6277 parameter \A_WIDTH 4'1000
6278 parameter \B_SIGNED 1'0
6279 parameter \B_WIDTH 4'1000
6280 parameter \Y_WIDTH 4'1000
6286 assign \qlq 8'00000000
6291 attribute \generator "nMigen"
6292 attribute \nmigen.hierarchy "top.fumemdeps.dm2"
6294 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6295 wire width 1 input 0 \rst
6296 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6297 wire width 1 input 1 \clk
6298 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
6299 wire width 8 output 2 \st_wait_o
6300 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
6301 wire width 8 output 3 \ld_wait_o
6302 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
6303 wire width 8 input 4 \issue_i
6304 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
6305 wire width 8 input 5 \go_st_i
6306 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
6307 wire width 8 input 6 \go_ld_i
6308 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
6309 wire width 8 input 7 \go_die_i
6310 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
6311 wire width 8 input 8 \st_pend_i
6312 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
6313 wire width 8 input 9 \ld_pend_i
6314 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6315 wire width 8 \st_c_s
6316 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6317 wire width 8 \st_c_r
6318 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6319 wire width 8 \st_c_qlq
6325 connect \qlq \st_c_qlq
6327 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6328 wire width 8 \ld_c_s
6329 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6330 wire width 8 \ld_c_r
6331 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6332 wire width 8 \ld_c_qlq
6338 connect \qlq \ld_c_qlq
6340 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
6342 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
6344 parameter \A_SIGNED 1'0
6345 parameter \A_WIDTH 4'1000
6346 parameter \B_SIGNED 1'0
6347 parameter \B_WIDTH 4'1000
6348 parameter \Y_WIDTH 4'1000
6350 connect \B \st_pend_i
6353 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6355 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6357 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6359 parameter \A_SIGNED 1'0
6360 parameter \A_WIDTH 4'1000
6361 parameter \B_SIGNED 1'0
6362 parameter \B_WIDTH 4'1000
6363 parameter \Y_WIDTH 4'1000
6365 connect \B \st_pend_i
6368 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6370 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6372 parameter \A_SIGNED 1'1
6373 parameter \A_WIDTH 4'1000
6374 parameter \B_SIGNED 1'1
6375 parameter \B_WIDTH 4'1000
6376 parameter \Y_WIDTH 4'1001
6378 connect \B 8'11111011
6383 assign \st_c_s 8'00000000
6385 assign \st_c_s $3 [7:0]
6388 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
6390 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
6392 parameter \A_SIGNED 1'0
6393 parameter \A_WIDTH 4'1000
6394 parameter \B_SIGNED 1'0
6395 parameter \B_WIDTH 4'1000
6396 parameter \Y_WIDTH 4'1000
6398 connect \B \ld_pend_i
6401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6403 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6405 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6407 parameter \A_SIGNED 1'0
6408 parameter \A_WIDTH 4'1000
6409 parameter \B_SIGNED 1'0
6410 parameter \B_WIDTH 4'1000
6411 parameter \Y_WIDTH 4'1000
6413 connect \B \ld_pend_i
6416 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6418 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6420 parameter \A_SIGNED 1'1
6421 parameter \A_WIDTH 4'1000
6422 parameter \B_SIGNED 1'1
6423 parameter \B_WIDTH 4'1000
6424 parameter \Y_WIDTH 4'1001
6426 connect \B 8'11111011
6431 assign \ld_c_s 8'00000000
6433 assign \ld_c_s $10 [7:0]
6436 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
6438 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
6440 parameter \A_SIGNED 1'0
6441 parameter \A_WIDTH 4'1000
6442 parameter \B_SIGNED 1'0
6443 parameter \B_WIDTH 4'1000
6444 parameter \Y_WIDTH 4'1000
6446 connect \B \go_die_i
6450 assign \ld_c_r 8'11111111
6454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
6456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
6458 parameter \A_SIGNED 1'0
6459 parameter \A_WIDTH 4'1000
6460 parameter \B_SIGNED 1'0
6461 parameter \B_WIDTH 4'1000
6462 parameter \Y_WIDTH 4'1000
6464 connect \B \go_die_i
6468 assign \st_c_r 8'11111111
6472 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
6474 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
6476 parameter \A_SIGNED 1'0
6477 parameter \A_WIDTH 4'1000
6478 parameter \Y_WIDTH 4'1000
6482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
6484 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
6486 parameter \A_SIGNED 1'0
6487 parameter \A_WIDTH 4'1000
6488 parameter \B_SIGNED 1'0
6489 parameter \B_WIDTH 4'1000
6490 parameter \Y_WIDTH 4'1000
6491 connect \A \st_c_qlq
6496 assign \st_wait_o 8'00000000
6497 assign \st_wait_o $21
6500 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
6502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
6504 parameter \A_SIGNED 1'0
6505 parameter \A_WIDTH 4'1000
6506 parameter \Y_WIDTH 4'1000
6510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
6512 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
6514 parameter \A_SIGNED 1'0
6515 parameter \A_WIDTH 4'1000
6516 parameter \B_SIGNED 1'0
6517 parameter \B_WIDTH 4'1000
6518 parameter \Y_WIDTH 4'1000
6519 connect \A \ld_c_qlq
6524 assign \ld_wait_o 8'00000000
6525 assign \ld_wait_o $25
6529 attribute \generator "nMigen"
6530 attribute \nmigen.hierarchy "top.fumemdeps.dm3.st_c"
6532 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6533 wire width 1 input 0 \rst
6534 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6535 wire width 1 input 1 \clk
6536 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6537 wire width 8 input 2 \s
6538 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6539 wire width 8 input 3 \r
6540 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6541 wire width 8 output 4 \qlq
6542 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6544 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6545 wire width 8 \q_int$next
6546 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6548 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6550 parameter \A_SIGNED 1'0
6551 parameter \A_WIDTH 4'1000
6552 parameter \Y_WIDTH 4'1000
6556 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6558 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6560 parameter \A_SIGNED 1'0
6561 parameter \A_WIDTH 4'1000
6562 parameter \B_SIGNED 1'0
6563 parameter \B_WIDTH 4'1000
6564 parameter \Y_WIDTH 4'1000
6569 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6571 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6573 parameter \A_SIGNED 1'0
6574 parameter \A_WIDTH 4'1000
6575 parameter \B_SIGNED 1'0
6576 parameter \B_WIDTH 4'1000
6577 parameter \Y_WIDTH 4'1000
6583 assign \q_int$next \q_int
6584 assign \q_int$next $5
6585 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
6588 assign \q_int$next 8'00000000
6591 update \q_int 8'00000000
6593 update \q_int \q_int$next
6595 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
6597 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6599 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6601 parameter \A_SIGNED 1'0
6602 parameter \A_WIDTH 4'1000
6603 parameter \Y_WIDTH 4'1000
6607 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6609 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6611 parameter \A_SIGNED 1'0
6612 parameter \A_WIDTH 4'1000
6613 parameter \B_SIGNED 1'0
6614 parameter \B_WIDTH 4'1000
6615 parameter \Y_WIDTH 4'1000
6620 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6622 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6624 parameter \A_SIGNED 1'0
6625 parameter \A_WIDTH 4'1000
6626 parameter \B_SIGNED 1'0
6627 parameter \B_WIDTH 4'1000
6628 parameter \Y_WIDTH 4'1000
6634 assign \q 8'00000000
6638 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
6640 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6642 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6644 parameter \A_SIGNED 1'0
6645 parameter \A_WIDTH 4'1000
6646 parameter \Y_WIDTH 4'1000
6651 assign \qn 8'00000000
6655 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6657 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6659 parameter \A_SIGNED 1'0
6660 parameter \A_WIDTH 4'1000
6661 parameter \B_SIGNED 1'0
6662 parameter \B_WIDTH 4'1000
6663 parameter \Y_WIDTH 4'1000
6669 assign \qlq 8'00000000
6674 attribute \generator "nMigen"
6675 attribute \nmigen.hierarchy "top.fumemdeps.dm3.ld_c"
6677 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6678 wire width 1 input 0 \rst
6679 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6680 wire width 1 input 1 \clk
6681 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6682 wire width 8 input 2 \s
6683 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6684 wire width 8 input 3 \r
6685 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6686 wire width 8 output 4 \qlq
6687 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6689 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
6690 wire width 8 \q_int$next
6691 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6693 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6695 parameter \A_SIGNED 1'0
6696 parameter \A_WIDTH 4'1000
6697 parameter \Y_WIDTH 4'1000
6701 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6703 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6705 parameter \A_SIGNED 1'0
6706 parameter \A_WIDTH 4'1000
6707 parameter \B_SIGNED 1'0
6708 parameter \B_WIDTH 4'1000
6709 parameter \Y_WIDTH 4'1000
6714 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6716 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
6718 parameter \A_SIGNED 1'0
6719 parameter \A_WIDTH 4'1000
6720 parameter \B_SIGNED 1'0
6721 parameter \B_WIDTH 4'1000
6722 parameter \Y_WIDTH 4'1000
6728 assign \q_int$next \q_int
6729 assign \q_int$next $5
6730 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
6733 assign \q_int$next 8'00000000
6736 update \q_int 8'00000000
6738 update \q_int \q_int$next
6740 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
6742 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6744 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6746 parameter \A_SIGNED 1'0
6747 parameter \A_WIDTH 4'1000
6748 parameter \Y_WIDTH 4'1000
6752 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6754 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6756 parameter \A_SIGNED 1'0
6757 parameter \A_WIDTH 4'1000
6758 parameter \B_SIGNED 1'0
6759 parameter \B_WIDTH 4'1000
6760 parameter \Y_WIDTH 4'1000
6765 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6767 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
6769 parameter \A_SIGNED 1'0
6770 parameter \A_WIDTH 4'1000
6771 parameter \B_SIGNED 1'0
6772 parameter \B_WIDTH 4'1000
6773 parameter \Y_WIDTH 4'1000
6779 assign \q 8'00000000
6783 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
6785 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6787 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
6789 parameter \A_SIGNED 1'0
6790 parameter \A_WIDTH 4'1000
6791 parameter \Y_WIDTH 4'1000
6796 assign \qn 8'00000000
6800 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6802 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
6804 parameter \A_SIGNED 1'0
6805 parameter \A_WIDTH 4'1000
6806 parameter \B_SIGNED 1'0
6807 parameter \B_WIDTH 4'1000
6808 parameter \Y_WIDTH 4'1000
6814 assign \qlq 8'00000000
6819 attribute \generator "nMigen"
6820 attribute \nmigen.hierarchy "top.fumemdeps.dm3"
6822 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6823 wire width 1 input 0 \rst
6824 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
6825 wire width 1 input 1 \clk
6826 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
6827 wire width 8 output 2 \st_wait_o
6828 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
6829 wire width 8 output 3 \ld_wait_o
6830 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
6831 wire width 8 input 4 \issue_i
6832 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
6833 wire width 8 input 5 \go_st_i
6834 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
6835 wire width 8 input 6 \go_ld_i
6836 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
6837 wire width 8 input 7 \go_die_i
6838 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
6839 wire width 8 input 8 \st_pend_i
6840 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
6841 wire width 8 input 9 \ld_pend_i
6842 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6843 wire width 8 \st_c_s
6844 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6845 wire width 8 \st_c_r
6846 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6847 wire width 8 \st_c_qlq
6853 connect \qlq \st_c_qlq
6855 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
6856 wire width 8 \ld_c_s
6857 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
6858 wire width 8 \ld_c_r
6859 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
6860 wire width 8 \ld_c_qlq
6866 connect \qlq \ld_c_qlq
6868 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
6870 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
6872 parameter \A_SIGNED 1'0
6873 parameter \A_WIDTH 4'1000
6874 parameter \B_SIGNED 1'0
6875 parameter \B_WIDTH 4'1000
6876 parameter \Y_WIDTH 4'1000
6878 connect \B \st_pend_i
6881 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6883 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6885 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6887 parameter \A_SIGNED 1'0
6888 parameter \A_WIDTH 4'1000
6889 parameter \B_SIGNED 1'0
6890 parameter \B_WIDTH 4'1000
6891 parameter \Y_WIDTH 4'1000
6893 connect \B \st_pend_i
6896 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6898 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
6900 parameter \A_SIGNED 1'1
6901 parameter \A_WIDTH 4'1000
6902 parameter \B_SIGNED 1'1
6903 parameter \B_WIDTH 4'1000
6904 parameter \Y_WIDTH 4'1001
6906 connect \B 8'11110111
6911 assign \st_c_s 8'00000000
6913 assign \st_c_s $3 [7:0]
6916 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
6918 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
6920 parameter \A_SIGNED 1'0
6921 parameter \A_WIDTH 4'1000
6922 parameter \B_SIGNED 1'0
6923 parameter \B_WIDTH 4'1000
6924 parameter \Y_WIDTH 4'1000
6926 connect \B \ld_pend_i
6929 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6931 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6933 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6935 parameter \A_SIGNED 1'0
6936 parameter \A_WIDTH 4'1000
6937 parameter \B_SIGNED 1'0
6938 parameter \B_WIDTH 4'1000
6939 parameter \Y_WIDTH 4'1000
6941 connect \B \ld_pend_i
6944 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6946 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
6948 parameter \A_SIGNED 1'1
6949 parameter \A_WIDTH 4'1000
6950 parameter \B_SIGNED 1'1
6951 parameter \B_WIDTH 4'1000
6952 parameter \Y_WIDTH 4'1001
6954 connect \B 8'11110111
6959 assign \ld_c_s 8'00000000
6961 assign \ld_c_s $10 [7:0]
6964 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
6966 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
6968 parameter \A_SIGNED 1'0
6969 parameter \A_WIDTH 4'1000
6970 parameter \B_SIGNED 1'0
6971 parameter \B_WIDTH 4'1000
6972 parameter \Y_WIDTH 4'1000
6974 connect \B \go_die_i
6978 assign \ld_c_r 8'11111111
6982 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
6984 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
6986 parameter \A_SIGNED 1'0
6987 parameter \A_WIDTH 4'1000
6988 parameter \B_SIGNED 1'0
6989 parameter \B_WIDTH 4'1000
6990 parameter \Y_WIDTH 4'1000
6992 connect \B \go_die_i
6996 assign \st_c_r 8'11111111
7000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7002 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7004 parameter \A_SIGNED 1'0
7005 parameter \A_WIDTH 4'1000
7006 parameter \Y_WIDTH 4'1000
7010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7012 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7014 parameter \A_SIGNED 1'0
7015 parameter \A_WIDTH 4'1000
7016 parameter \B_SIGNED 1'0
7017 parameter \B_WIDTH 4'1000
7018 parameter \Y_WIDTH 4'1000
7019 connect \A \st_c_qlq
7024 assign \st_wait_o 8'00000000
7025 assign \st_wait_o $21
7028 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7030 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7032 parameter \A_SIGNED 1'0
7033 parameter \A_WIDTH 4'1000
7034 parameter \Y_WIDTH 4'1000
7038 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7040 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7042 parameter \A_SIGNED 1'0
7043 parameter \A_WIDTH 4'1000
7044 parameter \B_SIGNED 1'0
7045 parameter \B_WIDTH 4'1000
7046 parameter \Y_WIDTH 4'1000
7047 connect \A \ld_c_qlq
7052 assign \ld_wait_o 8'00000000
7053 assign \ld_wait_o $25
7057 attribute \generator "nMigen"
7058 attribute \nmigen.hierarchy "top.fumemdeps.dm4.st_c"
7060 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7061 wire width 1 input 0 \rst
7062 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7063 wire width 1 input 1 \clk
7064 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7065 wire width 8 input 2 \s
7066 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7067 wire width 8 input 3 \r
7068 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7069 wire width 8 output 4 \qlq
7070 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7072 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7073 wire width 8 \q_int$next
7074 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7076 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7078 parameter \A_SIGNED 1'0
7079 parameter \A_WIDTH 4'1000
7080 parameter \Y_WIDTH 4'1000
7084 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7086 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7088 parameter \A_SIGNED 1'0
7089 parameter \A_WIDTH 4'1000
7090 parameter \B_SIGNED 1'0
7091 parameter \B_WIDTH 4'1000
7092 parameter \Y_WIDTH 4'1000
7097 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7099 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7101 parameter \A_SIGNED 1'0
7102 parameter \A_WIDTH 4'1000
7103 parameter \B_SIGNED 1'0
7104 parameter \B_WIDTH 4'1000
7105 parameter \Y_WIDTH 4'1000
7111 assign \q_int$next \q_int
7112 assign \q_int$next $5
7113 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
7116 assign \q_int$next 8'00000000
7119 update \q_int 8'00000000
7121 update \q_int \q_int$next
7123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
7125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7129 parameter \A_SIGNED 1'0
7130 parameter \A_WIDTH 4'1000
7131 parameter \Y_WIDTH 4'1000
7135 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7137 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7139 parameter \A_SIGNED 1'0
7140 parameter \A_WIDTH 4'1000
7141 parameter \B_SIGNED 1'0
7142 parameter \B_WIDTH 4'1000
7143 parameter \Y_WIDTH 4'1000
7148 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7150 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7152 parameter \A_SIGNED 1'0
7153 parameter \A_WIDTH 4'1000
7154 parameter \B_SIGNED 1'0
7155 parameter \B_WIDTH 4'1000
7156 parameter \Y_WIDTH 4'1000
7162 assign \q 8'00000000
7166 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
7168 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7170 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7172 parameter \A_SIGNED 1'0
7173 parameter \A_WIDTH 4'1000
7174 parameter \Y_WIDTH 4'1000
7179 assign \qn 8'00000000
7183 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7185 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7187 parameter \A_SIGNED 1'0
7188 parameter \A_WIDTH 4'1000
7189 parameter \B_SIGNED 1'0
7190 parameter \B_WIDTH 4'1000
7191 parameter \Y_WIDTH 4'1000
7197 assign \qlq 8'00000000
7202 attribute \generator "nMigen"
7203 attribute \nmigen.hierarchy "top.fumemdeps.dm4.ld_c"
7205 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7206 wire width 1 input 0 \rst
7207 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7208 wire width 1 input 1 \clk
7209 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7210 wire width 8 input 2 \s
7211 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7212 wire width 8 input 3 \r
7213 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7214 wire width 8 output 4 \qlq
7215 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7217 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7218 wire width 8 \q_int$next
7219 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7221 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7223 parameter \A_SIGNED 1'0
7224 parameter \A_WIDTH 4'1000
7225 parameter \Y_WIDTH 4'1000
7229 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7231 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7233 parameter \A_SIGNED 1'0
7234 parameter \A_WIDTH 4'1000
7235 parameter \B_SIGNED 1'0
7236 parameter \B_WIDTH 4'1000
7237 parameter \Y_WIDTH 4'1000
7242 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7244 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7246 parameter \A_SIGNED 1'0
7247 parameter \A_WIDTH 4'1000
7248 parameter \B_SIGNED 1'0
7249 parameter \B_WIDTH 4'1000
7250 parameter \Y_WIDTH 4'1000
7256 assign \q_int$next \q_int
7257 assign \q_int$next $5
7258 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
7261 assign \q_int$next 8'00000000
7264 update \q_int 8'00000000
7266 update \q_int \q_int$next
7268 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
7270 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7272 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7274 parameter \A_SIGNED 1'0
7275 parameter \A_WIDTH 4'1000
7276 parameter \Y_WIDTH 4'1000
7280 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7282 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7284 parameter \A_SIGNED 1'0
7285 parameter \A_WIDTH 4'1000
7286 parameter \B_SIGNED 1'0
7287 parameter \B_WIDTH 4'1000
7288 parameter \Y_WIDTH 4'1000
7293 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7295 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7297 parameter \A_SIGNED 1'0
7298 parameter \A_WIDTH 4'1000
7299 parameter \B_SIGNED 1'0
7300 parameter \B_WIDTH 4'1000
7301 parameter \Y_WIDTH 4'1000
7307 assign \q 8'00000000
7311 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
7313 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7315 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7317 parameter \A_SIGNED 1'0
7318 parameter \A_WIDTH 4'1000
7319 parameter \Y_WIDTH 4'1000
7324 assign \qn 8'00000000
7328 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7330 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7332 parameter \A_SIGNED 1'0
7333 parameter \A_WIDTH 4'1000
7334 parameter \B_SIGNED 1'0
7335 parameter \B_WIDTH 4'1000
7336 parameter \Y_WIDTH 4'1000
7342 assign \qlq 8'00000000
7347 attribute \generator "nMigen"
7348 attribute \nmigen.hierarchy "top.fumemdeps.dm4"
7350 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7351 wire width 1 input 0 \rst
7352 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7353 wire width 1 input 1 \clk
7354 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
7355 wire width 8 output 2 \st_wait_o
7356 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
7357 wire width 8 output 3 \ld_wait_o
7358 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
7359 wire width 8 input 4 \issue_i
7360 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
7361 wire width 8 input 5 \go_st_i
7362 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
7363 wire width 8 input 6 \go_ld_i
7364 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
7365 wire width 8 input 7 \go_die_i
7366 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
7367 wire width 8 input 8 \st_pend_i
7368 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
7369 wire width 8 input 9 \ld_pend_i
7370 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7371 wire width 8 \st_c_s
7372 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7373 wire width 8 \st_c_r
7374 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7375 wire width 8 \st_c_qlq
7381 connect \qlq \st_c_qlq
7383 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7384 wire width 8 \ld_c_s
7385 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7386 wire width 8 \ld_c_r
7387 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7388 wire width 8 \ld_c_qlq
7394 connect \qlq \ld_c_qlq
7396 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
7398 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
7400 parameter \A_SIGNED 1'0
7401 parameter \A_WIDTH 4'1000
7402 parameter \B_SIGNED 1'0
7403 parameter \B_WIDTH 4'1000
7404 parameter \Y_WIDTH 4'1000
7406 connect \B \st_pend_i
7409 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7411 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7413 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7415 parameter \A_SIGNED 1'0
7416 parameter \A_WIDTH 4'1000
7417 parameter \B_SIGNED 1'0
7418 parameter \B_WIDTH 4'1000
7419 parameter \Y_WIDTH 4'1000
7421 connect \B \st_pend_i
7424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7426 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7428 parameter \A_SIGNED 1'1
7429 parameter \A_WIDTH 4'1000
7430 parameter \B_SIGNED 1'1
7431 parameter \B_WIDTH 4'1000
7432 parameter \Y_WIDTH 4'1001
7434 connect \B 8'11101111
7439 assign \st_c_s 8'00000000
7441 assign \st_c_s $3 [7:0]
7444 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
7446 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
7448 parameter \A_SIGNED 1'0
7449 parameter \A_WIDTH 4'1000
7450 parameter \B_SIGNED 1'0
7451 parameter \B_WIDTH 4'1000
7452 parameter \Y_WIDTH 4'1000
7454 connect \B \ld_pend_i
7457 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7459 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7461 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7463 parameter \A_SIGNED 1'0
7464 parameter \A_WIDTH 4'1000
7465 parameter \B_SIGNED 1'0
7466 parameter \B_WIDTH 4'1000
7467 parameter \Y_WIDTH 4'1000
7469 connect \B \ld_pend_i
7472 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7474 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7476 parameter \A_SIGNED 1'1
7477 parameter \A_WIDTH 4'1000
7478 parameter \B_SIGNED 1'1
7479 parameter \B_WIDTH 4'1000
7480 parameter \Y_WIDTH 4'1001
7482 connect \B 8'11101111
7487 assign \ld_c_s 8'00000000
7489 assign \ld_c_s $10 [7:0]
7492 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
7494 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
7496 parameter \A_SIGNED 1'0
7497 parameter \A_WIDTH 4'1000
7498 parameter \B_SIGNED 1'0
7499 parameter \B_WIDTH 4'1000
7500 parameter \Y_WIDTH 4'1000
7502 connect \B \go_die_i
7506 assign \ld_c_r 8'11111111
7510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
7512 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
7514 parameter \A_SIGNED 1'0
7515 parameter \A_WIDTH 4'1000
7516 parameter \B_SIGNED 1'0
7517 parameter \B_WIDTH 4'1000
7518 parameter \Y_WIDTH 4'1000
7520 connect \B \go_die_i
7524 assign \st_c_r 8'11111111
7528 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7530 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7532 parameter \A_SIGNED 1'0
7533 parameter \A_WIDTH 4'1000
7534 parameter \Y_WIDTH 4'1000
7538 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7540 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
7542 parameter \A_SIGNED 1'0
7543 parameter \A_WIDTH 4'1000
7544 parameter \B_SIGNED 1'0
7545 parameter \B_WIDTH 4'1000
7546 parameter \Y_WIDTH 4'1000
7547 connect \A \st_c_qlq
7552 assign \st_wait_o 8'00000000
7553 assign \st_wait_o $21
7556 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7558 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7560 parameter \A_SIGNED 1'0
7561 parameter \A_WIDTH 4'1000
7562 parameter \Y_WIDTH 4'1000
7566 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7568 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
7570 parameter \A_SIGNED 1'0
7571 parameter \A_WIDTH 4'1000
7572 parameter \B_SIGNED 1'0
7573 parameter \B_WIDTH 4'1000
7574 parameter \Y_WIDTH 4'1000
7575 connect \A \ld_c_qlq
7580 assign \ld_wait_o 8'00000000
7581 assign \ld_wait_o $25
7585 attribute \generator "nMigen"
7586 attribute \nmigen.hierarchy "top.fumemdeps.dm5.st_c"
7588 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7589 wire width 1 input 0 \rst
7590 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7591 wire width 1 input 1 \clk
7592 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7593 wire width 8 input 2 \s
7594 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7595 wire width 8 input 3 \r
7596 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7597 wire width 8 output 4 \qlq
7598 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7600 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7601 wire width 8 \q_int$next
7602 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7604 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7606 parameter \A_SIGNED 1'0
7607 parameter \A_WIDTH 4'1000
7608 parameter \Y_WIDTH 4'1000
7612 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7614 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7616 parameter \A_SIGNED 1'0
7617 parameter \A_WIDTH 4'1000
7618 parameter \B_SIGNED 1'0
7619 parameter \B_WIDTH 4'1000
7620 parameter \Y_WIDTH 4'1000
7625 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7627 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7629 parameter \A_SIGNED 1'0
7630 parameter \A_WIDTH 4'1000
7631 parameter \B_SIGNED 1'0
7632 parameter \B_WIDTH 4'1000
7633 parameter \Y_WIDTH 4'1000
7639 assign \q_int$next \q_int
7640 assign \q_int$next $5
7641 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
7644 assign \q_int$next 8'00000000
7647 update \q_int 8'00000000
7649 update \q_int \q_int$next
7651 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
7653 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7655 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7657 parameter \A_SIGNED 1'0
7658 parameter \A_WIDTH 4'1000
7659 parameter \Y_WIDTH 4'1000
7663 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7665 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7667 parameter \A_SIGNED 1'0
7668 parameter \A_WIDTH 4'1000
7669 parameter \B_SIGNED 1'0
7670 parameter \B_WIDTH 4'1000
7671 parameter \Y_WIDTH 4'1000
7676 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7678 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7680 parameter \A_SIGNED 1'0
7681 parameter \A_WIDTH 4'1000
7682 parameter \B_SIGNED 1'0
7683 parameter \B_WIDTH 4'1000
7684 parameter \Y_WIDTH 4'1000
7690 assign \q 8'00000000
7694 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
7696 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7698 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7700 parameter \A_SIGNED 1'0
7701 parameter \A_WIDTH 4'1000
7702 parameter \Y_WIDTH 4'1000
7707 assign \qn 8'00000000
7711 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7713 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7715 parameter \A_SIGNED 1'0
7716 parameter \A_WIDTH 4'1000
7717 parameter \B_SIGNED 1'0
7718 parameter \B_WIDTH 4'1000
7719 parameter \Y_WIDTH 4'1000
7725 assign \qlq 8'00000000
7730 attribute \generator "nMigen"
7731 attribute \nmigen.hierarchy "top.fumemdeps.dm5.ld_c"
7733 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7734 wire width 1 input 0 \rst
7735 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7736 wire width 1 input 1 \clk
7737 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7738 wire width 8 input 2 \s
7739 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7740 wire width 8 input 3 \r
7741 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7742 wire width 8 output 4 \qlq
7743 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7745 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
7746 wire width 8 \q_int$next
7747 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7749 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7751 parameter \A_SIGNED 1'0
7752 parameter \A_WIDTH 4'1000
7753 parameter \Y_WIDTH 4'1000
7757 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7759 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7761 parameter \A_SIGNED 1'0
7762 parameter \A_WIDTH 4'1000
7763 parameter \B_SIGNED 1'0
7764 parameter \B_WIDTH 4'1000
7765 parameter \Y_WIDTH 4'1000
7770 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7772 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
7774 parameter \A_SIGNED 1'0
7775 parameter \A_WIDTH 4'1000
7776 parameter \B_SIGNED 1'0
7777 parameter \B_WIDTH 4'1000
7778 parameter \Y_WIDTH 4'1000
7784 assign \q_int$next \q_int
7785 assign \q_int$next $5
7786 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
7789 assign \q_int$next 8'00000000
7792 update \q_int 8'00000000
7794 update \q_int \q_int$next
7796 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
7798 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7800 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7802 parameter \A_SIGNED 1'0
7803 parameter \A_WIDTH 4'1000
7804 parameter \Y_WIDTH 4'1000
7808 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7810 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7812 parameter \A_SIGNED 1'0
7813 parameter \A_WIDTH 4'1000
7814 parameter \B_SIGNED 1'0
7815 parameter \B_WIDTH 4'1000
7816 parameter \Y_WIDTH 4'1000
7821 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7823 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
7825 parameter \A_SIGNED 1'0
7826 parameter \A_WIDTH 4'1000
7827 parameter \B_SIGNED 1'0
7828 parameter \B_WIDTH 4'1000
7829 parameter \Y_WIDTH 4'1000
7835 assign \q 8'00000000
7839 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
7841 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7843 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
7845 parameter \A_SIGNED 1'0
7846 parameter \A_WIDTH 4'1000
7847 parameter \Y_WIDTH 4'1000
7852 assign \qn 8'00000000
7856 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7858 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
7860 parameter \A_SIGNED 1'0
7861 parameter \A_WIDTH 4'1000
7862 parameter \B_SIGNED 1'0
7863 parameter \B_WIDTH 4'1000
7864 parameter \Y_WIDTH 4'1000
7870 assign \qlq 8'00000000
7875 attribute \generator "nMigen"
7876 attribute \nmigen.hierarchy "top.fumemdeps.dm5"
7878 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7879 wire width 1 input 0 \rst
7880 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
7881 wire width 1 input 1 \clk
7882 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
7883 wire width 8 output 2 \st_wait_o
7884 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
7885 wire width 8 output 3 \ld_wait_o
7886 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
7887 wire width 8 input 4 \issue_i
7888 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
7889 wire width 8 input 5 \go_st_i
7890 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
7891 wire width 8 input 6 \go_ld_i
7892 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
7893 wire width 8 input 7 \go_die_i
7894 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
7895 wire width 8 input 8 \st_pend_i
7896 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
7897 wire width 8 input 9 \ld_pend_i
7898 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7899 wire width 8 \st_c_s
7900 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7901 wire width 8 \st_c_r
7902 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7903 wire width 8 \st_c_qlq
7909 connect \qlq \st_c_qlq
7911 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
7912 wire width 8 \ld_c_s
7913 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
7914 wire width 8 \ld_c_r
7915 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
7916 wire width 8 \ld_c_qlq
7922 connect \qlq \ld_c_qlq
7924 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
7926 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
7928 parameter \A_SIGNED 1'0
7929 parameter \A_WIDTH 4'1000
7930 parameter \B_SIGNED 1'0
7931 parameter \B_WIDTH 4'1000
7932 parameter \Y_WIDTH 4'1000
7934 connect \B \st_pend_i
7937 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7939 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7941 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7943 parameter \A_SIGNED 1'0
7944 parameter \A_WIDTH 4'1000
7945 parameter \B_SIGNED 1'0
7946 parameter \B_WIDTH 4'1000
7947 parameter \Y_WIDTH 4'1000
7949 connect \B \st_pend_i
7952 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7954 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
7956 parameter \A_SIGNED 1'1
7957 parameter \A_WIDTH 4'1000
7958 parameter \B_SIGNED 1'1
7959 parameter \B_WIDTH 4'1000
7960 parameter \Y_WIDTH 4'1001
7962 connect \B 8'11011111
7967 assign \st_c_s 8'00000000
7969 assign \st_c_s $3 [7:0]
7972 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
7974 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
7976 parameter \A_SIGNED 1'0
7977 parameter \A_WIDTH 4'1000
7978 parameter \B_SIGNED 1'0
7979 parameter \B_WIDTH 4'1000
7980 parameter \Y_WIDTH 4'1000
7982 connect \B \ld_pend_i
7985 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7987 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7989 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
7991 parameter \A_SIGNED 1'0
7992 parameter \A_WIDTH 4'1000
7993 parameter \B_SIGNED 1'0
7994 parameter \B_WIDTH 4'1000
7995 parameter \Y_WIDTH 4'1000
7997 connect \B \ld_pend_i
8000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8002 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8004 parameter \A_SIGNED 1'1
8005 parameter \A_WIDTH 4'1000
8006 parameter \B_SIGNED 1'1
8007 parameter \B_WIDTH 4'1000
8008 parameter \Y_WIDTH 4'1001
8010 connect \B 8'11011111
8015 assign \ld_c_s 8'00000000
8017 assign \ld_c_s $10 [7:0]
8020 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
8022 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
8024 parameter \A_SIGNED 1'0
8025 parameter \A_WIDTH 4'1000
8026 parameter \B_SIGNED 1'0
8027 parameter \B_WIDTH 4'1000
8028 parameter \Y_WIDTH 4'1000
8030 connect \B \go_die_i
8034 assign \ld_c_r 8'11111111
8038 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
8040 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
8042 parameter \A_SIGNED 1'0
8043 parameter \A_WIDTH 4'1000
8044 parameter \B_SIGNED 1'0
8045 parameter \B_WIDTH 4'1000
8046 parameter \Y_WIDTH 4'1000
8048 connect \B \go_die_i
8052 assign \st_c_r 8'11111111
8056 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8058 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8060 parameter \A_SIGNED 1'0
8061 parameter \A_WIDTH 4'1000
8062 parameter \Y_WIDTH 4'1000
8066 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8068 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8070 parameter \A_SIGNED 1'0
8071 parameter \A_WIDTH 4'1000
8072 parameter \B_SIGNED 1'0
8073 parameter \B_WIDTH 4'1000
8074 parameter \Y_WIDTH 4'1000
8075 connect \A \st_c_qlq
8080 assign \st_wait_o 8'00000000
8081 assign \st_wait_o $21
8084 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8086 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8088 parameter \A_SIGNED 1'0
8089 parameter \A_WIDTH 4'1000
8090 parameter \Y_WIDTH 4'1000
8094 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8096 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8098 parameter \A_SIGNED 1'0
8099 parameter \A_WIDTH 4'1000
8100 parameter \B_SIGNED 1'0
8101 parameter \B_WIDTH 4'1000
8102 parameter \Y_WIDTH 4'1000
8103 connect \A \ld_c_qlq
8108 assign \ld_wait_o 8'00000000
8109 assign \ld_wait_o $25
8113 attribute \generator "nMigen"
8114 attribute \nmigen.hierarchy "top.fumemdeps.dm6.st_c"
8116 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8117 wire width 1 input 0 \rst
8118 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8119 wire width 1 input 1 \clk
8120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8121 wire width 8 input 2 \s
8122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8123 wire width 8 input 3 \r
8124 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8125 wire width 8 output 4 \qlq
8126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8128 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8129 wire width 8 \q_int$next
8130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8132 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8134 parameter \A_SIGNED 1'0
8135 parameter \A_WIDTH 4'1000
8136 parameter \Y_WIDTH 4'1000
8140 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8142 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8144 parameter \A_SIGNED 1'0
8145 parameter \A_WIDTH 4'1000
8146 parameter \B_SIGNED 1'0
8147 parameter \B_WIDTH 4'1000
8148 parameter \Y_WIDTH 4'1000
8153 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8155 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8157 parameter \A_SIGNED 1'0
8158 parameter \A_WIDTH 4'1000
8159 parameter \B_SIGNED 1'0
8160 parameter \B_WIDTH 4'1000
8161 parameter \Y_WIDTH 4'1000
8167 assign \q_int$next \q_int
8168 assign \q_int$next $5
8169 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
8172 assign \q_int$next 8'00000000
8175 update \q_int 8'00000000
8177 update \q_int \q_int$next
8179 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
8181 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8183 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8185 parameter \A_SIGNED 1'0
8186 parameter \A_WIDTH 4'1000
8187 parameter \Y_WIDTH 4'1000
8191 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8193 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8195 parameter \A_SIGNED 1'0
8196 parameter \A_WIDTH 4'1000
8197 parameter \B_SIGNED 1'0
8198 parameter \B_WIDTH 4'1000
8199 parameter \Y_WIDTH 4'1000
8204 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8206 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8208 parameter \A_SIGNED 1'0
8209 parameter \A_WIDTH 4'1000
8210 parameter \B_SIGNED 1'0
8211 parameter \B_WIDTH 4'1000
8212 parameter \Y_WIDTH 4'1000
8218 assign \q 8'00000000
8222 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
8224 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8226 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8228 parameter \A_SIGNED 1'0
8229 parameter \A_WIDTH 4'1000
8230 parameter \Y_WIDTH 4'1000
8235 assign \qn 8'00000000
8239 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8241 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8243 parameter \A_SIGNED 1'0
8244 parameter \A_WIDTH 4'1000
8245 parameter \B_SIGNED 1'0
8246 parameter \B_WIDTH 4'1000
8247 parameter \Y_WIDTH 4'1000
8253 assign \qlq 8'00000000
8258 attribute \generator "nMigen"
8259 attribute \nmigen.hierarchy "top.fumemdeps.dm6.ld_c"
8261 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8262 wire width 1 input 0 \rst
8263 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8264 wire width 1 input 1 \clk
8265 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8266 wire width 8 input 2 \s
8267 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8268 wire width 8 input 3 \r
8269 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8270 wire width 8 output 4 \qlq
8271 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8273 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8274 wire width 8 \q_int$next
8275 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8277 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8279 parameter \A_SIGNED 1'0
8280 parameter \A_WIDTH 4'1000
8281 parameter \Y_WIDTH 4'1000
8285 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8287 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8289 parameter \A_SIGNED 1'0
8290 parameter \A_WIDTH 4'1000
8291 parameter \B_SIGNED 1'0
8292 parameter \B_WIDTH 4'1000
8293 parameter \Y_WIDTH 4'1000
8298 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8300 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8302 parameter \A_SIGNED 1'0
8303 parameter \A_WIDTH 4'1000
8304 parameter \B_SIGNED 1'0
8305 parameter \B_WIDTH 4'1000
8306 parameter \Y_WIDTH 4'1000
8312 assign \q_int$next \q_int
8313 assign \q_int$next $5
8314 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
8317 assign \q_int$next 8'00000000
8320 update \q_int 8'00000000
8322 update \q_int \q_int$next
8324 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
8326 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8328 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8330 parameter \A_SIGNED 1'0
8331 parameter \A_WIDTH 4'1000
8332 parameter \Y_WIDTH 4'1000
8336 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8338 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8340 parameter \A_SIGNED 1'0
8341 parameter \A_WIDTH 4'1000
8342 parameter \B_SIGNED 1'0
8343 parameter \B_WIDTH 4'1000
8344 parameter \Y_WIDTH 4'1000
8349 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8351 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8353 parameter \A_SIGNED 1'0
8354 parameter \A_WIDTH 4'1000
8355 parameter \B_SIGNED 1'0
8356 parameter \B_WIDTH 4'1000
8357 parameter \Y_WIDTH 4'1000
8363 assign \q 8'00000000
8367 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
8369 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8371 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8373 parameter \A_SIGNED 1'0
8374 parameter \A_WIDTH 4'1000
8375 parameter \Y_WIDTH 4'1000
8380 assign \qn 8'00000000
8384 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8386 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8388 parameter \A_SIGNED 1'0
8389 parameter \A_WIDTH 4'1000
8390 parameter \B_SIGNED 1'0
8391 parameter \B_WIDTH 4'1000
8392 parameter \Y_WIDTH 4'1000
8398 assign \qlq 8'00000000
8403 attribute \generator "nMigen"
8404 attribute \nmigen.hierarchy "top.fumemdeps.dm6"
8406 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8407 wire width 1 input 0 \rst
8408 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8409 wire width 1 input 1 \clk
8410 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
8411 wire width 8 output 2 \st_wait_o
8412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
8413 wire width 8 output 3 \ld_wait_o
8414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
8415 wire width 8 input 4 \issue_i
8416 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
8417 wire width 8 input 5 \go_st_i
8418 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
8419 wire width 8 input 6 \go_ld_i
8420 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
8421 wire width 8 input 7 \go_die_i
8422 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
8423 wire width 8 input 8 \st_pend_i
8424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
8425 wire width 8 input 9 \ld_pend_i
8426 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8427 wire width 8 \st_c_s
8428 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8429 wire width 8 \st_c_r
8430 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8431 wire width 8 \st_c_qlq
8437 connect \qlq \st_c_qlq
8439 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8440 wire width 8 \ld_c_s
8441 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8442 wire width 8 \ld_c_r
8443 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8444 wire width 8 \ld_c_qlq
8450 connect \qlq \ld_c_qlq
8452 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
8454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
8456 parameter \A_SIGNED 1'0
8457 parameter \A_WIDTH 4'1000
8458 parameter \B_SIGNED 1'0
8459 parameter \B_WIDTH 4'1000
8460 parameter \Y_WIDTH 4'1000
8462 connect \B \st_pend_i
8465 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8467 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8469 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8471 parameter \A_SIGNED 1'0
8472 parameter \A_WIDTH 4'1000
8473 parameter \B_SIGNED 1'0
8474 parameter \B_WIDTH 4'1000
8475 parameter \Y_WIDTH 4'1000
8477 connect \B \st_pend_i
8480 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8484 parameter \A_SIGNED 1'1
8485 parameter \A_WIDTH 4'1000
8486 parameter \B_SIGNED 1'1
8487 parameter \B_WIDTH 4'1000
8488 parameter \Y_WIDTH 4'1001
8490 connect \B 8'10111111
8495 assign \st_c_s 8'00000000
8497 assign \st_c_s $3 [7:0]
8500 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
8502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
8504 parameter \A_SIGNED 1'0
8505 parameter \A_WIDTH 4'1000
8506 parameter \B_SIGNED 1'0
8507 parameter \B_WIDTH 4'1000
8508 parameter \Y_WIDTH 4'1000
8510 connect \B \ld_pend_i
8513 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8515 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8517 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8519 parameter \A_SIGNED 1'0
8520 parameter \A_WIDTH 4'1000
8521 parameter \B_SIGNED 1'0
8522 parameter \B_WIDTH 4'1000
8523 parameter \Y_WIDTH 4'1000
8525 connect \B \ld_pend_i
8528 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8530 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
8532 parameter \A_SIGNED 1'1
8533 parameter \A_WIDTH 4'1000
8534 parameter \B_SIGNED 1'1
8535 parameter \B_WIDTH 4'1000
8536 parameter \Y_WIDTH 4'1001
8538 connect \B 8'10111111
8543 assign \ld_c_s 8'00000000
8545 assign \ld_c_s $10 [7:0]
8548 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
8550 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
8552 parameter \A_SIGNED 1'0
8553 parameter \A_WIDTH 4'1000
8554 parameter \B_SIGNED 1'0
8555 parameter \B_WIDTH 4'1000
8556 parameter \Y_WIDTH 4'1000
8558 connect \B \go_die_i
8562 assign \ld_c_r 8'11111111
8566 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
8568 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
8570 parameter \A_SIGNED 1'0
8571 parameter \A_WIDTH 4'1000
8572 parameter \B_SIGNED 1'0
8573 parameter \B_WIDTH 4'1000
8574 parameter \Y_WIDTH 4'1000
8576 connect \B \go_die_i
8580 assign \st_c_r 8'11111111
8584 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8586 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8588 parameter \A_SIGNED 1'0
8589 parameter \A_WIDTH 4'1000
8590 parameter \Y_WIDTH 4'1000
8594 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8596 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
8598 parameter \A_SIGNED 1'0
8599 parameter \A_WIDTH 4'1000
8600 parameter \B_SIGNED 1'0
8601 parameter \B_WIDTH 4'1000
8602 parameter \Y_WIDTH 4'1000
8603 connect \A \st_c_qlq
8608 assign \st_wait_o 8'00000000
8609 assign \st_wait_o $21
8612 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8614 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8616 parameter \A_SIGNED 1'0
8617 parameter \A_WIDTH 4'1000
8618 parameter \Y_WIDTH 4'1000
8622 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8624 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
8626 parameter \A_SIGNED 1'0
8627 parameter \A_WIDTH 4'1000
8628 parameter \B_SIGNED 1'0
8629 parameter \B_WIDTH 4'1000
8630 parameter \Y_WIDTH 4'1000
8631 connect \A \ld_c_qlq
8636 assign \ld_wait_o 8'00000000
8637 assign \ld_wait_o $25
8641 attribute \generator "nMigen"
8642 attribute \nmigen.hierarchy "top.fumemdeps.dm7.st_c"
8644 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8645 wire width 1 input 0 \rst
8646 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8647 wire width 1 input 1 \clk
8648 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8649 wire width 8 input 2 \s
8650 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8651 wire width 8 input 3 \r
8652 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8653 wire width 8 output 4 \qlq
8654 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8656 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8657 wire width 8 \q_int$next
8658 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8660 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8662 parameter \A_SIGNED 1'0
8663 parameter \A_WIDTH 4'1000
8664 parameter \Y_WIDTH 4'1000
8668 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8670 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8672 parameter \A_SIGNED 1'0
8673 parameter \A_WIDTH 4'1000
8674 parameter \B_SIGNED 1'0
8675 parameter \B_WIDTH 4'1000
8676 parameter \Y_WIDTH 4'1000
8681 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8683 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8685 parameter \A_SIGNED 1'0
8686 parameter \A_WIDTH 4'1000
8687 parameter \B_SIGNED 1'0
8688 parameter \B_WIDTH 4'1000
8689 parameter \Y_WIDTH 4'1000
8695 assign \q_int$next \q_int
8696 assign \q_int$next $5
8697 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
8700 assign \q_int$next 8'00000000
8703 update \q_int 8'00000000
8705 update \q_int \q_int$next
8707 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
8709 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8711 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8713 parameter \A_SIGNED 1'0
8714 parameter \A_WIDTH 4'1000
8715 parameter \Y_WIDTH 4'1000
8719 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8721 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8723 parameter \A_SIGNED 1'0
8724 parameter \A_WIDTH 4'1000
8725 parameter \B_SIGNED 1'0
8726 parameter \B_WIDTH 4'1000
8727 parameter \Y_WIDTH 4'1000
8732 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8734 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8736 parameter \A_SIGNED 1'0
8737 parameter \A_WIDTH 4'1000
8738 parameter \B_SIGNED 1'0
8739 parameter \B_WIDTH 4'1000
8740 parameter \Y_WIDTH 4'1000
8746 assign \q 8'00000000
8750 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
8752 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8754 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8756 parameter \A_SIGNED 1'0
8757 parameter \A_WIDTH 4'1000
8758 parameter \Y_WIDTH 4'1000
8763 assign \qn 8'00000000
8767 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8769 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8771 parameter \A_SIGNED 1'0
8772 parameter \A_WIDTH 4'1000
8773 parameter \B_SIGNED 1'0
8774 parameter \B_WIDTH 4'1000
8775 parameter \Y_WIDTH 4'1000
8781 assign \qlq 8'00000000
8786 attribute \generator "nMigen"
8787 attribute \nmigen.hierarchy "top.fumemdeps.dm7.ld_c"
8789 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8790 wire width 1 input 0 \rst
8791 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8792 wire width 1 input 1 \clk
8793 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8794 wire width 8 input 2 \s
8795 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8796 wire width 8 input 3 \r
8797 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8798 wire width 8 output 4 \qlq
8799 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8801 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
8802 wire width 8 \q_int$next
8803 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8805 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8807 parameter \A_SIGNED 1'0
8808 parameter \A_WIDTH 4'1000
8809 parameter \Y_WIDTH 4'1000
8813 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8815 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8817 parameter \A_SIGNED 1'0
8818 parameter \A_WIDTH 4'1000
8819 parameter \B_SIGNED 1'0
8820 parameter \B_WIDTH 4'1000
8821 parameter \Y_WIDTH 4'1000
8826 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8828 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
8830 parameter \A_SIGNED 1'0
8831 parameter \A_WIDTH 4'1000
8832 parameter \B_SIGNED 1'0
8833 parameter \B_WIDTH 4'1000
8834 parameter \Y_WIDTH 4'1000
8840 assign \q_int$next \q_int
8841 assign \q_int$next $5
8842 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518"
8845 assign \q_int$next 8'00000000
8848 update \q_int 8'00000000
8850 update \q_int \q_int$next
8852 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
8854 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8856 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8858 parameter \A_SIGNED 1'0
8859 parameter \A_WIDTH 4'1000
8860 parameter \Y_WIDTH 4'1000
8864 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8866 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8868 parameter \A_SIGNED 1'0
8869 parameter \A_WIDTH 4'1000
8870 parameter \B_SIGNED 1'0
8871 parameter \B_WIDTH 4'1000
8872 parameter \Y_WIDTH 4'1000
8877 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8879 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
8881 parameter \A_SIGNED 1'0
8882 parameter \A_WIDTH 4'1000
8883 parameter \B_SIGNED 1'0
8884 parameter \B_WIDTH 4'1000
8885 parameter \Y_WIDTH 4'1000
8891 assign \q 8'00000000
8895 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
8897 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8899 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
8901 parameter \A_SIGNED 1'0
8902 parameter \A_WIDTH 4'1000
8903 parameter \Y_WIDTH 4'1000
8908 assign \qn 8'00000000
8912 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8914 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
8916 parameter \A_SIGNED 1'0
8917 parameter \A_WIDTH 4'1000
8918 parameter \B_SIGNED 1'0
8919 parameter \B_WIDTH 4'1000
8920 parameter \Y_WIDTH 4'1000
8926 assign \qlq 8'00000000
8931 attribute \generator "nMigen"
8932 attribute \nmigen.hierarchy "top.fumemdeps.dm7"
8934 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8935 wire width 1 input 0 \rst
8936 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
8937 wire width 1 input 1 \clk
8938 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
8939 wire width 8 output 2 \st_wait_o
8940 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
8941 wire width 8 output 3 \ld_wait_o
8942 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
8943 wire width 8 input 4 \issue_i
8944 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
8945 wire width 8 input 5 \go_st_i
8946 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
8947 wire width 8 input 6 \go_ld_i
8948 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
8949 wire width 8 input 7 \go_die_i
8950 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
8951 wire width 8 input 8 \st_pend_i
8952 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
8953 wire width 8 input 9 \ld_pend_i
8954 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8955 wire width 8 \st_c_s
8956 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8957 wire width 8 \st_c_r
8958 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8959 wire width 8 \st_c_qlq
8965 connect \qlq \st_c_qlq
8967 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
8968 wire width 8 \ld_c_s
8969 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
8970 wire width 8 \ld_c_r
8971 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
8972 wire width 8 \ld_c_qlq
8978 connect \qlq \ld_c_qlq
8980 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
8982 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:32"
8984 parameter \A_SIGNED 1'0
8985 parameter \A_WIDTH 4'1000
8986 parameter \B_SIGNED 1'0
8987 parameter \B_WIDTH 4'1000
8988 parameter \Y_WIDTH 4'1000
8990 connect \B \st_pend_i
8993 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8995 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8997 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
8999 parameter \A_SIGNED 1'0
9000 parameter \A_WIDTH 4'1000
9001 parameter \B_SIGNED 1'0
9002 parameter \B_WIDTH 4'1000
9003 parameter \Y_WIDTH 4'1000
9005 connect \B \st_pend_i
9008 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
9010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:40"
9012 parameter \A_SIGNED 1'1
9013 parameter \A_WIDTH 4'1000
9014 parameter \B_SIGNED 1'1
9015 parameter \B_WIDTH 4'1000
9016 parameter \Y_WIDTH 4'1001
9018 connect \B 8'01111111
9023 assign \st_c_s 8'00000000
9025 assign \st_c_s $3 [7:0]
9028 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
9030 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:33"
9032 parameter \A_SIGNED 1'0
9033 parameter \A_WIDTH 4'1000
9034 parameter \B_SIGNED 1'0
9035 parameter \B_WIDTH 4'1000
9036 parameter \Y_WIDTH 4'1000
9038 connect \B \ld_pend_i
9041 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9043 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9045 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9047 parameter \A_SIGNED 1'0
9048 parameter \A_WIDTH 4'1000
9049 parameter \B_SIGNED 1'0
9050 parameter \B_WIDTH 4'1000
9051 parameter \Y_WIDTH 4'1000
9053 connect \B \ld_pend_i
9056 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9058 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:41"
9060 parameter \A_SIGNED 1'1
9061 parameter \A_WIDTH 4'1000
9062 parameter \B_SIGNED 1'1
9063 parameter \B_WIDTH 4'1000
9064 parameter \Y_WIDTH 4'1001
9066 connect \B 8'01111111
9071 assign \ld_c_s 8'00000000
9073 assign \ld_c_s $10 [7:0]
9076 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
9078 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:36"
9080 parameter \A_SIGNED 1'0
9081 parameter \A_WIDTH 4'1000
9082 parameter \B_SIGNED 1'0
9083 parameter \B_WIDTH 4'1000
9084 parameter \Y_WIDTH 4'1000
9086 connect \B \go_die_i
9090 assign \ld_c_r 8'11111111
9094 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
9096 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:37"
9098 parameter \A_SIGNED 1'0
9099 parameter \A_WIDTH 4'1000
9100 parameter \B_SIGNED 1'0
9101 parameter \B_WIDTH 4'1000
9102 parameter \Y_WIDTH 4'1000
9104 connect \B \go_die_i
9108 assign \st_c_r 8'11111111
9112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
9114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
9116 parameter \A_SIGNED 1'0
9117 parameter \A_WIDTH 4'1000
9118 parameter \Y_WIDTH 4'1000
9122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
9124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:44"
9126 parameter \A_SIGNED 1'0
9127 parameter \A_WIDTH 4'1000
9128 parameter \B_SIGNED 1'0
9129 parameter \B_WIDTH 4'1000
9130 parameter \Y_WIDTH 4'1000
9131 connect \A \st_c_qlq
9136 assign \st_wait_o 8'00000000
9137 assign \st_wait_o $21
9140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
9142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
9144 parameter \A_SIGNED 1'0
9145 parameter \A_WIDTH 4'1000
9146 parameter \Y_WIDTH 4'1000
9150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
9152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:45"
9154 parameter \A_SIGNED 1'0
9155 parameter \A_WIDTH 4'1000
9156 parameter \B_SIGNED 1'0
9157 parameter \B_WIDTH 4'1000
9158 parameter \Y_WIDTH 4'1000
9159 connect \A \ld_c_qlq
9164 assign \ld_wait_o 8'00000000
9165 assign \ld_wait_o $25
9169 attribute \generator "nMigen"
9170 attribute \nmigen.hierarchy "top.fumemdeps.fur_x0"
9172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9173 wire width 1 output 0 \storable_o
9174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9175 wire width 1 output 1 \loadable_o
9176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9177 wire width 8 input 2 \st_pend_i
9178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9179 wire width 8 input 3 \ld_pend_i
9180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9185 cell $reduce_bool $3
9186 parameter \A_SIGNED 1'0
9187 parameter \A_WIDTH 4'1000
9188 parameter \Y_WIDTH 1'1
9189 connect \A \ld_pend_i
9192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9194 parameter \A_SIGNED 1'0
9195 parameter \A_WIDTH 1'1
9196 parameter \Y_WIDTH 1'1
9201 assign \storable_o 1'0
9202 assign \storable_o $1
9205 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9207 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9209 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9210 cell $reduce_bool $7
9211 parameter \A_SIGNED 1'0
9212 parameter \A_WIDTH 4'1000
9213 parameter \Y_WIDTH 1'1
9214 connect \A \st_pend_i
9217 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9219 parameter \A_SIGNED 1'0
9220 parameter \A_WIDTH 1'1
9221 parameter \Y_WIDTH 1'1
9226 assign \loadable_o 1'0
9227 assign \loadable_o $5
9231 attribute \generator "nMigen"
9232 attribute \nmigen.hierarchy "top.fumemdeps.fur_x1"
9234 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9235 wire width 1 output 0 \storable_o
9236 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9237 wire width 1 output 1 \loadable_o
9238 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9239 wire width 8 input 2 \st_pend_i
9240 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9241 wire width 8 input 3 \ld_pend_i
9242 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9244 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9246 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9247 cell $reduce_bool $3
9248 parameter \A_SIGNED 1'0
9249 parameter \A_WIDTH 4'1000
9250 parameter \Y_WIDTH 1'1
9251 connect \A \ld_pend_i
9254 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9256 parameter \A_SIGNED 1'0
9257 parameter \A_WIDTH 1'1
9258 parameter \Y_WIDTH 1'1
9263 assign \storable_o 1'0
9264 assign \storable_o $1
9267 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9269 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9271 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9272 cell $reduce_bool $7
9273 parameter \A_SIGNED 1'0
9274 parameter \A_WIDTH 4'1000
9275 parameter \Y_WIDTH 1'1
9276 connect \A \st_pend_i
9279 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9281 parameter \A_SIGNED 1'0
9282 parameter \A_WIDTH 1'1
9283 parameter \Y_WIDTH 1'1
9288 assign \loadable_o 1'0
9289 assign \loadable_o $5
9293 attribute \generator "nMigen"
9294 attribute \nmigen.hierarchy "top.fumemdeps.fur_x2"
9296 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9297 wire width 1 output 0 \storable_o
9298 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9299 wire width 1 output 1 \loadable_o
9300 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9301 wire width 8 input 2 \st_pend_i
9302 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9303 wire width 8 input 3 \ld_pend_i
9304 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9306 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9308 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9309 cell $reduce_bool $3
9310 parameter \A_SIGNED 1'0
9311 parameter \A_WIDTH 4'1000
9312 parameter \Y_WIDTH 1'1
9313 connect \A \ld_pend_i
9316 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9318 parameter \A_SIGNED 1'0
9319 parameter \A_WIDTH 1'1
9320 parameter \Y_WIDTH 1'1
9325 assign \storable_o 1'0
9326 assign \storable_o $1
9329 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9331 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9333 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9334 cell $reduce_bool $7
9335 parameter \A_SIGNED 1'0
9336 parameter \A_WIDTH 4'1000
9337 parameter \Y_WIDTH 1'1
9338 connect \A \st_pend_i
9341 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9343 parameter \A_SIGNED 1'0
9344 parameter \A_WIDTH 1'1
9345 parameter \Y_WIDTH 1'1
9350 assign \loadable_o 1'0
9351 assign \loadable_o $5
9355 attribute \generator "nMigen"
9356 attribute \nmigen.hierarchy "top.fumemdeps.fur_x3"
9358 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9359 wire width 1 output 0 \storable_o
9360 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9361 wire width 1 output 1 \loadable_o
9362 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9363 wire width 8 input 2 \st_pend_i
9364 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9365 wire width 8 input 3 \ld_pend_i
9366 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9368 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9370 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9371 cell $reduce_bool $3
9372 parameter \A_SIGNED 1'0
9373 parameter \A_WIDTH 4'1000
9374 parameter \Y_WIDTH 1'1
9375 connect \A \ld_pend_i
9378 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9380 parameter \A_SIGNED 1'0
9381 parameter \A_WIDTH 1'1
9382 parameter \Y_WIDTH 1'1
9387 assign \storable_o 1'0
9388 assign \storable_o $1
9391 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9395 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9396 cell $reduce_bool $7
9397 parameter \A_SIGNED 1'0
9398 parameter \A_WIDTH 4'1000
9399 parameter \Y_WIDTH 1'1
9400 connect \A \st_pend_i
9403 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9405 parameter \A_SIGNED 1'0
9406 parameter \A_WIDTH 1'1
9407 parameter \Y_WIDTH 1'1
9412 assign \loadable_o 1'0
9413 assign \loadable_o $5
9417 attribute \generator "nMigen"
9418 attribute \nmigen.hierarchy "top.fumemdeps.fur_x4"
9420 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9421 wire width 1 output 0 \storable_o
9422 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9423 wire width 1 output 1 \loadable_o
9424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9425 wire width 8 input 2 \st_pend_i
9426 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9427 wire width 8 input 3 \ld_pend_i
9428 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9430 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9432 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9433 cell $reduce_bool $3
9434 parameter \A_SIGNED 1'0
9435 parameter \A_WIDTH 4'1000
9436 parameter \Y_WIDTH 1'1
9437 connect \A \ld_pend_i
9440 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9442 parameter \A_SIGNED 1'0
9443 parameter \A_WIDTH 1'1
9444 parameter \Y_WIDTH 1'1
9449 assign \storable_o 1'0
9450 assign \storable_o $1
9453 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9455 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9457 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9458 cell $reduce_bool $7
9459 parameter \A_SIGNED 1'0
9460 parameter \A_WIDTH 4'1000
9461 parameter \Y_WIDTH 1'1
9462 connect \A \st_pend_i
9465 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9467 parameter \A_SIGNED 1'0
9468 parameter \A_WIDTH 1'1
9469 parameter \Y_WIDTH 1'1
9474 assign \loadable_o 1'0
9475 assign \loadable_o $5
9479 attribute \generator "nMigen"
9480 attribute \nmigen.hierarchy "top.fumemdeps.fur_x5"
9482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9483 wire width 1 output 0 \storable_o
9484 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9485 wire width 1 output 1 \loadable_o
9486 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9487 wire width 8 input 2 \st_pend_i
9488 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9489 wire width 8 input 3 \ld_pend_i
9490 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9492 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9494 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9495 cell $reduce_bool $3
9496 parameter \A_SIGNED 1'0
9497 parameter \A_WIDTH 4'1000
9498 parameter \Y_WIDTH 1'1
9499 connect \A \ld_pend_i
9502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9504 parameter \A_SIGNED 1'0
9505 parameter \A_WIDTH 1'1
9506 parameter \Y_WIDTH 1'1
9511 assign \storable_o 1'0
9512 assign \storable_o $1
9515 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9517 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9519 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9520 cell $reduce_bool $7
9521 parameter \A_SIGNED 1'0
9522 parameter \A_WIDTH 4'1000
9523 parameter \Y_WIDTH 1'1
9524 connect \A \st_pend_i
9527 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9529 parameter \A_SIGNED 1'0
9530 parameter \A_WIDTH 1'1
9531 parameter \Y_WIDTH 1'1
9536 assign \loadable_o 1'0
9537 assign \loadable_o $5
9541 attribute \generator "nMigen"
9542 attribute \nmigen.hierarchy "top.fumemdeps.fur_x6"
9544 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9545 wire width 1 output 0 \storable_o
9546 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9547 wire width 1 output 1 \loadable_o
9548 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9549 wire width 8 input 2 \st_pend_i
9550 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9551 wire width 8 input 3 \ld_pend_i
9552 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9554 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9556 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9557 cell $reduce_bool $3
9558 parameter \A_SIGNED 1'0
9559 parameter \A_WIDTH 4'1000
9560 parameter \Y_WIDTH 1'1
9561 connect \A \ld_pend_i
9564 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9566 parameter \A_SIGNED 1'0
9567 parameter \A_WIDTH 1'1
9568 parameter \Y_WIDTH 1'1
9573 assign \storable_o 1'0
9574 assign \storable_o $1
9577 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9579 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9581 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9582 cell $reduce_bool $7
9583 parameter \A_SIGNED 1'0
9584 parameter \A_WIDTH 4'1000
9585 parameter \Y_WIDTH 1'1
9586 connect \A \st_pend_i
9589 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9591 parameter \A_SIGNED 1'0
9592 parameter \A_WIDTH 1'1
9593 parameter \Y_WIDTH 1'1
9598 assign \loadable_o 1'0
9599 assign \loadable_o $5
9603 attribute \generator "nMigen"
9604 attribute \nmigen.hierarchy "top.fumemdeps.fur_x7"
9606 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9607 wire width 1 output 0 \storable_o
9608 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9609 wire width 1 output 1 \loadable_o
9610 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9611 wire width 8 input 2 \st_pend_i
9612 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9613 wire width 8 input 3 \ld_pend_i
9614 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9616 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9618 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9619 cell $reduce_bool $3
9620 parameter \A_SIGNED 1'0
9621 parameter \A_WIDTH 4'1000
9622 parameter \Y_WIDTH 1'1
9623 connect \A \ld_pend_i
9626 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:20"
9628 parameter \A_SIGNED 1'0
9629 parameter \A_WIDTH 1'1
9630 parameter \Y_WIDTH 1'1
9635 assign \storable_o 1'0
9636 assign \storable_o $1
9639 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9641 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9643 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9644 cell $reduce_bool $7
9645 parameter \A_SIGNED 1'0
9646 parameter \A_WIDTH 4'1000
9647 parameter \Y_WIDTH 1'1
9648 connect \A \st_pend_i
9651 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:23"
9653 parameter \A_SIGNED 1'0
9654 parameter \A_WIDTH 1'1
9655 parameter \Y_WIDTH 1'1
9660 assign \loadable_o 1'0
9661 assign \loadable_o $5
9665 attribute \generator "nMigen"
9666 attribute \nmigen.hierarchy "top.fumemdeps"
9668 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:30"
9669 wire width 8 output 0 \storable_o
9670 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:31"
9671 wire width 8 output 1 \loadable_o
9672 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:22"
9673 wire width 8 input 2 \ld_pend_i
9674 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:21"
9675 wire width 8 input 3 \st_pend_i
9676 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:26"
9677 wire width 8 input 4 \go_st_i
9678 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:25"
9679 wire width 8 input 5 \go_ld_i
9680 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:27"
9681 wire width 8 input 6 \go_die_i
9682 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:23"
9683 wire width 8 input 7 \issue_i
9684 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
9685 wire width 1 input 8 \rst
9686 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
9687 wire width 1 input 9 \clk
9688 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9689 wire width 8 \dm0_st_wait_o
9690 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9691 wire width 8 \dm0_ld_wait_o
9692 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9693 wire width 8 \dm0_issue_i
9694 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9695 wire width 8 \dm0_go_st_i
9696 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9697 wire width 8 \dm0_go_ld_i
9698 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9699 wire width 8 \dm0_go_die_i
9700 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9701 wire width 8 \dm0_st_pend_i
9702 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9703 wire width 8 \dm0_ld_pend_i
9707 connect \st_wait_o \dm0_st_wait_o
9708 connect \ld_wait_o \dm0_ld_wait_o
9709 connect \issue_i \dm0_issue_i
9710 connect \go_st_i \dm0_go_st_i
9711 connect \go_ld_i \dm0_go_ld_i
9712 connect \go_die_i \dm0_go_die_i
9713 connect \st_pend_i \dm0_st_pend_i
9714 connect \ld_pend_i \dm0_ld_pend_i
9716 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9717 wire width 8 \dm1_st_wait_o
9718 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9719 wire width 8 \dm1_ld_wait_o
9720 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9721 wire width 8 \dm1_issue_i
9722 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9723 wire width 8 \dm1_go_st_i
9724 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9725 wire width 8 \dm1_go_ld_i
9726 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9727 wire width 8 \dm1_go_die_i
9728 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9729 wire width 8 \dm1_st_pend_i
9730 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9731 wire width 8 \dm1_ld_pend_i
9735 connect \st_wait_o \dm1_st_wait_o
9736 connect \ld_wait_o \dm1_ld_wait_o
9737 connect \issue_i \dm1_issue_i
9738 connect \go_st_i \dm1_go_st_i
9739 connect \go_ld_i \dm1_go_ld_i
9740 connect \go_die_i \dm1_go_die_i
9741 connect \st_pend_i \dm1_st_pend_i
9742 connect \ld_pend_i \dm1_ld_pend_i
9744 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9745 wire width 8 \dm2_st_wait_o
9746 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9747 wire width 8 \dm2_ld_wait_o
9748 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9749 wire width 8 \dm2_issue_i
9750 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9751 wire width 8 \dm2_go_st_i
9752 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9753 wire width 8 \dm2_go_ld_i
9754 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9755 wire width 8 \dm2_go_die_i
9756 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9757 wire width 8 \dm2_st_pend_i
9758 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9759 wire width 8 \dm2_ld_pend_i
9763 connect \st_wait_o \dm2_st_wait_o
9764 connect \ld_wait_o \dm2_ld_wait_o
9765 connect \issue_i \dm2_issue_i
9766 connect \go_st_i \dm2_go_st_i
9767 connect \go_ld_i \dm2_go_ld_i
9768 connect \go_die_i \dm2_go_die_i
9769 connect \st_pend_i \dm2_st_pend_i
9770 connect \ld_pend_i \dm2_ld_pend_i
9772 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9773 wire width 8 \dm3_st_wait_o
9774 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9775 wire width 8 \dm3_ld_wait_o
9776 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9777 wire width 8 \dm3_issue_i
9778 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9779 wire width 8 \dm3_go_st_i
9780 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9781 wire width 8 \dm3_go_ld_i
9782 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9783 wire width 8 \dm3_go_die_i
9784 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9785 wire width 8 \dm3_st_pend_i
9786 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9787 wire width 8 \dm3_ld_pend_i
9791 connect \st_wait_o \dm3_st_wait_o
9792 connect \ld_wait_o \dm3_ld_wait_o
9793 connect \issue_i \dm3_issue_i
9794 connect \go_st_i \dm3_go_st_i
9795 connect \go_ld_i \dm3_go_ld_i
9796 connect \go_die_i \dm3_go_die_i
9797 connect \st_pend_i \dm3_st_pend_i
9798 connect \ld_pend_i \dm3_ld_pend_i
9800 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9801 wire width 8 \dm4_st_wait_o
9802 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9803 wire width 8 \dm4_ld_wait_o
9804 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9805 wire width 8 \dm4_issue_i
9806 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9807 wire width 8 \dm4_go_st_i
9808 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9809 wire width 8 \dm4_go_ld_i
9810 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9811 wire width 8 \dm4_go_die_i
9812 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9813 wire width 8 \dm4_st_pend_i
9814 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9815 wire width 8 \dm4_ld_pend_i
9819 connect \st_wait_o \dm4_st_wait_o
9820 connect \ld_wait_o \dm4_ld_wait_o
9821 connect \issue_i \dm4_issue_i
9822 connect \go_st_i \dm4_go_st_i
9823 connect \go_ld_i \dm4_go_ld_i
9824 connect \go_die_i \dm4_go_die_i
9825 connect \st_pend_i \dm4_st_pend_i
9826 connect \ld_pend_i \dm4_ld_pend_i
9828 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9829 wire width 8 \dm5_st_wait_o
9830 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9831 wire width 8 \dm5_ld_wait_o
9832 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9833 wire width 8 \dm5_issue_i
9834 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9835 wire width 8 \dm5_go_st_i
9836 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9837 wire width 8 \dm5_go_ld_i
9838 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9839 wire width 8 \dm5_go_die_i
9840 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9841 wire width 8 \dm5_st_pend_i
9842 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9843 wire width 8 \dm5_ld_pend_i
9847 connect \st_wait_o \dm5_st_wait_o
9848 connect \ld_wait_o \dm5_ld_wait_o
9849 connect \issue_i \dm5_issue_i
9850 connect \go_st_i \dm5_go_st_i
9851 connect \go_ld_i \dm5_go_ld_i
9852 connect \go_die_i \dm5_go_die_i
9853 connect \st_pend_i \dm5_st_pend_i
9854 connect \ld_pend_i \dm5_ld_pend_i
9856 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9857 wire width 8 \dm6_st_wait_o
9858 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9859 wire width 8 \dm6_ld_wait_o
9860 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9861 wire width 8 \dm6_issue_i
9862 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9863 wire width 8 \dm6_go_st_i
9864 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9865 wire width 8 \dm6_go_ld_i
9866 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9867 wire width 8 \dm6_go_die_i
9868 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9869 wire width 8 \dm6_st_pend_i
9870 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9871 wire width 8 \dm6_ld_pend_i
9875 connect \st_wait_o \dm6_st_wait_o
9876 connect \ld_wait_o \dm6_ld_wait_o
9877 connect \issue_i \dm6_issue_i
9878 connect \go_st_i \dm6_go_st_i
9879 connect \go_ld_i \dm6_go_ld_i
9880 connect \go_die_i \dm6_go_die_i
9881 connect \st_pend_i \dm6_st_pend_i
9882 connect \ld_pend_i \dm6_ld_pend_i
9884 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:23"
9885 wire width 8 \dm7_st_wait_o
9886 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:24"
9887 wire width 8 \dm7_ld_wait_o
9888 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:16"
9889 wire width 8 \dm7_issue_i
9890 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:19"
9891 wire width 8 \dm7_go_st_i
9892 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:18"
9893 wire width 8 \dm7_go_ld_i
9894 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:20"
9895 wire width 8 \dm7_go_die_i
9896 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:14"
9897 wire width 8 \dm7_st_pend_i
9898 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fumem_dep_cell.py:15"
9899 wire width 8 \dm7_ld_pend_i
9903 connect \st_wait_o \dm7_st_wait_o
9904 connect \ld_wait_o \dm7_ld_wait_o
9905 connect \issue_i \dm7_issue_i
9906 connect \go_st_i \dm7_go_st_i
9907 connect \go_ld_i \dm7_go_ld_i
9908 connect \go_die_i \dm7_go_die_i
9909 connect \st_pend_i \dm7_st_pend_i
9910 connect \ld_pend_i \dm7_ld_pend_i
9912 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9913 wire width 1 \fur_x0_storable_o
9914 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9915 wire width 1 \fur_x0_loadable_o
9916 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9917 wire width 8 \fur_x0_st_pend_i
9918 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9919 wire width 8 \fur_x0_ld_pend_i
9920 cell \fur_x0 \fur_x0
9921 connect \storable_o \fur_x0_storable_o
9922 connect \loadable_o \fur_x0_loadable_o
9923 connect \st_pend_i \fur_x0_st_pend_i
9924 connect \ld_pend_i \fur_x0_ld_pend_i
9926 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9927 wire width 1 \fur_x1_storable_o
9928 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9929 wire width 1 \fur_x1_loadable_o
9930 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9931 wire width 8 \fur_x1_st_pend_i
9932 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9933 wire width 8 \fur_x1_ld_pend_i
9934 cell \fur_x1 \fur_x1
9935 connect \storable_o \fur_x1_storable_o
9936 connect \loadable_o \fur_x1_loadable_o
9937 connect \st_pend_i \fur_x1_st_pend_i
9938 connect \ld_pend_i \fur_x1_ld_pend_i
9940 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9941 wire width 1 \fur_x2_storable_o
9942 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9943 wire width 1 \fur_x2_loadable_o
9944 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9945 wire width 8 \fur_x2_st_pend_i
9946 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9947 wire width 8 \fur_x2_ld_pend_i
9948 cell \fur_x2 \fur_x2
9949 connect \storable_o \fur_x2_storable_o
9950 connect \loadable_o \fur_x2_loadable_o
9951 connect \st_pend_i \fur_x2_st_pend_i
9952 connect \ld_pend_i \fur_x2_ld_pend_i
9954 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9955 wire width 1 \fur_x3_storable_o
9956 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9957 wire width 1 \fur_x3_loadable_o
9958 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9959 wire width 8 \fur_x3_st_pend_i
9960 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9961 wire width 8 \fur_x3_ld_pend_i
9962 cell \fur_x3 \fur_x3
9963 connect \storable_o \fur_x3_storable_o
9964 connect \loadable_o \fur_x3_loadable_o
9965 connect \st_pend_i \fur_x3_st_pend_i
9966 connect \ld_pend_i \fur_x3_ld_pend_i
9968 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9969 wire width 1 \fur_x4_storable_o
9970 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9971 wire width 1 \fur_x4_loadable_o
9972 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9973 wire width 8 \fur_x4_st_pend_i
9974 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9975 wire width 8 \fur_x4_ld_pend_i
9976 cell \fur_x4 \fur_x4
9977 connect \storable_o \fur_x4_storable_o
9978 connect \loadable_o \fur_x4_loadable_o
9979 connect \st_pend_i \fur_x4_st_pend_i
9980 connect \ld_pend_i \fur_x4_ld_pend_i
9982 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9983 wire width 1 \fur_x5_storable_o
9984 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9985 wire width 1 \fur_x5_loadable_o
9986 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
9987 wire width 8 \fur_x5_st_pend_i
9988 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
9989 wire width 8 \fur_x5_ld_pend_i
9990 cell \fur_x5 \fur_x5
9991 connect \storable_o \fur_x5_storable_o
9992 connect \loadable_o \fur_x5_loadable_o
9993 connect \st_pend_i \fur_x5_st_pend_i
9994 connect \ld_pend_i \fur_x5_ld_pend_i
9996 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
9997 wire width 1 \fur_x6_storable_o
9998 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
9999 wire width 1 \fur_x6_loadable_o
10000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
10001 wire width 8 \fur_x6_st_pend_i
10002 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
10003 wire width 8 \fur_x6_ld_pend_i
10004 cell \fur_x6 \fur_x6
10005 connect \storable_o \fur_x6_storable_o
10006 connect \loadable_o \fur_x6_loadable_o
10007 connect \st_pend_i \fur_x6_st_pend_i
10008 connect \ld_pend_i \fur_x6_ld_pend_i
10010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:13"
10011 wire width 1 \fur_x7_storable_o
10012 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:14"
10013 wire width 1 \fur_x7_loadable_o
10014 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:10"
10015 wire width 8 \fur_x7_st_pend_i
10016 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_picker_vec.py:11"
10017 wire width 8 \fur_x7_ld_pend_i
10018 cell \fur_x7 \fur_x7
10019 connect \storable_o \fur_x7_storable_o
10020 connect \loadable_o \fur_x7_loadable_o
10021 connect \st_pend_i \fur_x7_st_pend_i
10022 connect \ld_pend_i \fur_x7_ld_pend_i
10025 assign \storable_o 8'00000000
10026 assign \storable_o { \fur_x7_storable_o \fur_x6_storable_o \fur_x5_storable_o \fur_x4_storable_o \fur_x3_storable_o \fur_x2_storable_o \fur_x1_storable_o \fur_x0_storable_o }
10030 assign \loadable_o 8'00000000
10031 assign \loadable_o { \fur_x7_loadable_o \fur_x6_loadable_o \fur_x5_loadable_o \fur_x4_loadable_o \fur_x3_loadable_o \fur_x2_loadable_o \fur_x1_loadable_o \fur_x0_loadable_o }
10035 assign \fur_x0_st_pend_i 8'00000000
10036 assign \fur_x0_st_pend_i \dm0_st_wait_o
10040 assign \fur_x0_ld_pend_i 8'00000000
10041 assign \fur_x0_ld_pend_i \dm0_ld_wait_o
10045 assign \fur_x1_st_pend_i 8'00000000
10046 assign \fur_x1_st_pend_i \dm1_st_wait_o
10050 assign \fur_x1_ld_pend_i 8'00000000
10051 assign \fur_x1_ld_pend_i \dm1_ld_wait_o
10055 assign \fur_x2_st_pend_i 8'00000000
10056 assign \fur_x2_st_pend_i \dm2_st_wait_o
10060 assign \fur_x2_ld_pend_i 8'00000000
10061 assign \fur_x2_ld_pend_i \dm2_ld_wait_o
10065 assign \fur_x3_st_pend_i 8'00000000
10066 assign \fur_x3_st_pend_i \dm3_st_wait_o
10070 assign \fur_x3_ld_pend_i 8'00000000
10071 assign \fur_x3_ld_pend_i \dm3_ld_wait_o
10075 assign \fur_x4_st_pend_i 8'00000000
10076 assign \fur_x4_st_pend_i \dm4_st_wait_o
10080 assign \fur_x4_ld_pend_i 8'00000000
10081 assign \fur_x4_ld_pend_i \dm4_ld_wait_o
10085 assign \fur_x5_st_pend_i 8'00000000
10086 assign \fur_x5_st_pend_i \dm5_st_wait_o
10090 assign \fur_x5_ld_pend_i 8'00000000
10091 assign \fur_x5_ld_pend_i \dm5_ld_wait_o
10095 assign \fur_x6_st_pend_i 8'00000000
10096 assign \fur_x6_st_pend_i \dm6_st_wait_o
10100 assign \fur_x6_ld_pend_i 8'00000000
10101 assign \fur_x6_ld_pend_i \dm6_ld_wait_o
10105 assign \fur_x7_st_pend_i 8'00000000
10106 assign \fur_x7_st_pend_i \dm7_st_wait_o
10110 assign \fur_x7_ld_pend_i 8'00000000
10111 assign \fur_x7_ld_pend_i \dm7_ld_wait_o
10115 assign \dm0_issue_i 8'00000000
10116 assign \dm1_issue_i 8'00000000
10117 assign \dm2_issue_i 8'00000000
10118 assign \dm3_issue_i 8'00000000
10119 assign \dm4_issue_i 8'00000000
10120 assign \dm5_issue_i 8'00000000
10121 assign \dm6_issue_i 8'00000000
10122 assign \dm7_issue_i 8'00000000
10123 assign { \dm7_issue_i [0] \dm6_issue_i [0] \dm5_issue_i [0] \dm4_issue_i [0] \dm3_issue_i [0] \dm2_issue_i [0] \dm1_issue_i [0] \dm0_issue_i [0] } \issue_i
10124 assign { \dm7_issue_i [1] \dm6_issue_i [1] \dm5_issue_i [1] \dm4_issue_i [1] \dm3_issue_i [1] \dm2_issue_i [1] \dm1_issue_i [1] \dm0_issue_i [1] } \issue_i
10125 assign { \dm7_issue_i [2] \dm6_issue_i [2] \dm5_issue_i [2] \dm4_issue_i [2] \dm3_issue_i [2] \dm2_issue_i [2] \dm1_issue_i [2] \dm0_issue_i [2] } \issue_i
10126 assign { \dm7_issue_i [3] \dm6_issue_i [3] \dm5_issue_i [3] \dm4_issue_i [3] \dm3_issue_i [3] \dm2_issue_i [3] \dm1_issue_i [3] \dm0_issue_i [3] } \issue_i
10127 assign { \dm7_issue_i [4] \dm6_issue_i [4] \dm5_issue_i [4] \dm4_issue_i [4] \dm3_issue_i [4] \dm2_issue_i [4] \dm1_issue_i [4] \dm0_issue_i [4] } \issue_i
10128 assign { \dm7_issue_i [5] \dm6_issue_i [5] \dm5_issue_i [5] \dm4_issue_i [5] \dm3_issue_i [5] \dm2_issue_i [5] \dm1_issue_i [5] \dm0_issue_i [5] } \issue_i
10129 assign { \dm7_issue_i [6] \dm6_issue_i [6] \dm5_issue_i [6] \dm4_issue_i [6] \dm3_issue_i [6] \dm2_issue_i [6] \dm1_issue_i [6] \dm0_issue_i [6] } \issue_i
10130 assign { \dm7_issue_i [7] \dm6_issue_i [7] \dm5_issue_i [7] \dm4_issue_i [7] \dm3_issue_i [7] \dm2_issue_i [7] \dm1_issue_i [7] \dm0_issue_i [7] } \issue_i
10134 assign \dm0_go_st_i 8'00000000
10135 assign \dm0_go_st_i \go_st_i
10139 assign \dm0_go_ld_i 8'00000000
10140 assign \dm0_go_ld_i \go_ld_i
10144 assign \dm0_go_die_i 8'00000000
10145 assign \dm0_go_die_i \go_die_i
10149 assign \dm1_go_st_i 8'00000000
10150 assign \dm1_go_st_i \go_st_i
10154 assign \dm1_go_ld_i 8'00000000
10155 assign \dm1_go_ld_i \go_ld_i
10159 assign \dm1_go_die_i 8'00000000
10160 assign \dm1_go_die_i \go_die_i
10164 assign \dm2_go_st_i 8'00000000
10165 assign \dm2_go_st_i \go_st_i
10169 assign \dm2_go_ld_i 8'00000000
10170 assign \dm2_go_ld_i \go_ld_i
10174 assign \dm2_go_die_i 8'00000000
10175 assign \dm2_go_die_i \go_die_i
10179 assign \dm3_go_st_i 8'00000000
10180 assign \dm3_go_st_i \go_st_i
10184 assign \dm3_go_ld_i 8'00000000
10185 assign \dm3_go_ld_i \go_ld_i
10189 assign \dm3_go_die_i 8'00000000
10190 assign \dm3_go_die_i \go_die_i
10194 assign \dm4_go_st_i 8'00000000
10195 assign \dm4_go_st_i \go_st_i
10199 assign \dm4_go_ld_i 8'00000000
10200 assign \dm4_go_ld_i \go_ld_i
10204 assign \dm4_go_die_i 8'00000000
10205 assign \dm4_go_die_i \go_die_i
10209 assign \dm5_go_st_i 8'00000000
10210 assign \dm5_go_st_i \go_st_i
10214 assign \dm5_go_ld_i 8'00000000
10215 assign \dm5_go_ld_i \go_ld_i
10219 assign \dm5_go_die_i 8'00000000
10220 assign \dm5_go_die_i \go_die_i
10224 assign \dm6_go_st_i 8'00000000
10225 assign \dm6_go_st_i \go_st_i
10229 assign \dm6_go_ld_i 8'00000000
10230 assign \dm6_go_ld_i \go_ld_i
10234 assign \dm6_go_die_i 8'00000000
10235 assign \dm6_go_die_i \go_die_i
10239 assign \dm7_go_st_i 8'00000000
10240 assign \dm7_go_st_i \go_st_i
10244 assign \dm7_go_ld_i 8'00000000
10245 assign \dm7_go_ld_i \go_ld_i
10249 assign \dm7_go_die_i 8'00000000
10250 assign \dm7_go_die_i \go_die_i
10254 assign \dm0_st_pend_i 8'00000000
10255 assign \dm0_st_pend_i \st_pend_i
10259 assign \dm0_ld_pend_i 8'00000000
10260 assign \dm0_ld_pend_i \ld_pend_i
10264 assign \dm1_st_pend_i 8'00000000
10265 assign \dm1_st_pend_i \st_pend_i
10269 assign \dm1_ld_pend_i 8'00000000
10270 assign \dm1_ld_pend_i \ld_pend_i
10274 assign \dm2_st_pend_i 8'00000000
10275 assign \dm2_st_pend_i \st_pend_i
10279 assign \dm2_ld_pend_i 8'00000000
10280 assign \dm2_ld_pend_i \ld_pend_i
10284 assign \dm3_st_pend_i 8'00000000
10285 assign \dm3_st_pend_i \st_pend_i
10289 assign \dm3_ld_pend_i 8'00000000
10290 assign \dm3_ld_pend_i \ld_pend_i
10294 assign \dm4_st_pend_i 8'00000000
10295 assign \dm4_st_pend_i \st_pend_i
10299 assign \dm4_ld_pend_i 8'00000000
10300 assign \dm4_ld_pend_i \ld_pend_i
10304 assign \dm5_st_pend_i 8'00000000
10305 assign \dm5_st_pend_i \st_pend_i
10309 assign \dm5_ld_pend_i 8'00000000
10310 assign \dm5_ld_pend_i \ld_pend_i
10314 assign \dm6_st_pend_i 8'00000000
10315 assign \dm6_st_pend_i \st_pend_i
10319 assign \dm6_ld_pend_i 8'00000000
10320 assign \dm6_ld_pend_i \ld_pend_i
10324 assign \dm7_st_pend_i 8'00000000
10325 assign \dm7_st_pend_i \st_pend_i
10329 assign \dm7_ld_pend_i 8'00000000
10330 assign \dm7_ld_pend_i \ld_pend_i
10334 attribute \generator "nMigen"
10336 attribute \nmigen.hierarchy "test_mem_fus"
10337 module \test_mem_fus
10338 attribute \src "scoreboard/test_mem_fu_matrix.py:72"
10339 wire width 8 input 0 \ld_i
10340 attribute \src "scoreboard/test_mem_fu_matrix.py:73"
10341 wire width 8 input 1 \st_i
10342 attribute \src "scoreboard/test_mem_fu_matrix.py:84"
10343 wire width 8 input 2 \req_rel_i
10344 attribute \src "scoreboard/test_mem_fu_matrix.py:85"
10345 wire width 8 output 3 \loadable_o
10346 attribute \src "scoreboard/test_mem_fu_matrix.py:86"
10347 wire width 8 output 4 \storable_o
10348 attribute \src "scoreboard/test_mem_fu_matrix.py:75"
10349 wire width 8 input 5 \load_hit_i
10350 attribute \src "scoreboard/test_mem_fu_matrix.py:76"
10351 wire width 8 input 6 \stwd_hit_i
10352 attribute \src "scoreboard/test_mem_fu_matrix.py:88"
10353 wire width 8 input 7 \go_st_i
10354 attribute \src "scoreboard/test_mem_fu_matrix.py:89"
10355 wire width 8 input 8 \go_ld_i
10356 attribute \src "scoreboard/test_mem_fu_matrix.py:90"
10357 wire width 8 input 9 \go_die_i
10358 attribute \src "scoreboard/test_mem_fu_matrix.py:91"
10359 wire width 8 input 10 \req_rel_o
10360 attribute \src "scoreboard/test_mem_fu_matrix.py:92"
10361 wire width 8 input 11 \fn_issue_i
10362 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
10363 wire width 1 input 12 \clk
10364 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
10365 wire width 1 input 13 \rst
10366 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:51"
10367 wire width 8 \ldstdeps_ld_pend_i
10368 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:52"
10369 wire width 8 \ldstdeps_st_pend_i
10370 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:53"
10371 wire width 8 \ldstdeps_issue_i
10372 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:56"
10373 wire width 8 \ldstdeps_load_hit_i
10374 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:58"
10375 wire width 8 \ldstdeps_stwd_hit_i
10376 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:54"
10377 wire width 8 \ldstdeps_go_die_i
10378 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:62"
10379 wire width 8 \ldstdeps_ld_hold_st_o
10380 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/ldst_matrix.py:64"
10381 wire width 8 \ldstdeps_st_hold_ld_o
10382 cell \ldstdeps \ldstdeps
10383 connect \ld_pend_i \ldstdeps_ld_pend_i
10384 connect \st_pend_i \ldstdeps_st_pend_i
10385 connect \issue_i \ldstdeps_issue_i
10386 connect \load_hit_i \ldstdeps_load_hit_i
10387 connect \stwd_hit_i \ldstdeps_stwd_hit_i
10388 connect \go_die_i \ldstdeps_go_die_i
10389 connect \ld_hold_st_o \ldstdeps_ld_hold_st_o
10390 connect \st_hold_ld_o \ldstdeps_st_hold_ld_o
10394 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:30"
10395 wire width 8 \fumemdeps_storable_o
10396 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:31"
10397 wire width 8 \fumemdeps_loadable_o
10398 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:22"
10399 wire width 8 \fumemdeps_ld_pend_i
10400 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:21"
10401 wire width 8 \fumemdeps_st_pend_i
10402 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:26"
10403 wire width 8 \fumemdeps_go_st_i
10404 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:25"
10405 wire width 8 \fumemdeps_go_ld_i
10406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:27"
10407 wire width 8 \fumemdeps_go_die_i
10408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_mem_matrix.py:23"
10409 wire width 8 \fumemdeps_issue_i
10410 cell \fumemdeps \fumemdeps
10411 connect \storable_o \fumemdeps_storable_o
10412 connect \loadable_o \fumemdeps_loadable_o
10413 connect \ld_pend_i \fumemdeps_ld_pend_i
10414 connect \st_pend_i \fumemdeps_st_pend_i
10415 connect \go_st_i \fumemdeps_go_st_i
10416 connect \go_ld_i \fumemdeps_go_ld_i
10417 connect \go_die_i \fumemdeps_go_die_i
10418 connect \issue_i \fumemdeps_issue_i
10423 assign \ldstdeps_ld_pend_i 8'00000000
10424 assign \ldstdeps_ld_pend_i \ld_i
10428 assign \ldstdeps_st_pend_i 8'00000000
10429 assign \ldstdeps_st_pend_i \st_i
10433 assign \ldstdeps_issue_i 8'00000000
10434 assign \ldstdeps_issue_i \fn_issue_i
10438 assign \ldstdeps_load_hit_i 8'00000000
10439 assign \ldstdeps_load_hit_i \load_hit_i
10443 assign \ldstdeps_stwd_hit_i 8'00000000
10444 assign \ldstdeps_stwd_hit_i \stwd_hit_i
10448 assign \ldstdeps_go_die_i 8'00000000
10449 assign \ldstdeps_go_die_i \go_die_i
10453 assign \storable_o 8'00000000
10454 assign \storable_o \fumemdeps_storable_o
10458 assign \loadable_o 8'00000000
10459 assign \loadable_o \fumemdeps_loadable_o
10463 assign \fumemdeps_ld_pend_i 8'00000000
10464 assign \fumemdeps_ld_pend_i \ldstdeps_ld_hold_st_o
10468 assign \fumemdeps_st_pend_i 8'00000000
10469 assign \fumemdeps_st_pend_i \ldstdeps_st_hold_ld_o
10473 assign \fumemdeps_go_st_i 8'00000000
10474 assign \fumemdeps_go_st_i \stwd_hit_i
10478 assign \fumemdeps_go_ld_i 8'00000000
10479 assign \fumemdeps_go_ld_i \load_hit_i
10483 assign \fumemdeps_go_die_i 8'00000000
10484 assign \fumemdeps_go_die_i \go_die_i
10488 assign \fumemdeps_issue_i 8'00000000
10489 assign \fumemdeps_issue_i \fn_issue_i