2 from __future__
import print_function
10 from helpers
.io
import ErrorMessage
, WarningMessage
11 from helpers
import trace
, l
, u
, n
13 from Hurricane
import DbU
14 from plugins
.alpha
.block
.configuration
import IoPin
, GaugeConf
15 from plugins
.alpha
.block
.iospecs
import IoSpecs
16 from plugins
.alpha
.block
.block
import Block
17 from plugins
.alpha
.core2chip
.niolib
import CoreToChip
18 from plugins
.alpha
.chip
.configuration
import ChipConf
19 from plugins
.alpha
.chip
.chip
import Chip
22 af
= CRL
.AllianceFramework
.get()
24 def scriptMain (**kw
):
25 """The mandatory function to be called by Coriolis CGT/Unicorn."""
29 cwd
= os
.path
.split( os
.path
.abspath(__file__
) )[0]
31 ioSpecs
.loadFromPinmux( '{}/ls180/litex_pinpads.json'.format(cwd
) )
33 #helpers.setTraceLevel( 550 )
34 cell
, editor
= plugins
.kwParseMain( **kw
)
35 cell
= af
.getCell( 'ls180', CRL
.Catalog
.State
.Logical
)
37 print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to '
38 'load cell "{}".'.format('ls180') ))
40 if editor
: editor
.setCell( cell
)
41 ls180Conf
= ChipConf( cell
, ioPads
=ioSpecs
.ioPadsSpec
)
42 ls180Conf
.cfg
.etesian
.bloat
= 'nsxlib'
43 ls180Conf
.cfg
.etesian
.uniformDensity
= True
44 ls180Conf
.cfg
.etesian
.aspectRatio
= 1.0
45 ls180Conf
.cfg
.etesian
.spaceMargin
= 0.05
46 #ls180Conf.cfg.katana.hTracksReservedLocal = 6
47 #ls180Conf.cfg.katana.vTracksReservedLocal = 3
48 ls180Conf
.cfg
.katana
.hTracksReservedMin
= 6
49 ls180Conf
.cfg
.katana
.vTracksReservedMin
= 1
50 ls180Conf
.cfg
.block
.spareSide
= l(700)
51 ls180Conf
.cfg
.chip
.padCoreSide
= 'North'
52 ls180Conf
.editor
= editor
53 ls180Conf
.useSpares
= True
54 ls180Conf
.useClockTree
= True
55 ls180Conf
.bColumns
= 2
57 ls180Conf
.chipConf
.name
= 'chip'
58 ls180Conf
.chipConf
.ioPadGauge
= 'niolib'
59 ls180Conf
.coreSize
= (l(coreSize
), l(coreSize
))
60 ls180Conf
.chipSize
= (l(coreSize
+3360), l(coreSize
+3360))
61 # ooo, how annoying. nsxlib (only 6 METAL) cannot cope with 3 clocks!
62 #ls180Conf.useHTree('core.por_clk') # output from the PLL, needs to be H-Tree
63 ls180Conf
.useHTree('jtag_tck_from_pad')
64 ls180Conf
.useHTree('sys_clk_from_pad')
66 ls180ToChip
= CoreToChip( ls180Conf
)
67 ls180ToChip
.buildChip()
69 chipBuilder
= Chip( ls180Conf
)
70 chipBuilder
.doChipFloorplan()
72 rvalue
= chipBuilder
.doPnR()
74 CRL
.Gds
.save(ls180Conf
.chip
)