experiments9/non_generated/spblock512w64b8w_3.vbe

   1 -- Phony VHDL interface for SRAM block.
   2
   3 entity spblock512w64b8w_3 is
   4    port ( clk     : in  bit
   5         ; we      : in  bit_vector( 7 downto 0)
   6         ; a       : in  bit_vector( 8 downto 0)
   7         ; d       : in  bit_vector(63 downto 0)
   8         ; q       : out bit_vector(63 downto 0)
   9         ; vdd     : in  bit
  10         ; vss     : in  bit
  11         );
  12 end spblock512w64b8w_3;
  13
  14 architecture behavioral of spblock512w64b8w_3 is
  15
  16 begin
  17
  18 end behavioral;