sim, kvm: make KvmVM a System parameter
[gem5.git] / ext / dsent / model / electrical / TestModel.cc
1 /* Copyright (c) 2012 Massachusetts Institute of Technology
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a copy
4 * of this software and associated documentation files (the "Software"), to deal
5 * in the Software without restriction, including without limitation the rights
6 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
7 * copies of the Software, and to permit persons to whom the Software is
8 * furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
19 * THE SOFTWARE.
20 */
21
22 #include "model/electrical/TestModel.h"
23
24 #include <cmath>
25
26 #include "model/std_cells/StdCell.h"
27 #include "model/std_cells/StdCellLib.h"
28 #include "model/electrical/RippleAdder.h"
29 #include "model/electrical/Multiplexer.h"
30 #include "model/timing_graph/ElectricalNet.h"
31 #include "model/timing_graph/ElectricalDriver.h"
32 #include "model/timing_graph/ElectricalLoad.h"
33 #include "model/timing_graph/ElectricalTimingTree.h"
34
35 namespace DSENT
36 {
37 TestModel::TestModel(const String& instance_name_, const TechModel* tech_model_)
38 : ElectricalModel(instance_name_, tech_model_)
39 {
40 initProperties();
41 }
42
43 TestModel::~TestModel()
44 {}
45
46 void TestModel::initProperties()
47 {
48 return;
49 }
50
51 TestModel* TestModel::clone() const
52 {
53 return NULL;
54 }
55
56 void TestModel::constructModel()
57 {
58 unsigned int num_bits = 64;
59 unsigned int mux_bits = 1;
60
61 // Create the instance
62 createNet("CK");
63 createNet("CI");
64 getNet("CI")->setDistributedCap(100e-15);
65 getNet("CI")->setDistributedRes(10);
66 createNet("CO");
67 createNet("A", makeNetIndex(0, num_bits - 1));
68 createNet("B", makeNetIndex(0, num_bits - 1));
69 createNet("S", makeNetIndex(0, num_bits - 1));
70
71 StdCell* ci_reg = getTechModel()->getStdCellLib()->createStdCell("DFFQ", "DFFQ-CI");
72 ci_reg->setProperty("P(D)", 0.5);
73 ci_reg->setProperty("P(CK)", 0.5);
74 ci_reg->construct();
75 portConnect(ci_reg, "Q", "CI");
76 portConnect(ci_reg, "CK", "CK");
77 //ci_reg->connect("Q", getNet("CI"));
78 //ci_reg->connect("CK", getNet("CK"));
79 addSubInstances(ci_reg, 1.0);
80
81 StdCell* co_reg = getTechModel()->getStdCellLib()->createStdCell("DFFQ", "DFFQ-CO");
82 co_reg->setProperty("P(D)", 0.5);
83 co_reg->setProperty("P(CK)", 0.5);
84 co_reg->construct();
85 portConnect(co_reg, "D", "CO");
86 portConnect(co_reg, "CK", "CK");
87 //co_reg->connect("D", getNet("CO"));
88 //co_reg->connect("CK", getNet("CK"));
89 addSubInstances(co_reg, 1.0);
90
91 for (unsigned int i = 0; i < num_bits; i++)
92 {
93 StdCell* a_reg = getTechModel()->getStdCellLib()->createStdCell("DFFQ", "DFFQ-A[" + (String) i + "]");
94 a_reg->setProperty("P(D)", 0.5);
95 a_reg->setProperty("P(CK)", 0.5);
96 a_reg->construct();
97 portConnect(a_reg, "Q", "A", makeNetIndex(i));
98 portConnect(a_reg, "CK", "CK");
99 //a_reg->connect("Q", getNet("A[" + (String) i + "]"));
100 //a_reg->connect("CK", getNet("CK"));
101 addSubInstances(a_reg, 1.0);
102
103 StdCell* b_reg = getTechModel()->getStdCellLib()->createStdCell("DFFQ", "DFFQ-B[" + (String) i + "]");
104 b_reg->setProperty("P(D)", 0.5);
105 b_reg->setProperty("P(CK)", 0.5);
106 b_reg->construct();
107 portConnect(b_reg, "Q", "B", makeNetIndex(i));
108 portConnect(b_reg, "CK", "CK");
109 //b_reg->connect("Q", getNet("B[" + (String) i + "]"));
110 //b_reg->connect("CK", getNet("CK"));
111 addSubInstances(b_reg, 1.0);
112
113 StdCell* s_reg = getTechModel()->getStdCellLib()->createStdCell("DFFQ", "DFFQ-S[" + (String) i + "]");
114 s_reg->setProperty("P(D)", 0.5);
115 s_reg->setProperty("P(CK)", 0.5);
116 s_reg->construct();
117 portConnect(s_reg, "D", "S", makeNetIndex(i));
118 portConnect(s_reg, "CK", "CK");
119 //s_reg->connect("D", getNet("A[" + (String) i + "]"));
120 //s_reg->connect("CK", getNet("CK"));
121 addSubInstances(s_reg, 1.0);
122 }
123
124
125 //Create some adders!
126
127 ElectricalModel* ripple_adder = new RippleAdder("Adder_1", getTechModel());
128 ripple_adder->setParameter("NumberBits", num_bits);
129 ripple_adder->setProperty("P(A)", 0.5);
130 ripple_adder->setProperty("P(B)", 0.5);
131 ripple_adder->setProperty("P(CI)", 0.5);
132
133 ripple_adder->construct();
134 addSubInstances(ripple_adder, 1.0);
135 portConnect(ripple_adder, "CI", "CI");
136 portConnect(ripple_adder, "CO", "CO");
137 portConnect(ripple_adder, "A", "A");
138 portConnect(ripple_adder, "B", "B");
139 portConnect(ripple_adder, "S", "S");
140
141 ElectricalModel* multiplexer = new Multiplexer("Mux_1", getTechModel());
142 multiplexer->setParameter("NumberInputs", 2);
143 multiplexer->setParameter("NumberBits", mux_bits);
144 multiplexer->setParameter("BitDuplicate", "FALSE");
145 //multiplexer->setProperty("P(In)", "[0.5, 0.5, 0.5, 0.5, 0.5, 0.5, 0.5, 0.5]");
146 //multiplexer->setProperty("P(Sel)", "[0.5, 0.5, 0.5]");
147 //multiplexer->setProperty("Act(In)", "[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0]");
148 //multiplexer->setProperty("Act(Sel)", "[2.0, 4.0, 8.0]");
149 multiplexer->setProperty("P(In)", "[0.5, 0.5]");
150 multiplexer->setProperty("P(Sel)", "[0.5]");
151 multiplexer->setProperty("Act(In)", "[1.0, 1.0]");
152 multiplexer->setProperty("Act(Sel)", "[1.0]");
153 multiplexer->construct();
154
155 createNet("In0", makeNetIndex(0, mux_bits-1));
156 createNet("In1", makeNetIndex(0, mux_bits-1));
157 createNet("In2", makeNetIndex(0, mux_bits-1));
158 createNet("In3", makeNetIndex(0, mux_bits-1));
159 createNet("In4", makeNetIndex(0, mux_bits-1));
160 createNet("Out", makeNetIndex(0, mux_bits-1));
161
162 portConnect(multiplexer, "In0", "In0");
163 portConnect(multiplexer, "In1", "In1");
164 //portConnect(multiplexer, "In2", "In2");
165 //portConnect(multiplexer, "In3", "In3");
166 //portConnect(multiplexer, "In4", "In4");
167 portConnect(multiplexer, "Out", "Out");
168
169 for (unsigned int i = 0; i < mux_bits; ++i)
170 {
171 String n = (String) i;
172
173 createLoad("OutLoad[" + n + "]");
174 getLoad("OutLoad[" + n + "]")->setLoadCap(100e-15);
175
176 getNet("Out", makeNetIndex(i))->addDownstreamNode(getLoad("OutLoad[" + n + "]"));
177 }
178 createNet("Sel", makeNetIndex(0, 2));
179 assign("Sel", makeNetIndex(0), "CK");
180 assign("Sel", makeNetIndex(1), "CK");
181 assign("Sel", makeNetIndex(2), "CK");
182
183 //portConnect(multiplexer, "Sel", "Sel");
184
185 addSubInstances(multiplexer, 1.0);
186
187 //ElectricalTimingAbstract* abstract = new ElectricalTimingAbstract("HAHAHA", getTechModel(), ripple_adder);
188 //abstract->buildAbstract();
189
190 return;
191 }
192
193 void TestModel::updateModel()
194 {
195 Model::updateModel();
196
197 //ElectricalTimingTree* t = new ElectricalTimingTree("Add", this);
198 //t->performTimingOpt(getNet("CK"), 4.21300e-8);
199 //t->performTimingOpt(getNet("CK"), 1e-9);
200 //delete t;
201
202 ElectricalTimingTree* t2 = new ElectricalTimingTree("Mux", this);
203 t2->performTimingOpt(getNet("In1", makeNetIndex(0)), 500e-12);
204 delete t2;
205
206
207 }
208
209 void TestModel::evaluateModel()
210 {
211 Model::evaluateModel();
212
213 //ripple_adder->getNddPowerResult("LeakagePower")->print("RippleAdder->Leakage", 10, cout);
214 getSubInstance("Adder_1")->getNddPowerResult("Leakage")->print("RippleAdder->Leakage", 0, cout);
215 //ripple_adder->getAreaResult("TotalArea")->print("RippleAdder->TotalArea", 10, cout);
216 getSubInstance("Adder_1")->getAreaResult("Active")->print("RippleAdder->ActiveArea", 0, cout);
217 //ripple_adder->getEventResult("AddEvent")->print("RippleAdder->AddEvent", 10, cout);
218 getSubInstance("Adder_1")->getEventResult("Add")->print("RippleAdder->Add", 0, cout);
219
220 getSubInstance("Mux_1")->getNddPowerResult("Leakage")->print("Multiplexer->Leakage", 0, cout);
221 getSubInstance("Mux_1")->getAreaResult("Active")->print("Multiplexer->ActiveArea", 0, cout);
222 getSubInstance("Mux_1")->getEventResult("Mux")->print("Multiplexer->MuxEvent", 0, cout);
223 cout << "Multiplexer->P(Out) = " << getSubInstance("Mux_1")->getGenProperties()->get("P(Out)") << endl;
224
225 getSubInstance("DFFQ-CI")->getNddPowerResult("Leakage")->print("DFFQ-CI->Leakage", 0, cout);
226 getSubInstance("DFFQ-CI")->getAreaResult("Active")->print("DFFQ-CI->ActiveArea", 0, cout);
227 getSubInstance("DFFQ-CI")->getEventResult("DFF")->print("DFFQ-CI->DFF", 0, cout);
228 getSubInstance("DFFQ-CI")->getEventResult("CK")->print("DFFQ-CI->CK", 0, cout);
229
230 //ripple_adder->getNddPowerResult("LeakagePower")->print("RippleAdder->Leakage", 10, cout);
231 getSubInstance("Adder_1")->getNddPowerResult("Leakage")->print("RippleAdder->Leakage", 0, cout);
232 //ripple_adder->getAreaResult("TotalArea")->print("RippleAdder->TotalArea", 10, cout);
233 getSubInstance("Adder_1")->getAreaResult("Active")->print("RippleAdder->ActiveArea", 0, cout);
234 //ripple_adder->getEventResult("AddEvent")->print("RippleAdder->AddEvent", 10, cout);
235 getSubInstance("Adder_1")->getEventResult("Add")->print("RippleAdder->AddEvent", 0, cout);
236 }
237
238 } // namespace DSENT
239