1 /*****************************************************************************
3 * SOFTWARE LICENSE AGREEMENT
4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
30 ***************************************************************************/
37 //#define _CRT_SECURE_NO_DEPRECATE
45 #include "xmlParser.h"
49 void myfree(char *t); // {free(t);}
50 ToXMLStringTool tx,tx2;
52 //all subnodes at the level of system.core(0-n)
53 //cache_policy is added into cache property arrays;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
57 char prediction_scheme
[20];
59 int predictor_entries
;
60 int local_predictor_size
[20];
61 int local_predictor_entries
;
62 int global_predictor_entries
;
63 int global_predictor_bits
;
64 int chooser_predictor_entries
;
65 int chooser_predictor_bits
;
66 double predictor_accesses
;
67 } predictor_systemcore
;
70 int cache_policy
;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
72 double total_accesses
;
78 double icache_config
[20];
80 int cache_policy
;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
82 double total_accesses
;
89 double miss_buffer_access
;
90 double fill_buffer_accesses
;
91 double prefetch_buffer_accesses
;
92 double prefetch_buffer_writes
;
93 double prefetch_buffer_reads
;
94 double prefetch_buffer_hits
;
100 int cache_policy
;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
102 double total_accesses
;
103 double read_accesses
;
104 double write_accesses
;
115 double dcache_config
[20];
116 int buffer_sizes
[20];
117 int cache_policy
;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
119 double total_accesses
;
120 double read_accesses
;
121 double write_accesses
;
130 double miss_buffer_access
;
131 double fill_buffer_accesses
;
132 double prefetch_buffer_accesses
;
133 double prefetch_buffer_writes
;
134 double prefetch_buffer_reads
;
135 double prefetch_buffer_hits
;
144 double total_accesses
;
145 double read_accesses
;
146 double write_accesses
;
156 //all params at the level of system.core(0-n)
161 int virtual_address_width
;
162 int physical_address_width
;
164 int micro_opcode_width
;
165 int instruction_length
;
167 int internal_datapath_width
;
168 int number_hardware_threads
;
170 int number_instruction_fetch_ports
;
173 int peak_issue_width
;
175 int pipelines_per_core
[20];
176 int pipeline_depth
[20];
178 char divider_multiplier
[20];
182 int instruction_buffer_size
;
183 int decoded_stream_buffer_size
;
184 int instruction_window_scheme
;
185 int instruction_window_size
;
186 int fp_instruction_window_size
;
188 int archi_Regs_IRF_size
;
189 int archi_Regs_FRF_size
;
190 int phy_Regs_IRF_size
;
191 int phy_Regs_FRF_size
;
193 int register_windows_size
;
195 int store_buffer_size
;
196 int load_buffer_size
;
198 char Dcache_dual_pump
[20];
201 int prediction_width
;
205 //all stats at the level of system.core(0-n)
206 double total_instructions
;
207 double int_instructions
;
208 double fp_instructions
;
209 double branch_instructions
;
210 double branch_mispredictions
;
211 double committed_instructions
;
212 double committed_int_instructions
;
213 double committed_fp_instructions
;
214 double load_instructions
;
215 double store_instructions
;
219 double instruction_buffer_reads
;
220 double instruction_buffer_write
;
223 double rename_accesses
;
224 double fp_rename_accesses
;
226 double rename_writes
;
227 double fp_rename_reads
;
228 double fp_rename_writes
;
229 double inst_window_reads
;
230 double inst_window_writes
;
231 double inst_window_wakeup_accesses
;
232 double inst_window_selections
;
233 double fp_inst_window_reads
;
234 double fp_inst_window_writes
;
235 double fp_inst_window_wakeup_accesses
;
236 double fp_inst_window_selections
;
237 double archi_int_regfile_reads
;
238 double archi_float_regfile_reads
;
239 double phy_int_regfile_reads
;
240 double phy_float_regfile_reads
;
241 double phy_int_regfile_writes
;
242 double phy_float_regfile_writes
;
243 double archi_int_regfile_writes
;
244 double archi_float_regfile_writes
;
245 double int_regfile_reads
;
246 double float_regfile_reads
;
247 double int_regfile_writes
;
248 double float_regfile_writes
;
249 double windowed_reg_accesses
;
250 double windowed_reg_transports
;
251 double function_calls
;
252 double context_switches
;
253 double ialu_accesses
;
256 double cdb_alu_accesses
;
257 double cdb_mul_accesses
;
258 double cdb_fpu_accesses
;
259 double load_buffer_reads
;
260 double load_buffer_writes
;
261 double load_buffer_cams
;
262 double store_buffer_reads
;
263 double store_buffer_writes
;
264 double store_buffer_cams
;
265 double store_buffer_forwards
;
266 double main_memory_access
;
267 double main_memory_read
;
268 double main_memory_write
;
269 double pipeline_duty_cycle
;
271 double IFU_duty_cycle
;
272 double BR_duty_cycle
;
273 double LSU_duty_cycle
;
274 double MemManU_I_duty_cycle
;
275 double MemManU_D_duty_cycle
;
276 double ALU_duty_cycle
;
277 double MUL_duty_cycle
;
278 double FPU_duty_cycle
;
279 double ALU_cdb_duty_cycle
;
280 double MUL_cdb_duty_cycle
;
281 double FPU_cdb_duty_cycle
;
283 //all subnodes at the level of system.core(0-n)
284 predictor_systemcore predictor
;
285 itlb_systemcore itlb
;
286 icache_systemcore icache
;
287 dtlb_systemcore dtlb
;
288 dcache_systemcore dcache
;
295 double Dir_config
[20];
296 int buffer_sizes
[20];
300 int cache_policy
;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
301 char threeD_stack
[20];
303 double total_accesses
;
304 double read_accesses
;
305 double write_accesses
;
310 } system_L1Directory
;
314 double Dir_config
[20];
315 int buffer_sizes
[20];
319 int cache_policy
;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
320 char threeD_stack
[20];
322 double total_accesses
;
323 double read_accesses
;
324 double write_accesses
;
329 } system_L2Directory
;
332 double L2_config
[20];
336 int cache_policy
;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
337 char threeD_stack
[20];
338 int buffer_sizes
[20];
340 double total_accesses
;
341 double read_accesses
;
342 double write_accesses
;
351 double miss_buffer_accesses
;
352 double fill_buffer_accesses
;
353 double prefetch_buffer_accesses
;
354 double prefetch_buffer_writes
;
355 double prefetch_buffer_reads
;
356 double prefetch_buffer_hits
;
363 double homenode_read_accesses
;
364 double homenode_write_accesses
;
365 double homenode_read_hits
;
366 double homenode_write_hits
;
367 double homenode_read_misses
;
368 double homenode_write_misses
;
369 double dir_duty_cycle
;
373 double L3_config
[20];
377 int cache_policy
;//0 no write or write-though with non-write allocate;1 write-back with write-allocate
378 char threeD_stack
[20];
379 int buffer_sizes
[20];
381 double total_accesses
;
382 double read_accesses
;
383 double write_accesses
;
392 double miss_buffer_accesses
;
393 double fill_buffer_accesses
;
394 double prefetch_buffer_accesses
;
395 double prefetch_buffer_writes
;
396 double prefetch_buffer_reads
;
397 double prefetch_buffer_hits
;
404 double homenode_read_accesses
;
405 double homenode_write_accesses
;
406 double homenode_read_hits
;
407 double homenode_write_hits
;
408 double homenode_read_misses
;
409 double homenode_write_misses
;
410 double dir_duty_cycle
;
414 int number_of_inputs_of_crossbars
;
415 int number_of_outputs_of_crossbars
;
417 int input_buffer_entries_per_port
;
418 int ports_of_input_buffer
[20];
420 double crossbar_accesses
;
426 bool has_global_link
;
428 int horizontal_nodes
;
434 int virtual_channel_per_port
;
436 int input_buffer_entries_per_vc
;
437 int ports_of_input_buffer
[20];
439 int number_of_crossbars
;
440 char crossbar_type
[20];
441 char crosspoint_type
[20];
442 xbar0_systemNoC xbar0
;
444 double chip_coverage
;
446 double total_accesses
;
448 double route_over_perc
;
454 int peak_transfer_rate
;
455 int internal_prefetch_of_DRAM_chip
;
456 int capacity_per_channel
;
458 int num_banks_of_DRAM_chip
;
459 int Block_width_of_DRAM_chip
;
460 int output_width_of_DRAM_chip
;
461 int page_size_of_DRAM_chip
;
462 int burstlength_of_DRAM_chip
;
464 double memory_accesses
;
466 double memory_writes
;
470 //Common Param for mc and fc
471 double peak_transfer_rate
;
479 double total_load_perc
;
484 int memory_channels_per_mc
;
486 int req_window_size_per_channel
;
487 int IO_buffer_size_per_channel
;
489 int addressbus_width
;
493 double memory_accesses
;
495 double memory_writes
;
505 double total_load_perc
;
517 double total_load_perc
;
521 //All number_of_* at the level of 'system' Ying 03/21/2009
523 int number_of_L1Directories
;
524 int number_of_L2Directories
;
529 int number_of_dir_levels
;
532 // All params at the level of 'system'
533 int homogeneous_cores
;
534 int homogeneous_L1Directories
;
535 int homogeneous_L2Directories
;
536 double core_tech_node
;
537 int target_core_clockrate
;
538 int target_chip_area
;
540 int number_cache_levels
;
546 int homogeneous_NoCs
;
548 int Max_area_deviation
;
549 int Max_power_deviation
;
551 bool longer_channel_device
;
553 bool opt_dynamic_power
;
554 bool opt_lakage_power
;
557 int interconnect_projection_type
;
559 int virtual_address_width
;
560 int physical_address_width
;
561 int virtual_memory_page_size
;
563 //system.core(0-n):3rd level
564 system_core core
[64];
565 system_L1Directory L1Directory
[64];
566 system_L2Directory L2Directory
[64];
580 void parse(char* filepath
);
587 #endif /* XML_PARSE_H_ */