ext/mcpat/cacti/parameter.h

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  31
  32
  33
  34 #ifndef __PARAMETER_H__
  35 #define __PARAMETER_H__
  36
  37 #include "area.h"
  38 #include "cacti_interface.h"
  39 #include "const.h"
  40 #include "io.h"
  41
  42 // parameters which are functions of certain device technology
  43 class TechnologyParameter
  44 {
  45  public:
  46   class DeviceType
  47   {
  48    public:
  49     double C_g_ideal;
  50     double C_fringe;
  51     double C_overlap;
  52     double C_junc;  // C_junc_area
  53     double C_junc_sidewall;
  54     double l_phy;
  55     double l_elec;
  56     double R_nch_on;
  57     double R_pch_on;
  58     double Vdd;
  59     double Vth;
  60     double I_on_n;
  61     double I_on_p;
  62     double I_off_n;
  63     double I_off_p;
  64     double I_g_on_n;
  65     double I_g_on_p;
  66     double C_ox;
  67     double t_ox;
  68     double n_to_p_eff_curr_drv_ratio;
  69     double long_channel_leakage_reduction;
  70
  71     DeviceType(): C_g_ideal(0), C_fringe(0), C_overlap(0), C_junc(0),
  72                   C_junc_sidewall(0), l_phy(0), l_elec(0), R_nch_on(0), R_pch_on(0),
  73                   Vdd(0), Vth(0),
  74                   I_on_n(0), I_on_p(0), I_off_n(0), I_off_p(0),I_g_on_n(0),I_g_on_p(0),
  75                   C_ox(0), t_ox(0), n_to_p_eff_curr_drv_ratio(0), long_channel_leakage_reduction(0) { };
  76     void reset()
  77     {
  78       C_g_ideal = 0;
  79       C_fringe  = 0;
  80       C_overlap = 0;
  81       C_junc    = 0;
  82       l_phy     = 0;
  83       l_elec    = 0;
  84       R_nch_on  = 0;
  85       R_pch_on  = 0;
  86       Vdd       = 0;
  87       Vth       = 0;
  88       I_on_n    = 0;
  89       I_on_p    = 0;
  90       I_off_n   = 0;
  91       I_off_p   = 0;
  92       I_g_on_n   = 0;
  93       I_g_on_p   = 0;
  94       C_ox      = 0;
  95       t_ox      = 0;
  96       n_to_p_eff_curr_drv_ratio = 0;
  97       long_channel_leakage_reduction = 0;
  98     }
  99
 100     void display(uint32_t indent = 0);
 101   };
 102   class InterconnectType
 103   {
 104    public:
 105     double pitch;
 106     double R_per_um;
 107     double C_per_um;
 108     double horiz_dielectric_constant;
 109     double vert_dielectric_constant;
 110     double aspect_ratio;
 111     double miller_value;
 112     double ild_thickness;
 113
 114     InterconnectType(): pitch(0), R_per_um(0), C_per_um(0) { };
 115
 116     void reset()
 117     {
 118       pitch = 0;
 119       R_per_um = 0;
 120       C_per_um = 0;
 121       horiz_dielectric_constant = 0;
 122       vert_dielectric_constant = 0;
 123       aspect_ratio = 0;
 124       miller_value = 0;
 125       ild_thickness = 0;
 126     }
 127
 128     void display(uint32_t indent = 0);
 129   };
 130   class MemoryType
 131   {
 132    public:
 133     double b_w;
 134     double b_h;
 135     double cell_a_w;
 136     double cell_pmos_w;
 137     double cell_nmos_w;
 138     double Vbitpre;
 139
 140     void reset()
 141     {
 142       b_w = 0;
 143       b_h = 0;
 144       cell_a_w = 0;
 145       cell_pmos_w = 0;
 146       cell_nmos_w = 0;
 147       Vbitpre = 0;
 148     }
 149
 150     void display(uint32_t indent = 0);
 151   };
 152
 153   class ScalingFactor
 154   {
 155    public:
 156     double logic_scaling_co_eff;
 157     double core_tx_density;
 158     double long_channel_leakage_reduction;
 159
 160     ScalingFactor(): logic_scaling_co_eff(0), core_tx_density(0),
 161     long_channel_leakage_reduction(0) { };
 162
 163     void reset()
 164     {
 165       logic_scaling_co_eff= 0;
 166       core_tx_density = 0;
 167       long_channel_leakage_reduction= 0;
 168     }
 169
 170     void display(uint32_t indent = 0);
 171   };
 172
 173   double ram_wl_stitching_overhead_;
 174   double min_w_nmos_;
 175   double max_w_nmos_;
 176   double max_w_nmos_dec;
 177   double unit_len_wire_del;
 178   double FO4;
 179   double kinv;
 180   double vpp;
 181   double w_sense_en;
 182   double w_sense_n;
 183   double w_sense_p;
 184   double sense_delay;
 185   double sense_dy_power;
 186   double w_iso;
 187   double w_poly_contact;
 188   double spacing_poly_to_poly;
 189   double spacing_poly_to_contact;
 190
 191   double w_comp_inv_p1;
 192   double w_comp_inv_p2;
 193   double w_comp_inv_p3;
 194   double w_comp_inv_n1;
 195   double w_comp_inv_n2;
 196   double w_comp_inv_n3;
 197   double w_eval_inv_p;
 198   double w_eval_inv_n;
 199   double w_comp_n;
 200   double w_comp_p;
 201
 202   double dram_cell_I_on;
 203   double dram_cell_Vdd;
 204   double dram_cell_I_off_worst_case_len_temp;
 205   double dram_cell_C;
 206   double gm_sense_amp_latch;
 207
 208   double w_nmos_b_mux;
 209   double w_nmos_sa_mux;
 210   double w_pmos_bl_precharge;
 211   double w_pmos_bl_eq;
 212   double MIN_GAP_BET_P_AND_N_DIFFS;
 213   double MIN_GAP_BET_SAME_TYPE_DIFFS;
 214   double HPOWERRAIL;
 215   double cell_h_def;
 216
 217   double chip_layout_overhead;
 218   double macro_layout_overhead;
 219   double sckt_co_eff;
 220
 221   double fringe_cap;
 222
 223   uint64_t h_dec;
 224
 225   DeviceType sram_cell;   // SRAM cell transistor
 226   DeviceType dram_acc;    // DRAM access transistor
 227   DeviceType dram_wl;     // DRAM wordline transistor
 228   DeviceType peri_global; // peripheral global
 229   DeviceType cam_cell;   // SRAM cell transistor
 230
 231   InterconnectType wire_local;
 232   InterconnectType wire_inside_mat;
 233   InterconnectType wire_outside_mat;
 234
 235   ScalingFactor scaling_factor;
 236
 237   MemoryType sram;
 238   MemoryType dram;
 239   MemoryType cam;
 240
 241   void display(uint32_t indent = 0);
 242
 243   void reset()
 244   {
 245     dram_cell_Vdd  = 0;
 246     dram_cell_I_on = 0;
 247     dram_cell_C    = 0;
 248     vpp            = 0;
 249
 250     sense_delay               = 0;
 251     sense_dy_power            = 0;
 252     fringe_cap                = 0;
 253 //    horiz_dielectric_constant = 0;
 254 //    vert_dielectric_constant  = 0;
 255 //    aspect_ratio              = 0;
 256 //    miller_value              = 0;
 257 //    ild_thickness             = 0;
 258
 259     dram_cell_I_off_worst_case_len_temp = 0;
 260
 261     sram_cell.reset();
 262     dram_acc.reset();
 263     dram_wl.reset();
 264     peri_global.reset();
 265     cam_cell.reset();
 266
 267     scaling_factor.reset();
 268
 269     wire_local.reset();
 270     wire_inside_mat.reset();
 271     wire_outside_mat.reset();
 272
 273     sram.reset();
 274     dram.reset();
 275     cam.reset();
 276
 277     chip_layout_overhead  = 0;
 278     macro_layout_overhead = 0;
 279     sckt_co_eff           = 0;
 280   }
 281 };
 282
 283
 284
 285 class DynamicParameter
 286 {
 287   public:
 288     bool is_tag;
 289     bool pure_ram;
 290     bool pure_cam;
 291     bool fully_assoc;
 292     int tagbits;
 293     int num_subarrays;  // only for leakage computation  -- the number of subarrays per bank
 294     int num_mats;       // only for leakage computation  -- the number of mats per bank
 295     double Nspd;
 296     int Ndwl;
 297     int Ndbl;
 298     int Ndcm;
 299     int deg_bl_muxing;
 300     int deg_senseamp_muxing_non_associativity;
 301     int Ndsam_lev_1;
 302     int Ndsam_lev_2;
 303     int number_addr_bits_mat;             // per port
 304     int number_subbanks_decode;           // per_port
 305     int num_di_b_bank_per_port;
 306     int num_do_b_bank_per_port;
 307     int num_di_b_mat;
 308     int num_do_b_mat;
 309     int num_di_b_subbank;
 310     int num_do_b_subbank;
 311
 312     int num_si_b_mat;
 313     int num_so_b_mat;
 314     int num_si_b_subbank;
 315     int num_so_b_subbank;
 316         int num_si_b_bank_per_port;
 317         int num_so_b_bank_per_port;
 318
 319     int number_way_select_signals_mat;
 320     int num_act_mats_hor_dir;
 321
 322     int num_act_mats_hor_dir_sl;
 323     bool is_dram;
 324     double V_b_sense;
 325     unsigned int num_r_subarray;
 326     unsigned int num_c_subarray;
 327     int tag_num_r_subarray;//sheng: fully associative cache tag and data must be computed together, data and tag must be separate
 328     int tag_num_c_subarray;
 329     int data_num_r_subarray;
 330     int data_num_c_subarray;
 331     int num_mats_h_dir;
 332     int num_mats_v_dir;
 333     uint32_t ram_cell_tech_type;
 334     double dram_refresh_period;
 335
 336     DynamicParameter();
 337     DynamicParameter(
 338         bool         is_tag_,
 339         int          pure_ram_,
 340         int          pure_cam_,
 341         double       Nspd_,
 342         unsigned int Ndwl_,
 343         unsigned int Ndbl_,
 344         unsigned int Ndcm_,
 345         unsigned int Ndsam_lev_1_,
 346         unsigned int Ndsam_lev_2_,
 347         bool         is_main_mem_);
 348
 349     int use_inp_params;
 350     unsigned int num_rw_ports;
 351     unsigned int num_rd_ports;
 352     unsigned int num_wr_ports;
 353     unsigned int num_se_rd_ports;  // number of single ended read ports
 354     unsigned int num_search_ports;
 355     unsigned int out_w;// == nr_bits_out
 356     bool   is_main_mem;
 357     Area   cell, cam_cell;//cell is the sram_cell in both nomal cache/ram and FA.
 358     bool   is_valid;
 359 };
 360
 361
 362
 363 extern InputParameter * g_ip;
 364 extern TechnologyParameter g_tp;
 365
 366 #endif
 367