ext/mcpat/cacti/subarray.cc

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  31
  32
  33
  34
  35 #include <cassert>
  36 #include <cmath>
  37 #include <iostream>
  38
  39 #include "subarray.h"
  40
  41 Subarray::Subarray(const DynamicParameter & dp_, bool is_fa_):
  42   dp(dp_), num_rows(dp.num_r_subarray), num_cols(dp.num_c_subarray),
  43   num_cols_fa_cam(dp.tag_num_c_subarray), num_cols_fa_ram(dp.data_num_c_subarray),
  44   cell(dp.cell), cam_cell(dp.cam_cell), is_fa(is_fa_)
  45 {
  46         //num_cols=7;
  47         //cout<<"num_cols ="<< num_cols <<endl;
  48   if (!(is_fa || dp.pure_cam))
  49   {
  50           num_cols +=(g_ip->add_ecc_b_ ? (int)ceil(num_cols / num_bits_per_ecc_b_) : 0);   // ECC overhead
  51           uint32_t ram_num_cells_wl_stitching =
  52                   (dp.ram_cell_tech_type == lp_dram)   ? dram_num_cells_wl_stitching_ :
  53           (dp.ram_cell_tech_type == comm_dram) ? comm_dram_num_cells_wl_stitching_ : sram_num_cells_wl_stitching_;
  54
  55           area.h = cell.h * num_rows;
  56
  57           area.w = cell.w * num_cols +
  58           ceil(num_cols / ram_num_cells_wl_stitching) * g_tp.ram_wl_stitching_overhead_;  // stitching overhead
  59   }
  60   else  //cam fa
  61   {
  62
  63           //should not add dummy row here since the dummy row do not need decoder
  64           if (is_fa)// fully associative cache
  65           {
  66                   num_cols_fa_cam  += g_ip->add_ecc_b_ ? (int)ceil(num_cols_fa_cam / num_bits_per_ecc_b_) : 0;
  67                   num_cols_fa_ram  += (g_ip->add_ecc_b_ ? (int)ceil(num_cols_fa_ram / num_bits_per_ecc_b_) : 0);
  68                   num_cols = num_cols_fa_cam + num_cols_fa_ram;
  69           }
  70           else
  71           {
  72                   num_cols_fa_cam  += g_ip->add_ecc_b_ ? (int)ceil(num_cols_fa_cam / num_bits_per_ecc_b_) : 0;
  73                   num_cols_fa_ram  = 0;
  74                   num_cols = num_cols_fa_cam;
  75           }
  76
  77           area.h = cam_cell.h * (num_rows + 1);//height of subarray is decided by CAM array. blank space in sram array are filled with dummy cells
  78           area.w = cam_cell.w * num_cols_fa_cam + cell.w * num_cols_fa_ram
  79           + ceil((num_cols_fa_cam + num_cols_fa_ram) / sram_num_cells_wl_stitching_)*g_tp.ram_wl_stitching_overhead_
  80           + 16*g_tp.wire_local.pitch //the overhead for the NAND gate to connect the two halves
  81           + 128*g_tp.wire_local.pitch;//the overhead for the drivers from matchline to wordline of RAM
  82   }
  83
  84   assert(area.h>0);
  85   assert(area.w>0);
  86   compute_C();
  87 }
  88
  89
  90
  91 Subarray::~Subarray()
  92 {
  93 }
  94
  95
  96
  97 double Subarray::get_total_cell_area()
  98 {
  99 //  return (is_fa==false? cell.get_area() * num_rows * num_cols
 100 //                //: cam_cell.h*(num_rows+1)*(num_cols_fa_cam + sram_cell.get_area()*num_cols_fa_ram));
 101 //                : cam_cell.get_area()*(num_rows+1)*(num_cols_fa_cam + num_cols_fa_ram));
 102 //                //: cam_cell.get_area()*(num_rows+1)*num_cols_fa_cam + sram_cell.get_area()*(num_rows+1)*num_cols_fa_ram);//for FA, this area does not include the dummy cells in SRAM arrays.
 103
 104     if (!(is_fa || dp.pure_cam))
 105           return (cell.get_area() * num_rows * num_cols);
 106     else if (is_fa)
 107     { //for FA, this area includes the dummy cells in SRAM arrays.
 108       //return (cam_cell.get_area()*(num_rows+1)*(num_cols_fa_cam + num_cols_fa_ram));
 109       //cout<<"diff" <<cam_cell.get_area()*(num_rows+1)*(num_cols_fa_cam + num_cols_fa_ram)- cam_cell.h*(num_rows+1)*(cam_cell.w*num_cols_fa_cam + cell.w*num_cols_fa_ram)<<endl;
 110       return (cam_cell.h*(num_rows+1)*(cam_cell.w*num_cols_fa_cam + cell.w*num_cols_fa_ram));
 111     }
 112     else
 113       return (cam_cell.get_area()*(num_rows+1)*num_cols_fa_cam );
 114
 115
 116 }
 117
 118
 119
 120 void Subarray::compute_C()
 121 {
 122   double c_w_metal = cell.w * g_tp.wire_local.C_per_um;
 123   double r_w_metal = cell.w * g_tp.wire_local.R_per_um;
 124   double C_b_metal = cell.h * g_tp.wire_local.C_per_um;
 125   double C_b_row_drain_C;
 126
 127   if (dp.is_dram)
 128   {
 129     C_wl = (gate_C_pass(g_tp.dram.cell_a_w, g_tp.dram.b_w, true, true) + c_w_metal) * num_cols;
 130
 131     if (dp.ram_cell_tech_type == comm_dram)
 132     {
 133       C_bl = num_rows * C_b_metal;
 134     }
 135     else
 136     {
 137       C_b_row_drain_C = drain_C_(g_tp.dram.cell_a_w, NCH, 1, 0, cell.w, true, true) / 2.0;  // due to shared contact
 138       C_bl = num_rows * (C_b_row_drain_C + C_b_metal);
 139     }
 140   }
 141   else
 142   {
 143           if (!(is_fa ||dp.pure_cam))
 144           {
 145                   C_wl = (gate_C_pass(g_tp.sram.cell_a_w, (g_tp.sram.b_w-2*g_tp.sram.cell_a_w)/2.0, false, true)*2 +
 146                                   c_w_metal) * num_cols;
 147                   C_b_row_drain_C = drain_C_(g_tp.sram.cell_a_w, NCH, 1, 0, cell.w, false, true) / 2.0;  // due to shared contact
 148                   C_bl = num_rows * (C_b_row_drain_C + C_b_metal);
 149           }
 150           else
 151           {
 152                  //Following is wordline not matchline
 153                  //CAM portion
 154                  c_w_metal = cam_cell.w * g_tp.wire_local.C_per_um;
 155                  r_w_metal = cam_cell.w * g_tp.wire_local.R_per_um;
 156          C_wl_cam = (gate_C_pass(g_tp.cam.cell_a_w, (g_tp.cam.b_w-2*g_tp.cam.cell_a_w)/2.0, false, true)*2 +
 157                                   c_w_metal) * num_cols_fa_cam;
 158          R_wl_cam = (r_w_metal) * num_cols_fa_cam;
 159
 160          if (!dp.pure_cam)
 161          {
 162                  //RAM portion
 163                  c_w_metal = cell.w * g_tp.wire_local.C_per_um;
 164                  r_w_metal = cell.w * g_tp.wire_local.R_per_um;
 165                  C_wl_ram = (gate_C_pass(g_tp.sram.cell_a_w, (g_tp.sram.b_w-2*g_tp.sram.cell_a_w)/2.0, false, true)*2 +
 166                                  c_w_metal) * num_cols_fa_ram;
 167                  R_wl_ram = (r_w_metal) * num_cols_fa_ram;
 168          }
 169          else
 170          {
 171                  C_wl_ram = R_wl_ram =0;
 172          }
 173          C_wl = C_wl_cam + C_wl_ram;
 174          C_wl += (16+128)*g_tp.wire_local.pitch*g_tp.wire_local.C_per_um;
 175
 176          R_wl = R_wl_cam + R_wl_ram;
 177          R_wl += (16+128)*g_tp.wire_local.pitch*g_tp.wire_local.R_per_um;
 178
 179          //there are two ways to write to a FA,
 180          //1) Write to CAM array then force a match on match line to active the corresponding wordline in RAM;
 181          //2) using separate wordline for read/write and search in RAM.
 182          //We are using the second approach.
 183
 184          //Bitline CAM portion This is bitline not searchline. We assume no sharing between bitline and searchline according to SUN's implementations.
 185          C_b_metal = cam_cell.h * g_tp.wire_local.C_per_um;
 186          C_b_row_drain_C = drain_C_(g_tp.cam.cell_a_w, NCH, 1, 0, cam_cell.w, false, true) / 2.0;  // due to shared contact
 187          C_bl_cam = (num_rows+1) * (C_b_row_drain_C + C_b_metal);
 188          //height of subarray is decided by CAM array. blank space in sram array are filled with dummy cells
 189          C_b_row_drain_C = drain_C_(g_tp.sram.cell_a_w, NCH, 1, 0, cell.w, false, true) / 2.0;  // due to shared contact
 190          C_bl = (num_rows +1) * (C_b_row_drain_C + C_b_metal);
 191
 192           }
 193   }
 194 }
 195
 196