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[gem5.git] / ext / mcpat / cacti / technology.cc
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31
32
33 #include "basic_circuit.h"
34
35 #include "parameter.h"
36
37 double wire_resistance(double resistivity, double wire_width, double wire_thickness,
38 double barrier_thickness, double dishing_thickness, double alpha_scatter)
39 {
40 double resistance;
41 resistance = alpha_scatter * resistivity /((wire_thickness - barrier_thickness - dishing_thickness)*(wire_width - 2 * barrier_thickness));
42 return(resistance);
43 }
44
45 double wire_capacitance(double wire_width, double wire_thickness, double wire_spacing,
46 double ild_thickness, double miller_value, double horiz_dielectric_constant,
47 double vert_dielectric_constant, double fringe_cap)
48 {
49 double vertical_cap, sidewall_cap, total_cap;
50 vertical_cap = 2 * PERMITTIVITY_FREE_SPACE * vert_dielectric_constant * wire_width / ild_thickness;
51 sidewall_cap = 2 * PERMITTIVITY_FREE_SPACE * miller_value * horiz_dielectric_constant * wire_thickness / wire_spacing;
52 total_cap = vertical_cap + sidewall_cap + fringe_cap;
53 return(total_cap);
54 }
55
56
57 void init_tech_params(double technology, bool is_tag)
58 {
59 int iter, tech, tech_lo, tech_hi;
60 double curr_alpha, curr_vpp;
61 double wire_width, wire_thickness, wire_spacing,
62 fringe_cap, pmos_to_nmos_sizing_r;
63 // double aspect_ratio,ild_thickness, miller_value = 1.5, horiz_dielectric_constant, vert_dielectric_constant;
64 double barrier_thickness, dishing_thickness, alpha_scatter;
65 double curr_vdd_dram_cell, curr_v_th_dram_access_transistor, curr_I_on_dram_cell, curr_c_dram_cell;
66
67 uint32_t ram_cell_tech_type = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type : g_ip->data_arr_ram_cell_tech_type;
68 uint32_t peri_global_tech_type = (is_tag) ? g_ip->tag_arr_peri_global_tech_type : g_ip->data_arr_peri_global_tech_type;
69
70 technology = technology * 1000.0; // in the unit of nm
71
72 // initialize parameters
73 g_tp.reset();
74 double gmp_to_gmn_multiplier_periph_global = 0;
75
76 double curr_Wmemcella_dram, curr_Wmemcellpmos_dram, curr_Wmemcellnmos_dram,
77 curr_area_cell_dram, curr_asp_ratio_cell_dram, curr_Wmemcella_sram,
78 curr_Wmemcellpmos_sram, curr_Wmemcellnmos_sram, curr_area_cell_sram,
79 curr_asp_ratio_cell_sram, curr_I_off_dram_cell_worst_case_length_temp;
80 double curr_Wmemcella_cam, curr_Wmemcellpmos_cam, curr_Wmemcellnmos_cam, curr_area_cell_cam,//Sheng: CAM data
81 curr_asp_ratio_cell_cam;
82 double SENSE_AMP_D, SENSE_AMP_P; // J
83 double area_cell_dram = 0;
84 double asp_ratio_cell_dram = 0;
85 double area_cell_sram = 0;
86 double asp_ratio_cell_sram = 0;
87 double area_cell_cam = 0;
88 double asp_ratio_cell_cam = 0;
89 double mobility_eff_periph_global = 0;
90 double Vdsat_periph_global = 0;
91 double nmos_effective_resistance_multiplier;
92 double width_dram_access_transistor;
93
94 double curr_logic_scaling_co_eff = 0;//This is based on the reported numbers of Intel Merom 65nm, Penryn45nm and IBM cell 90/65/45 date
95 double curr_core_tx_density = 0;//this is density per um^2; 90, ...22nm based on Intel Penryn
96 double curr_chip_layout_overhead = 0;
97 double curr_macro_layout_overhead = 0;
98 double curr_sckt_co_eff = 0;
99
100 if (technology < 181 && technology > 179)
101 {
102 tech_lo = 180;
103 tech_hi = 180;
104 }
105 else if (technology < 91 && technology > 89)
106 {
107 tech_lo = 90;
108 tech_hi = 90;
109 }
110 else if (technology < 66 && technology > 64)
111 {
112 tech_lo = 65;
113 tech_hi = 65;
114 }
115 else if (technology < 46 && technology > 44)
116 {
117 tech_lo = 45;
118 tech_hi = 45;
119 }
120 else if (technology < 33 && technology > 31)
121 {
122 tech_lo = 32;
123 tech_hi = 32;
124 }
125 else if (technology < 23 && technology > 21)
126 {
127 tech_lo = 22;
128 tech_hi = 22;
129 if (ram_cell_tech_type == 3 )
130 {
131 cout<<"current version does not support eDRAM technologies at 22nm"<<endl;
132 exit(0);
133 }
134 }
135 // else if (technology < 17 && technology > 15)
136 // {
137 // tech_lo = 16;
138 // tech_hi = 16;
139 // }
140 else if (technology < 180 && technology > 90)
141 {
142 tech_lo = 180;
143 tech_hi = 90;
144 }
145 else if (technology < 90 && technology > 65)
146 {
147 tech_lo = 90;
148 tech_hi = 65;
149 }
150 else if (technology < 65 && technology > 45)
151 {
152 tech_lo = 65;
153 tech_hi = 45;
154 }
155 else if (technology < 45 && technology > 32)
156 {
157 tech_lo = 45;
158 tech_hi = 32;
159 }
160 else if (technology < 32 && technology > 22)
161 {
162 tech_lo = 32;
163 tech_hi = 22;
164 }
165 // else if (technology < 22 && technology > 16)
166 // {
167 // tech_lo = 22;
168 // tech_hi = 16;
169 // }
170 else
171 {
172 cout<<"Invalid technology nodes"<<endl;
173 exit(0);
174 }
175
176 double vdd[NUMBER_TECH_FLAVORS];
177 double Lphy[NUMBER_TECH_FLAVORS];
178 double Lelec[NUMBER_TECH_FLAVORS];
179 double t_ox[NUMBER_TECH_FLAVORS];
180 double v_th[NUMBER_TECH_FLAVORS];
181 double c_ox[NUMBER_TECH_FLAVORS];
182 double mobility_eff[NUMBER_TECH_FLAVORS];
183 double Vdsat[NUMBER_TECH_FLAVORS];
184 double c_g_ideal[NUMBER_TECH_FLAVORS];
185 double c_fringe[NUMBER_TECH_FLAVORS];
186 double c_junc[NUMBER_TECH_FLAVORS];
187 double I_on_n[NUMBER_TECH_FLAVORS];
188 double I_on_p[NUMBER_TECH_FLAVORS];
189 double Rnchannelon[NUMBER_TECH_FLAVORS];
190 double Rpchannelon[NUMBER_TECH_FLAVORS];
191 double n_to_p_eff_curr_drv_ratio[NUMBER_TECH_FLAVORS];
192 double I_off_n[NUMBER_TECH_FLAVORS][101];
193 double I_g_on_n[NUMBER_TECH_FLAVORS][101];
194 //double I_off_p[NUMBER_TECH_FLAVORS][101];
195 double gmp_to_gmn_multiplier[NUMBER_TECH_FLAVORS];
196 //double curr_sckt_co_eff[NUMBER_TECH_FLAVORS];
197 double long_channel_leakage_reduction[NUMBER_TECH_FLAVORS];
198
199 for (iter = 0; iter <= 1; ++iter)
200 {
201 // linear interpolation
202 if (iter == 0)
203 {
204 tech = tech_lo;
205 if (tech_lo == tech_hi)
206 {
207 curr_alpha = 1;
208 }
209 else
210 {
211 curr_alpha = (technology - tech_hi)/(tech_lo - tech_hi);
212 }
213 }
214 else
215 {
216 tech = tech_hi;
217 if (tech_lo == tech_hi)
218 {
219 break;
220 }
221 else
222 {
223 curr_alpha = (tech_lo - technology)/(tech_lo - tech_hi);
224 }
225 }
226
227 if (tech == 180)
228 {
229 //180nm technology-node. Corresponds to year 1999 in ITRS
230 //Only HP transistor was of interest that 180nm since leakage power was not a big issue. Performance was the king
231 //MASTAR does not contain data for 0.18um process. The following parameters are projected based on ITRS 2000 update and IBM 0.18 Cu Spice input
232 bool Aggre_proj = false;
233 SENSE_AMP_D = .28e-9; // s
234 SENSE_AMP_P = 14.7e-15; // J
235 vdd[0] = 1.5;
236 Lphy[0] = 0.12;//Lphy is the physical gate-length. micron
237 Lelec[0] = 0.10;//Lelec is the electrical gate-length. micron
238 t_ox[0] = 1.2e-3*(Aggre_proj? 1.9/1.2:2);//micron
239 v_th[0] = Aggre_proj? 0.36 : 0.4407;//V
240 c_ox[0] = 1.79e-14*(Aggre_proj? 1.9/1.2:2);//F/micron2
241 mobility_eff[0] = 302.16 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs
242 Vdsat[0] = 0.128*2; //V
243 c_g_ideal[0] = (Aggre_proj? 1.9/1.2:2)*6.64e-16;//F/micron
244 c_fringe[0] = (Aggre_proj? 1.9/1.2:2)*0.08e-15;//F/micron
245 c_junc[0] = (Aggre_proj? 1.9/1.2:2)*1e-15;//F/micron2
246 I_on_n[0] = 750e-6;//A/micron
247 I_on_p[0] = 350e-6;//A/micron
248 //Note that nmos_effective_resistance_multiplier, n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are calculated offline
249 nmos_effective_resistance_multiplier = 1.54;
250 n_to_p_eff_curr_drv_ratio[0] = 2.45;
251 gmp_to_gmn_multiplier[0] = 1.22;
252 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron
253 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron
254 long_channel_leakage_reduction[0] = 1;
255 I_off_n[0][0] = 7e-10;//A/micron
256 I_off_n[0][10] = 8.26e-10;
257 I_off_n[0][20] = 9.74e-10;
258 I_off_n[0][30] = 1.15e-9;
259 I_off_n[0][40] = 1.35e-9;
260 I_off_n[0][50] = 1.60e-9;
261 I_off_n[0][60] = 1.88e-9;
262 I_off_n[0][70] = 2.29e-9;
263 I_off_n[0][80] = 2.70e-9;
264 I_off_n[0][90] = 3.19e-9;
265 I_off_n[0][100] = 3.76e-9;
266
267 I_g_on_n[0][0] = 1.65e-10;//A/micron
268 I_g_on_n[0][10] = 1.65e-10;
269 I_g_on_n[0][20] = 1.65e-10;
270 I_g_on_n[0][30] = 1.65e-10;
271 I_g_on_n[0][40] = 1.65e-10;
272 I_g_on_n[0][50] = 1.65e-10;
273 I_g_on_n[0][60] = 1.65e-10;
274 I_g_on_n[0][70] = 1.65e-10;
275 I_g_on_n[0][80] = 1.65e-10;
276 I_g_on_n[0][90] = 1.65e-10;
277 I_g_on_n[0][100] = 1.65e-10;
278
279 //SRAM cell properties
280 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
281 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
282 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
283 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
284 curr_asp_ratio_cell_sram = 1.46;
285 //CAM cell properties //TODO: data need to be revisited
286 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um;
287 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um;
288 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um;
289 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;//360
290 curr_asp_ratio_cell_cam = 2.92;//2.5
291 //Empirical undifferetiated core/FU coefficient
292 curr_logic_scaling_co_eff = 1.5;//linear scaling from 90nm
293 curr_core_tx_density = 1.25*0.7*0.7*0.4;
294 curr_sckt_co_eff = 1.11;
295 curr_chip_layout_overhead = 1.0;//die measurement results based on Niagara 1 and 2
296 curr_macro_layout_overhead = 1.0;//EDA placement and routing tool rule of thumb
297
298 }
299
300 if (tech == 90)
301 {
302 SENSE_AMP_D = .28e-9; // s
303 SENSE_AMP_P = 14.7e-15; // J
304 //90nm technology-node. Corresponds to year 2004 in ITRS
305 //ITRS HP device type
306 vdd[0] = 1.2;
307 Lphy[0] = 0.037;//Lphy is the physical gate-length. micron
308 Lelec[0] = 0.0266;//Lelec is the electrical gate-length. micron
309 t_ox[0] = 1.2e-3;//micron
310 v_th[0] = 0.23707;//V
311 c_ox[0] = 1.79e-14;//F/micron2
312 mobility_eff[0] = 342.16 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs
313 Vdsat[0] = 0.128; //V
314 c_g_ideal[0] = 6.64e-16;//F/micron
315 c_fringe[0] = 0.08e-15;//F/micron
316 c_junc[0] = 1e-15;//F/micron2
317 I_on_n[0] = 1076.9e-6;//A/micron
318 I_on_p[0] = 712.6e-6;//A/micron
319 //Note that nmos_effective_resistance_multiplier, n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are calculated offline
320 nmos_effective_resistance_multiplier = 1.54;
321 n_to_p_eff_curr_drv_ratio[0] = 2.45;
322 gmp_to_gmn_multiplier[0] = 1.22;
323 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron
324 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron
325 long_channel_leakage_reduction[0] = 1;
326 I_off_n[0][0] = 3.24e-8;//A/micron
327 I_off_n[0][10] = 4.01e-8;
328 I_off_n[0][20] = 4.90e-8;
329 I_off_n[0][30] = 5.92e-8;
330 I_off_n[0][40] = 7.08e-8;
331 I_off_n[0][50] = 8.38e-8;
332 I_off_n[0][60] = 9.82e-8;
333 I_off_n[0][70] = 1.14e-7;
334 I_off_n[0][80] = 1.29e-7;
335 I_off_n[0][90] = 1.43e-7;
336 I_off_n[0][100] = 1.54e-7;
337
338 I_g_on_n[0][0] = 1.65e-8;//A/micron
339 I_g_on_n[0][10] = 1.65e-8;
340 I_g_on_n[0][20] = 1.65e-8;
341 I_g_on_n[0][30] = 1.65e-8;
342 I_g_on_n[0][40] = 1.65e-8;
343 I_g_on_n[0][50] = 1.65e-8;
344 I_g_on_n[0][60] = 1.65e-8;
345 I_g_on_n[0][70] = 1.65e-8;
346 I_g_on_n[0][80] = 1.65e-8;
347 I_g_on_n[0][90] = 1.65e-8;
348 I_g_on_n[0][100] = 1.65e-8;
349
350 //ITRS LSTP device type
351 vdd[1] = 1.3;
352 Lphy[1] = 0.075;
353 Lelec[1] = 0.0486;
354 t_ox[1] = 2.2e-3;
355 v_th[1] = 0.48203;
356 c_ox[1] = 1.22e-14;
357 mobility_eff[1] = 356.76 * (1e-2 * 1e6 * 1e-2 * 1e6);
358 Vdsat[1] = 0.373;
359 c_g_ideal[1] = 9.15e-16;
360 c_fringe[1] = 0.08e-15;
361 c_junc[1] = 1e-15;
362 I_on_n[1] = 503.6e-6;
363 I_on_p[1] = 235.1e-6;
364 nmos_effective_resistance_multiplier = 1.92;
365 n_to_p_eff_curr_drv_ratio[1] = 2.44;
366 gmp_to_gmn_multiplier[1] =0.88;
367 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];
368 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];
369 long_channel_leakage_reduction[1] = 1;
370 I_off_n[1][0] = 2.81e-12;
371 I_off_n[1][10] = 4.76e-12;
372 I_off_n[1][20] = 7.82e-12;
373 I_off_n[1][30] = 1.25e-11;
374 I_off_n[1][40] = 1.94e-11;
375 I_off_n[1][50] = 2.94e-11;
376 I_off_n[1][60] = 4.36e-11;
377 I_off_n[1][70] = 6.32e-11;
378 I_off_n[1][80] = 8.95e-11;
379 I_off_n[1][90] = 1.25e-10;
380 I_off_n[1][100] = 1.7e-10;
381
382 I_g_on_n[1][0] = 3.87e-11;//A/micron
383 I_g_on_n[1][10] = 3.87e-11;
384 I_g_on_n[1][20] = 3.87e-11;
385 I_g_on_n[1][30] = 3.87e-11;
386 I_g_on_n[1][40] = 3.87e-11;
387 I_g_on_n[1][50] = 3.87e-11;
388 I_g_on_n[1][60] = 3.87e-11;
389 I_g_on_n[1][70] = 3.87e-11;
390 I_g_on_n[1][80] = 3.87e-11;
391 I_g_on_n[1][90] = 3.87e-11;
392 I_g_on_n[1][100] = 3.87e-11;
393
394 //ITRS LOP device type
395 vdd[2] = 0.9;
396 Lphy[2] = 0.053;
397 Lelec[2] = 0.0354;
398 t_ox[2] = 1.5e-3;
399 v_th[2] = 0.30764;
400 c_ox[2] = 1.59e-14;
401 mobility_eff[2] = 460.39 * (1e-2 * 1e6 * 1e-2 * 1e6);
402 Vdsat[2] = 0.113;
403 c_g_ideal[2] = 8.45e-16;
404 c_fringe[2] = 0.08e-15;
405 c_junc[2] = 1e-15;
406 I_on_n[2] = 386.6e-6;
407 I_on_p[2] = 209.7e-6;
408 nmos_effective_resistance_multiplier = 1.77;
409 n_to_p_eff_curr_drv_ratio[2] = 2.54;
410 gmp_to_gmn_multiplier[2] = 0.98;
411 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];
412 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];
413 long_channel_leakage_reduction[2] = 1;
414 I_off_n[2][0] = 2.14e-9;
415 I_off_n[2][10] = 2.9e-9;
416 I_off_n[2][20] = 3.87e-9;
417 I_off_n[2][30] = 5.07e-9;
418 I_off_n[2][40] = 6.54e-9;
419 I_off_n[2][50] = 8.27e-8;
420 I_off_n[2][60] = 1.02e-7;
421 I_off_n[2][70] = 1.20e-7;
422 I_off_n[2][80] = 1.36e-8;
423 I_off_n[2][90] = 1.52e-8;
424 I_off_n[2][100] = 1.73e-8;
425
426 I_g_on_n[2][0] = 4.31e-8;//A/micron
427 I_g_on_n[2][10] = 4.31e-8;
428 I_g_on_n[2][20] = 4.31e-8;
429 I_g_on_n[2][30] = 4.31e-8;
430 I_g_on_n[2][40] = 4.31e-8;
431 I_g_on_n[2][50] = 4.31e-8;
432 I_g_on_n[2][60] = 4.31e-8;
433 I_g_on_n[2][70] = 4.31e-8;
434 I_g_on_n[2][80] = 4.31e-8;
435 I_g_on_n[2][90] = 4.31e-8;
436 I_g_on_n[2][100] = 4.31e-8;
437
438 if (ram_cell_tech_type == lp_dram)
439 {
440 //LP-DRAM cell access transistor technology parameters
441 curr_vdd_dram_cell = 1.2;
442 Lphy[3] = 0.12;
443 Lelec[3] = 0.0756;
444 curr_v_th_dram_access_transistor = 0.4545;
445 width_dram_access_transistor = 0.14;
446 curr_I_on_dram_cell = 45e-6;
447 curr_I_off_dram_cell_worst_case_length_temp = 21.1e-12;
448 curr_Wmemcella_dram = width_dram_access_transistor;
449 curr_Wmemcellpmos_dram = 0;
450 curr_Wmemcellnmos_dram = 0;
451 curr_area_cell_dram = 0.168;
452 curr_asp_ratio_cell_dram = 1.46;
453 curr_c_dram_cell = 20e-15;
454
455 //LP-DRAM wordline transistor parameters
456 curr_vpp = 1.6;
457 t_ox[3] = 2.2e-3;
458 v_th[3] = 0.4545;
459 c_ox[3] = 1.22e-14;
460 mobility_eff[3] = 323.95 * (1e-2 * 1e6 * 1e-2 * 1e6);
461 Vdsat[3] = 0.3;
462 c_g_ideal[3] = 1.47e-15;
463 c_fringe[3] = 0.08e-15;
464 c_junc[3] = 1e-15;
465 I_on_n[3] = 321.6e-6;
466 I_on_p[3] = 203.3e-6;
467 nmos_effective_resistance_multiplier = 1.65;
468 n_to_p_eff_curr_drv_ratio[3] = 1.95;
469 gmp_to_gmn_multiplier[3] = 0.90;
470 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
471 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
472 long_channel_leakage_reduction[3] = 1;
473 I_off_n[3][0] = 1.42e-11;
474 I_off_n[3][10] = 2.25e-11;
475 I_off_n[3][20] = 3.46e-11;
476 I_off_n[3][30] = 5.18e-11;
477 I_off_n[3][40] = 7.58e-11;
478 I_off_n[3][50] = 1.08e-10;
479 I_off_n[3][60] = 1.51e-10;
480 I_off_n[3][70] = 2.02e-10;
481 I_off_n[3][80] = 2.57e-10;
482 I_off_n[3][90] = 3.14e-10;
483 I_off_n[3][100] = 3.85e-10;
484 }
485 else if (ram_cell_tech_type == comm_dram)
486 {
487 //COMM-DRAM cell access transistor technology parameters
488 curr_vdd_dram_cell = 1.6;
489 Lphy[3] = 0.09;
490 Lelec[3] = 0.0576;
491 curr_v_th_dram_access_transistor = 1;
492 width_dram_access_transistor = 0.09;
493 curr_I_on_dram_cell = 20e-6;
494 curr_I_off_dram_cell_worst_case_length_temp = 1e-15;
495 curr_Wmemcella_dram = width_dram_access_transistor;
496 curr_Wmemcellpmos_dram = 0;
497 curr_Wmemcellnmos_dram = 0;
498 curr_area_cell_dram = 6*0.09*0.09;
499 curr_asp_ratio_cell_dram = 1.5;
500 curr_c_dram_cell = 30e-15;
501
502 //COMM-DRAM wordline transistor parameters
503 curr_vpp = 3.7;
504 t_ox[3] = 5.5e-3;
505 v_th[3] = 1.0;
506 c_ox[3] = 5.65e-15;
507 mobility_eff[3] = 302.2 * (1e-2 * 1e6 * 1e-2 * 1e6);
508 Vdsat[3] = 0.32;
509 c_g_ideal[3] = 5.08e-16;
510 c_fringe[3] = 0.08e-15;
511 c_junc[3] = 1e-15;
512 I_on_n[3] = 1094.3e-6;
513 I_on_p[3] = I_on_n[3] / 2;
514 nmos_effective_resistance_multiplier = 1.62;
515 n_to_p_eff_curr_drv_ratio[3] = 2.05;
516 gmp_to_gmn_multiplier[3] = 0.90;
517 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
518 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
519 long_channel_leakage_reduction[3] = 1;
520 I_off_n[3][0] = 5.80e-15;
521 I_off_n[3][10] = 1.21e-14;
522 I_off_n[3][20] = 2.42e-14;
523 I_off_n[3][30] = 4.65e-14;
524 I_off_n[3][40] = 8.60e-14;
525 I_off_n[3][50] = 1.54e-13;
526 I_off_n[3][60] = 2.66e-13;
527 I_off_n[3][70] = 4.45e-13;
528 I_off_n[3][80] = 7.17e-13;
529 I_off_n[3][90] = 1.11e-12;
530 I_off_n[3][100] = 1.67e-12;
531 }
532
533 //SRAM cell properties
534 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
535 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
536 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
537 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
538 curr_asp_ratio_cell_sram = 1.46;
539 //CAM cell properties //TODO: data need to be revisited
540 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um;
541 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um;
542 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um;
543 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;//360
544 curr_asp_ratio_cell_cam = 2.92;//2.5
545 //Empirical undifferetiated core/FU coefficient
546 curr_logic_scaling_co_eff = 1;
547 curr_core_tx_density = 1.25*0.7*0.7;
548 curr_sckt_co_eff = 1.1539;
549 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2
550 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb
551
552
553 }
554
555 if (tech == 65)
556 { //65nm technology-node. Corresponds to year 2007 in ITRS
557 //ITRS HP device type
558 SENSE_AMP_D = .2e-9; // s
559 SENSE_AMP_P = 5.7e-15; // J
560 vdd[0] = 1.1;
561 Lphy[0] = 0.025;
562 Lelec[0] = 0.019;
563 t_ox[0] = 1.1e-3;
564 v_th[0] = .19491;
565 c_ox[0] = 1.88e-14;
566 mobility_eff[0] = 436.24 * (1e-2 * 1e6 * 1e-2 * 1e6);
567 Vdsat[0] = 7.71e-2;
568 c_g_ideal[0] = 4.69e-16;
569 c_fringe[0] = 0.077e-15;
570 c_junc[0] = 1e-15;
571 I_on_n[0] = 1197.2e-6;
572 I_on_p[0] = 870.8e-6;
573 nmos_effective_resistance_multiplier = 1.50;
574 n_to_p_eff_curr_drv_ratio[0] = 2.41;
575 gmp_to_gmn_multiplier[0] = 1.38;
576 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];
577 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];
578 long_channel_leakage_reduction[0] = 1/3.74;
579 //Using MASTAR, @380K, increase Lgate until Ion reduces to 90% or Lgate increase by 10%, whichever comes first
580 //Ioff(Lgate normal)/Ioff(Lgate long)= 3.74.
581 I_off_n[0][0] = 1.96e-7;
582 I_off_n[0][10] = 2.29e-7;
583 I_off_n[0][20] = 2.66e-7;
584 I_off_n[0][30] = 3.05e-7;
585 I_off_n[0][40] = 3.49e-7;
586 I_off_n[0][50] = 3.95e-7;
587 I_off_n[0][60] = 4.45e-7;
588 I_off_n[0][70] = 4.97e-7;
589 I_off_n[0][80] = 5.48e-7;
590 I_off_n[0][90] = 5.94e-7;
591 I_off_n[0][100] = 6.3e-7;
592 I_g_on_n[0][0] = 4.09e-8;//A/micron
593 I_g_on_n[0][10] = 4.09e-8;
594 I_g_on_n[0][20] = 4.09e-8;
595 I_g_on_n[0][30] = 4.09e-8;
596 I_g_on_n[0][40] = 4.09e-8;
597 I_g_on_n[0][50] = 4.09e-8;
598 I_g_on_n[0][60] = 4.09e-8;
599 I_g_on_n[0][70] = 4.09e-8;
600 I_g_on_n[0][80] = 4.09e-8;
601 I_g_on_n[0][90] = 4.09e-8;
602 I_g_on_n[0][100] = 4.09e-8;
603
604 //ITRS LSTP device type
605 vdd[1] = 1.2;
606 Lphy[1] = 0.045;
607 Lelec[1] = 0.0298;
608 t_ox[1] = 1.9e-3;
609 v_th[1] = 0.52354;
610 c_ox[1] = 1.36e-14;
611 mobility_eff[1] = 341.21 * (1e-2 * 1e6 * 1e-2 * 1e6);
612 Vdsat[1] = 0.128;
613 c_g_ideal[1] = 6.14e-16;
614 c_fringe[1] = 0.08e-15;
615 c_junc[1] = 1e-15;
616 I_on_n[1] = 519.2e-6;
617 I_on_p[1] = 266e-6;
618 nmos_effective_resistance_multiplier = 1.96;
619 n_to_p_eff_curr_drv_ratio[1] = 2.23;
620 gmp_to_gmn_multiplier[1] = 0.99;
621 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];
622 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];
623 long_channel_leakage_reduction[1] = 1/2.82;
624 I_off_n[1][0] = 9.12e-12;
625 I_off_n[1][10] = 1.49e-11;
626 I_off_n[1][20] = 2.36e-11;
627 I_off_n[1][30] = 3.64e-11;
628 I_off_n[1][40] = 5.48e-11;
629 I_off_n[1][50] = 8.05e-11;
630 I_off_n[1][60] = 1.15e-10;
631 I_off_n[1][70] = 1.59e-10;
632 I_off_n[1][80] = 2.1e-10;
633 I_off_n[1][90] = 2.62e-10;
634 I_off_n[1][100] = 3.21e-10;
635
636 I_g_on_n[1][0] = 1.09e-10;//A/micron
637 I_g_on_n[1][10] = 1.09e-10;
638 I_g_on_n[1][20] = 1.09e-10;
639 I_g_on_n[1][30] = 1.09e-10;
640 I_g_on_n[1][40] = 1.09e-10;
641 I_g_on_n[1][50] = 1.09e-10;
642 I_g_on_n[1][60] = 1.09e-10;
643 I_g_on_n[1][70] = 1.09e-10;
644 I_g_on_n[1][80] = 1.09e-10;
645 I_g_on_n[1][90] = 1.09e-10;
646 I_g_on_n[1][100] = 1.09e-10;
647
648 //ITRS LOP device type
649 vdd[2] = 0.8;
650 Lphy[2] = 0.032;
651 Lelec[2] = 0.0216;
652 t_ox[2] = 1.2e-3;
653 v_th[2] = 0.28512;
654 c_ox[2] = 1.87e-14;
655 mobility_eff[2] = 495.19 * (1e-2 * 1e6 * 1e-2 * 1e6);
656 Vdsat[2] = 0.292;
657 c_g_ideal[2] = 6e-16;
658 c_fringe[2] = 0.08e-15;
659 c_junc[2] = 1e-15;
660 I_on_n[2] = 573.1e-6;
661 I_on_p[2] = 340.6e-6;
662 nmos_effective_resistance_multiplier = 1.82;
663 n_to_p_eff_curr_drv_ratio[2] = 2.28;
664 gmp_to_gmn_multiplier[2] = 1.11;
665 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];
666 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];
667 long_channel_leakage_reduction[2] = 1/2.05;
668 I_off_n[2][0] = 4.9e-9;
669 I_off_n[2][10] = 6.49e-9;
670 I_off_n[2][20] = 8.45e-9;
671 I_off_n[2][30] = 1.08e-8;
672 I_off_n[2][40] = 1.37e-8;
673 I_off_n[2][50] = 1.71e-8;
674 I_off_n[2][60] = 2.09e-8;
675 I_off_n[2][70] = 2.48e-8;
676 I_off_n[2][80] = 2.84e-8;
677 I_off_n[2][90] = 3.13e-8;
678 I_off_n[2][100] = 3.42e-8;
679
680 I_g_on_n[2][0] = 9.61e-9;//A/micron
681 I_g_on_n[2][10] = 9.61e-9;
682 I_g_on_n[2][20] = 9.61e-9;
683 I_g_on_n[2][30] = 9.61e-9;
684 I_g_on_n[2][40] = 9.61e-9;
685 I_g_on_n[2][50] = 9.61e-9;
686 I_g_on_n[2][60] = 9.61e-9;
687 I_g_on_n[2][70] = 9.61e-9;
688 I_g_on_n[2][80] = 9.61e-9;
689 I_g_on_n[2][90] = 9.61e-9;
690 I_g_on_n[2][100] = 9.61e-9;
691
692 if (ram_cell_tech_type == lp_dram)
693 {
694 //LP-DRAM cell access transistor technology parameters
695 curr_vdd_dram_cell = 1.2;
696 Lphy[3] = 0.12;
697 Lelec[3] = 0.0756;
698 curr_v_th_dram_access_transistor = 0.43806;
699 width_dram_access_transistor = 0.09;
700 curr_I_on_dram_cell = 36e-6;
701 curr_I_off_dram_cell_worst_case_length_temp = 19.6e-12;
702 curr_Wmemcella_dram = width_dram_access_transistor;
703 curr_Wmemcellpmos_dram = 0;
704 curr_Wmemcellnmos_dram = 0;
705 curr_area_cell_dram = 0.11;
706 curr_asp_ratio_cell_dram = 1.46;
707 curr_c_dram_cell = 20e-15;
708
709 //LP-DRAM wordline transistor parameters
710 curr_vpp = 1.6;
711 t_ox[3] = 2.2e-3;
712 v_th[3] = 0.43806;
713 c_ox[3] = 1.22e-14;
714 mobility_eff[3] = 328.32 * (1e-2 * 1e6 * 1e-2 * 1e6);
715 Vdsat[3] = 0.43806;
716 c_g_ideal[3] = 1.46e-15;
717 c_fringe[3] = 0.08e-15;
718 c_junc[3] = 1e-15 ;
719 I_on_n[3] = 399.8e-6;
720 I_on_p[3] = 243.4e-6;
721 nmos_effective_resistance_multiplier = 1.65;
722 n_to_p_eff_curr_drv_ratio[3] = 2.05;
723 gmp_to_gmn_multiplier[3] = 0.90;
724 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
725 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
726 long_channel_leakage_reduction[3] = 1;
727 I_off_n[3][0] = 2.23e-11;
728 I_off_n[3][10] = 3.46e-11;
729 I_off_n[3][20] = 5.24e-11;
730 I_off_n[3][30] = 7.75e-11;
731 I_off_n[3][40] = 1.12e-10;
732 I_off_n[3][50] = 1.58e-10;
733 I_off_n[3][60] = 2.18e-10;
734 I_off_n[3][70] = 2.88e-10;
735 I_off_n[3][80] = 3.63e-10;
736 I_off_n[3][90] = 4.41e-10;
737 I_off_n[3][100] = 5.36e-10;
738 }
739 else if (ram_cell_tech_type == comm_dram)
740 {
741 //COMM-DRAM cell access transistor technology parameters
742 curr_vdd_dram_cell = 1.3;
743 Lphy[3] = 0.065;
744 Lelec[3] = 0.0426;
745 curr_v_th_dram_access_transistor = 1;
746 width_dram_access_transistor = 0.065;
747 curr_I_on_dram_cell = 20e-6;
748 curr_I_off_dram_cell_worst_case_length_temp = 1e-15;
749 curr_Wmemcella_dram = width_dram_access_transistor;
750 curr_Wmemcellpmos_dram = 0;
751 curr_Wmemcellnmos_dram = 0;
752 curr_area_cell_dram = 6*0.065*0.065;
753 curr_asp_ratio_cell_dram = 1.5;
754 curr_c_dram_cell = 30e-15;
755
756 //COMM-DRAM wordline transistor parameters
757 curr_vpp = 3.3;
758 t_ox[3] = 5e-3;
759 v_th[3] = 1.0;
760 c_ox[3] = 6.16e-15;
761 mobility_eff[3] = 303.44 * (1e-2 * 1e6 * 1e-2 * 1e6);
762 Vdsat[3] = 0.385;
763 c_g_ideal[3] = 4e-16;
764 c_fringe[3] = 0.08e-15;
765 c_junc[3] = 1e-15 ;
766 I_on_n[3] = 1031e-6;
767 I_on_p[3] = I_on_n[3] / 2;
768 nmos_effective_resistance_multiplier = 1.69;
769 n_to_p_eff_curr_drv_ratio[3] = 2.39;
770 gmp_to_gmn_multiplier[3] = 0.90;
771 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
772 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
773 long_channel_leakage_reduction[3] = 1;
774 I_off_n[3][0] = 1.80e-14;
775 I_off_n[3][10] = 3.64e-14;
776 I_off_n[3][20] = 7.03e-14;
777 I_off_n[3][30] = 1.31e-13;
778 I_off_n[3][40] = 2.35e-13;
779 I_off_n[3][50] = 4.09e-13;
780 I_off_n[3][60] = 6.89e-13;
781 I_off_n[3][70] = 1.13e-12;
782 I_off_n[3][80] = 1.78e-12;
783 I_off_n[3][90] = 2.71e-12;
784 I_off_n[3][100] = 3.99e-12;
785 }
786
787 //SRAM cell properties
788 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
789 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
790 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
791 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
792 curr_asp_ratio_cell_sram = 1.46;
793 //CAM cell properties //TODO: data need to be revisited
794 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um;
795 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um;
796 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um;
797 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;
798 curr_asp_ratio_cell_cam = 2.92;
799 //Empirical undifferetiated core/FU coefficient
800 curr_logic_scaling_co_eff = 0.7; //Rather than scale proportionally to square of feature size, only scale linearly according to IBM cell processor
801 curr_core_tx_density = 1.25*0.7;
802 curr_sckt_co_eff = 1.1359;
803 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2
804 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb
805 }
806
807 if (tech == 45)
808 { //45nm technology-node. Corresponds to year 2010 in ITRS
809 //ITRS HP device type
810 SENSE_AMP_D = .04e-9; // s
811 SENSE_AMP_P = 2.7e-15; // J
812 vdd[0] = 1.0;
813 Lphy[0] = 0.018;
814 Lelec[0] = 0.01345;
815 t_ox[0] = 0.65e-3;
816 v_th[0] = .18035;
817 c_ox[0] = 3.77e-14;
818 mobility_eff[0] = 266.68 * (1e-2 * 1e6 * 1e-2 * 1e6);
819 Vdsat[0] = 9.38E-2;
820 c_g_ideal[0] = 6.78e-16;
821 c_fringe[0] = 0.05e-15;
822 c_junc[0] = 1e-15;
823 I_on_n[0] = 2046.6e-6;
824 //There are certain problems with the ITRS PMOS numbers in MASTAR for 45nm. So we are using 65nm values of
825 //n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier for 45nm
826 I_on_p[0] = I_on_n[0] / 2;//This value is fixed arbitrarily but I_on_p is not being used in CACTI
827 nmos_effective_resistance_multiplier = 1.51;
828 n_to_p_eff_curr_drv_ratio[0] = 2.41;
829 gmp_to_gmn_multiplier[0] = 1.38;
830 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];
831 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];
832 long_channel_leakage_reduction[0] = 1/3.546;//Using MASTAR, @380K, increase Lgate until Ion reduces to 90%, Ioff(Lgate normal)/Ioff(Lgate long)= 3.74
833 I_off_n[0][0] = 2.8e-7;
834 I_off_n[0][10] = 3.28e-7;
835 I_off_n[0][20] = 3.81e-7;
836 I_off_n[0][30] = 4.39e-7;
837 I_off_n[0][40] = 5.02e-7;
838 I_off_n[0][50] = 5.69e-7;
839 I_off_n[0][60] = 6.42e-7;
840 I_off_n[0][70] = 7.2e-7;
841 I_off_n[0][80] = 8.03e-7;
842 I_off_n[0][90] = 8.91e-7;
843 I_off_n[0][100] = 9.84e-7;
844
845 I_g_on_n[0][0] = 3.59e-8;//A/micron
846 I_g_on_n[0][10] = 3.59e-8;
847 I_g_on_n[0][20] = 3.59e-8;
848 I_g_on_n[0][30] = 3.59e-8;
849 I_g_on_n[0][40] = 3.59e-8;
850 I_g_on_n[0][50] = 3.59e-8;
851 I_g_on_n[0][60] = 3.59e-8;
852 I_g_on_n[0][70] = 3.59e-8;
853 I_g_on_n[0][80] = 3.59e-8;
854 I_g_on_n[0][90] = 3.59e-8;
855 I_g_on_n[0][100] = 3.59e-8;
856
857 //ITRS LSTP device type
858 vdd[1] = 1.1;
859 Lphy[1] = 0.028;
860 Lelec[1] = 0.0212;
861 t_ox[1] = 1.4e-3;
862 v_th[1] = 0.50245;
863 c_ox[1] = 2.01e-14;
864 mobility_eff[1] = 363.96 * (1e-2 * 1e6 * 1e-2 * 1e6);
865 Vdsat[1] = 9.12e-2;
866 c_g_ideal[1] = 5.18e-16;
867 c_fringe[1] = 0.08e-15;
868 c_junc[1] = 1e-15;
869 I_on_n[1] = 666.2e-6;
870 I_on_p[1] = I_on_n[1] / 2;
871 nmos_effective_resistance_multiplier = 1.99;
872 n_to_p_eff_curr_drv_ratio[1] = 2.23;
873 gmp_to_gmn_multiplier[1] = 0.99;
874 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];
875 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];
876 long_channel_leakage_reduction[1] = 1/2.08;
877 I_off_n[1][0] = 1.01e-11;
878 I_off_n[1][10] = 1.65e-11;
879 I_off_n[1][20] = 2.62e-11;
880 I_off_n[1][30] = 4.06e-11;
881 I_off_n[1][40] = 6.12e-11;
882 I_off_n[1][50] = 9.02e-11;
883 I_off_n[1][60] = 1.3e-10;
884 I_off_n[1][70] = 1.83e-10;
885 I_off_n[1][80] = 2.51e-10;
886 I_off_n[1][90] = 3.29e-10;
887 I_off_n[1][100] = 4.1e-10;
888
889 I_g_on_n[1][0] = 9.47e-12;//A/micron
890 I_g_on_n[1][10] = 9.47e-12;
891 I_g_on_n[1][20] = 9.47e-12;
892 I_g_on_n[1][30] = 9.47e-12;
893 I_g_on_n[1][40] = 9.47e-12;
894 I_g_on_n[1][50] = 9.47e-12;
895 I_g_on_n[1][60] = 9.47e-12;
896 I_g_on_n[1][70] = 9.47e-12;
897 I_g_on_n[1][80] = 9.47e-12;
898 I_g_on_n[1][90] = 9.47e-12;
899 I_g_on_n[1][100] = 9.47e-12;
900
901 //ITRS LOP device type
902 vdd[2] = 0.7;
903 Lphy[2] = 0.022;
904 Lelec[2] = 0.016;
905 t_ox[2] = 0.9e-3;
906 v_th[2] = 0.22599;
907 c_ox[2] = 2.82e-14;//F/micron2
908 mobility_eff[2] = 508.9 * (1e-2 * 1e6 * 1e-2 * 1e6);
909 Vdsat[2] = 5.71e-2;
910 c_g_ideal[2] = 6.2e-16;
911 c_fringe[2] = 0.073e-15;
912 c_junc[2] = 1e-15;
913 I_on_n[2] = 748.9e-6;
914 I_on_p[2] = I_on_n[2] / 2;
915 nmos_effective_resistance_multiplier = 1.76;
916 n_to_p_eff_curr_drv_ratio[2] = 2.28;
917 gmp_to_gmn_multiplier[2] = 1.11;
918 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];
919 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];
920 long_channel_leakage_reduction[2] = 1/1.92;
921 I_off_n[2][0] = 4.03e-9;
922 I_off_n[2][10] = 5.02e-9;
923 I_off_n[2][20] = 6.18e-9;
924 I_off_n[2][30] = 7.51e-9;
925 I_off_n[2][40] = 9.04e-9;
926 I_off_n[2][50] = 1.08e-8;
927 I_off_n[2][60] = 1.27e-8;
928 I_off_n[2][70] = 1.47e-8;
929 I_off_n[2][80] = 1.66e-8;
930 I_off_n[2][90] = 1.84e-8;
931 I_off_n[2][100] = 2.03e-8;
932
933 I_g_on_n[2][0] = 3.24e-8;//A/micron
934 I_g_on_n[2][10] = 4.01e-8;
935 I_g_on_n[2][20] = 4.90e-8;
936 I_g_on_n[2][30] = 5.92e-8;
937 I_g_on_n[2][40] = 7.08e-8;
938 I_g_on_n[2][50] = 8.38e-8;
939 I_g_on_n[2][60] = 9.82e-8;
940 I_g_on_n[2][70] = 1.14e-7;
941 I_g_on_n[2][80] = 1.29e-7;
942 I_g_on_n[2][90] = 1.43e-7;
943 I_g_on_n[2][100] = 1.54e-7;
944
945 if (ram_cell_tech_type == lp_dram)
946 {
947 //LP-DRAM cell access transistor technology parameters
948 curr_vdd_dram_cell = 1.1;
949 Lphy[3] = 0.078;
950 Lelec[3] = 0.0504;// Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors.
951 curr_v_th_dram_access_transistor = 0.44559;
952 width_dram_access_transistor = 0.079;
953 curr_I_on_dram_cell = 36e-6;//A
954 curr_I_off_dram_cell_worst_case_length_temp = 19.5e-12;
955 curr_Wmemcella_dram = width_dram_access_transistor;
956 curr_Wmemcellpmos_dram = 0;
957 curr_Wmemcellnmos_dram = 0;
958 curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0;
959 curr_asp_ratio_cell_dram = 1.46;
960 curr_c_dram_cell = 20e-15;
961
962 //LP-DRAM wordline transistor parameters
963 curr_vpp = 1.5;
964 t_ox[3] = 2.1e-3;
965 v_th[3] = 0.44559;
966 c_ox[3] = 1.41e-14;
967 mobility_eff[3] = 426.30 * (1e-2 * 1e6 * 1e-2 * 1e6);
968 Vdsat[3] = 0.181;
969 c_g_ideal[3] = 1.10e-15;
970 c_fringe[3] = 0.08e-15;
971 c_junc[3] = 1e-15;
972 I_on_n[3] = 456e-6;
973 I_on_p[3] = I_on_n[3] / 2;
974 nmos_effective_resistance_multiplier = 1.65;
975 n_to_p_eff_curr_drv_ratio[3] = 2.05;
976 gmp_to_gmn_multiplier[3] = 0.90;
977 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
978 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
979 long_channel_leakage_reduction[3] = 1;
980 I_off_n[3][0] = 2.54e-11;
981 I_off_n[3][10] = 3.94e-11;
982 I_off_n[3][20] = 5.95e-11;
983 I_off_n[3][30] = 8.79e-11;
984 I_off_n[3][40] = 1.27e-10;
985 I_off_n[3][50] = 1.79e-10;
986 I_off_n[3][60] = 2.47e-10;
987 I_off_n[3][70] = 3.31e-10;
988 I_off_n[3][80] = 4.26e-10;
989 I_off_n[3][90] = 5.27e-10;
990 I_off_n[3][100] = 6.46e-10;
991 }
992 else if (ram_cell_tech_type == comm_dram)
993 {
994 //COMM-DRAM cell access transistor technology parameters
995 curr_vdd_dram_cell = 1.1;
996 Lphy[3] = 0.045;
997 Lelec[3] = 0.0298;
998 curr_v_th_dram_access_transistor = 1;
999 width_dram_access_transistor = 0.045;
1000 curr_I_on_dram_cell = 20e-6;//A
1001 curr_I_off_dram_cell_worst_case_length_temp = 1e-15;
1002 curr_Wmemcella_dram = width_dram_access_transistor;
1003 curr_Wmemcellpmos_dram = 0;
1004 curr_Wmemcellnmos_dram = 0;
1005 curr_area_cell_dram = 6*0.045*0.045;
1006 curr_asp_ratio_cell_dram = 1.5;
1007 curr_c_dram_cell = 30e-15;
1008
1009 //COMM-DRAM wordline transistor parameters
1010 curr_vpp = 2.7;
1011 t_ox[3] = 4e-3;
1012 v_th[3] = 1.0;
1013 c_ox[3] = 7.98e-15;
1014 mobility_eff[3] = 368.58 * (1e-2 * 1e6 * 1e-2 * 1e6);
1015 Vdsat[3] = 0.147;
1016 c_g_ideal[3] = 3.59e-16;
1017 c_fringe[3] = 0.08e-15;
1018 c_junc[3] = 1e-15;
1019 I_on_n[3] = 999.4e-6;
1020 I_on_p[3] = I_on_n[3] / 2;
1021 nmos_effective_resistance_multiplier = 1.69;
1022 n_to_p_eff_curr_drv_ratio[3] = 1.95;
1023 gmp_to_gmn_multiplier[3] = 0.90;
1024 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
1025 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
1026 long_channel_leakage_reduction[3] = 1;
1027 I_off_n[3][0] = 1.31e-14;
1028 I_off_n[3][10] = 2.68e-14;
1029 I_off_n[3][20] = 5.25e-14;
1030 I_off_n[3][30] = 9.88e-14;
1031 I_off_n[3][40] = 1.79e-13;
1032 I_off_n[3][50] = 3.15e-13;
1033 I_off_n[3][60] = 5.36e-13;
1034 I_off_n[3][70] = 8.86e-13;
1035 I_off_n[3][80] = 1.42e-12;
1036 I_off_n[3][90] = 2.20e-12;
1037 I_off_n[3][100] = 3.29e-12;
1038 }
1039
1040
1041 //SRAM cell properties
1042 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
1043 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
1044 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
1045 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
1046 curr_asp_ratio_cell_sram = 1.46;
1047 //CAM cell properties //TODO: data need to be revisited
1048 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um;
1049 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um;
1050 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um;
1051 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;
1052 curr_asp_ratio_cell_cam = 2.92;
1053 //Empirical undifferetiated core/FU coefficient
1054 curr_logic_scaling_co_eff = 0.7*0.7;
1055 curr_core_tx_density = 1.25;
1056 curr_sckt_co_eff = 1.1387;
1057 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2
1058 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb
1059 }
1060
1061 if (tech == 32)
1062 {
1063 SENSE_AMP_D = .03e-9; // s
1064 SENSE_AMP_P = 2.16e-15; // J
1065 //For 2013, MPU/ASIC stagger-contacted M1 half-pitch is 32 nm (so this is 32 nm
1066 //technology i.e. FEATURESIZE = 0.032). Using the SOI process numbers for
1067 //HP and LSTP.
1068 vdd[0] = 0.9;
1069 Lphy[0] = 0.013;
1070 Lelec[0] = 0.01013;
1071 t_ox[0] = 0.5e-3;
1072 v_th[0] = 0.21835;
1073 c_ox[0] = 4.11e-14;
1074 mobility_eff[0] = 361.84 * (1e-2 * 1e6 * 1e-2 * 1e6);
1075 Vdsat[0] = 5.09E-2;
1076 c_g_ideal[0] = 5.34e-16;
1077 c_fringe[0] = 0.04e-15;
1078 c_junc[0] = 1e-15;
1079 I_on_n[0] = 2211.7e-6;
1080 I_on_p[0] = I_on_n[0] / 2;
1081 nmos_effective_resistance_multiplier = 1.49;
1082 n_to_p_eff_curr_drv_ratio[0] = 2.41;
1083 gmp_to_gmn_multiplier[0] = 1.38;
1084 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron
1085 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron
1086 long_channel_leakage_reduction[0] = 1/3.706;
1087 //Using MASTAR, @300K (380K does not work in MASTAR), increase Lgate until Ion reduces to 95% or Lgate increase by 5% (DG device can only increase by 5%),
1088 //whichever comes first
1089 I_off_n[0][0] = 1.52e-7;
1090 I_off_n[0][10] = 1.55e-7;
1091 I_off_n[0][20] = 1.59e-7;
1092 I_off_n[0][30] = 1.68e-7;
1093 I_off_n[0][40] = 1.90e-7;
1094 I_off_n[0][50] = 2.69e-7;
1095 I_off_n[0][60] = 5.32e-7;
1096 I_off_n[0][70] = 1.02e-6;
1097 I_off_n[0][80] = 1.62e-6;
1098 I_off_n[0][90] = 2.73e-6;
1099 I_off_n[0][100] = 6.1e-6;
1100
1101 I_g_on_n[0][0] = 6.55e-8;//A/micron
1102 I_g_on_n[0][10] = 6.55e-8;
1103 I_g_on_n[0][20] = 6.55e-8;
1104 I_g_on_n[0][30] = 6.55e-8;
1105 I_g_on_n[0][40] = 6.55e-8;
1106 I_g_on_n[0][50] = 6.55e-8;
1107 I_g_on_n[0][60] = 6.55e-8;
1108 I_g_on_n[0][70] = 6.55e-8;
1109 I_g_on_n[0][80] = 6.55e-8;
1110 I_g_on_n[0][90] = 6.55e-8;
1111 I_g_on_n[0][100] = 6.55e-8;
1112
1113 // 32 DG
1114 // I_g_on_n[0][0] = 2.71e-9;//A/micron
1115 // I_g_on_n[0][10] = 2.71e-9;
1116 // I_g_on_n[0][20] = 2.71e-9;
1117 // I_g_on_n[0][30] = 2.71e-9;
1118 // I_g_on_n[0][40] = 2.71e-9;
1119 // I_g_on_n[0][50] = 2.71e-9;
1120 // I_g_on_n[0][60] = 2.71e-9;
1121 // I_g_on_n[0][70] = 2.71e-9;
1122 // I_g_on_n[0][80] = 2.71e-9;
1123 // I_g_on_n[0][90] = 2.71e-9;
1124 // I_g_on_n[0][100] = 2.71e-9;
1125
1126 //LSTP device type
1127 vdd[1] = 1;
1128 Lphy[1] = 0.020;
1129 Lelec[1] = 0.0173;
1130 t_ox[1] = 1.2e-3;
1131 v_th[1] = 0.513;
1132 c_ox[1] = 2.29e-14;
1133 mobility_eff[1] = 347.46 * (1e-2 * 1e6 * 1e-2 * 1e6);
1134 Vdsat[1] = 8.64e-2;
1135 c_g_ideal[1] = 4.58e-16;
1136 c_fringe[1] = 0.053e-15;
1137 c_junc[1] = 1e-15;
1138 I_on_n[1] = 683.6e-6;
1139 I_on_p[1] = I_on_n[1] / 2;
1140 nmos_effective_resistance_multiplier = 1.99;
1141 n_to_p_eff_curr_drv_ratio[1] = 2.23;
1142 gmp_to_gmn_multiplier[1] = 0.99;
1143 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];
1144 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];
1145 long_channel_leakage_reduction[1] = 1/1.93;
1146 I_off_n[1][0] = 2.06e-11;
1147 I_off_n[1][10] = 3.30e-11;
1148 I_off_n[1][20] = 5.15e-11;
1149 I_off_n[1][30] = 7.83e-11;
1150 I_off_n[1][40] = 1.16e-10;
1151 I_off_n[1][50] = 1.69e-10;
1152 I_off_n[1][60] = 2.40e-10;
1153 I_off_n[1][70] = 3.34e-10;
1154 I_off_n[1][80] = 4.54e-10;
1155 I_off_n[1][90] = 5.96e-10;
1156 I_off_n[1][100] = 7.44e-10;
1157
1158 I_g_on_n[1][0] = 3.73e-11;//A/micron
1159 I_g_on_n[1][10] = 3.73e-11;
1160 I_g_on_n[1][20] = 3.73e-11;
1161 I_g_on_n[1][30] = 3.73e-11;
1162 I_g_on_n[1][40] = 3.73e-11;
1163 I_g_on_n[1][50] = 3.73e-11;
1164 I_g_on_n[1][60] = 3.73e-11;
1165 I_g_on_n[1][70] = 3.73e-11;
1166 I_g_on_n[1][80] = 3.73e-11;
1167 I_g_on_n[1][90] = 3.73e-11;
1168 I_g_on_n[1][100] = 3.73e-11;
1169
1170
1171 //LOP device type
1172 vdd[2] = 0.6;
1173 Lphy[2] = 0.016;
1174 Lelec[2] = 0.01232;
1175 t_ox[2] = 0.9e-3;
1176 v_th[2] = 0.24227;
1177 c_ox[2] = 2.84e-14;
1178 mobility_eff[2] = 513.52 * (1e-2 * 1e6 * 1e-2 * 1e6);
1179 Vdsat[2] = 4.64e-2;
1180 c_g_ideal[2] = 4.54e-16;
1181 c_fringe[2] = 0.057e-15;
1182 c_junc[2] = 1e-15;
1183 I_on_n[2] = 827.8e-6;
1184 I_on_p[2] = I_on_n[2] / 2;
1185 nmos_effective_resistance_multiplier = 1.73;
1186 n_to_p_eff_curr_drv_ratio[2] = 2.28;
1187 gmp_to_gmn_multiplier[2] = 1.11;
1188 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];
1189 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];
1190 long_channel_leakage_reduction[2] = 1/1.89;
1191 I_off_n[2][0] = 5.94e-8;
1192 I_off_n[2][10] = 7.23e-8;
1193 I_off_n[2][20] = 8.7e-8;
1194 I_off_n[2][30] = 1.04e-7;
1195 I_off_n[2][40] = 1.22e-7;
1196 I_off_n[2][50] = 1.43e-7;
1197 I_off_n[2][60] = 1.65e-7;
1198 I_off_n[2][70] = 1.90e-7;
1199 I_off_n[2][80] = 2.15e-7;
1200 I_off_n[2][90] = 2.39e-7;
1201 I_off_n[2][100] = 2.63e-7;
1202
1203 I_g_on_n[2][0] = 2.93e-9;//A/micron
1204 I_g_on_n[2][10] = 2.93e-9;
1205 I_g_on_n[2][20] = 2.93e-9;
1206 I_g_on_n[2][30] = 2.93e-9;
1207 I_g_on_n[2][40] = 2.93e-9;
1208 I_g_on_n[2][50] = 2.93e-9;
1209 I_g_on_n[2][60] = 2.93e-9;
1210 I_g_on_n[2][70] = 2.93e-9;
1211 I_g_on_n[2][80] = 2.93e-9;
1212 I_g_on_n[2][90] = 2.93e-9;
1213 I_g_on_n[2][100] = 2.93e-9;
1214
1215 if (ram_cell_tech_type == lp_dram)
1216 {
1217 //LP-DRAM cell access transistor technology parameters
1218 curr_vdd_dram_cell = 1.0;
1219 Lphy[3] = 0.056;
1220 Lelec[3] = 0.0419;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors.
1221 curr_v_th_dram_access_transistor = 0.44129;
1222 width_dram_access_transistor = 0.056;
1223 curr_I_on_dram_cell = 36e-6;
1224 curr_I_off_dram_cell_worst_case_length_temp = 18.9e-12;
1225 curr_Wmemcella_dram = width_dram_access_transistor;
1226 curr_Wmemcellpmos_dram = 0;
1227 curr_Wmemcellnmos_dram = 0;
1228 curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0;
1229 curr_asp_ratio_cell_dram = 1.46;
1230 curr_c_dram_cell = 20e-15;
1231
1232 //LP-DRAM wordline transistor parameters
1233 curr_vpp = 1.5;
1234 t_ox[3] = 2e-3;
1235 v_th[3] = 0.44467;
1236 c_ox[3] = 1.48e-14;
1237 mobility_eff[3] = 408.12 * (1e-2 * 1e6 * 1e-2 * 1e6);
1238 Vdsat[3] = 0.174;
1239 c_g_ideal[3] = 7.45e-16;
1240 c_fringe[3] = 0.053e-15;
1241 c_junc[3] = 1e-15;
1242 I_on_n[3] = 1055.4e-6;
1243 I_on_p[3] = I_on_n[3] / 2;
1244 nmos_effective_resistance_multiplier = 1.65;
1245 n_to_p_eff_curr_drv_ratio[3] = 2.05;
1246 gmp_to_gmn_multiplier[3] = 0.90;
1247 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
1248 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
1249 long_channel_leakage_reduction[3] = 1;
1250 I_off_n[3][0] = 3.57e-11;
1251 I_off_n[3][10] = 5.51e-11;
1252 I_off_n[3][20] = 8.27e-11;
1253 I_off_n[3][30] = 1.21e-10;
1254 I_off_n[3][40] = 1.74e-10;
1255 I_off_n[3][50] = 2.45e-10;
1256 I_off_n[3][60] = 3.38e-10;
1257 I_off_n[3][70] = 4.53e-10;
1258 I_off_n[3][80] = 5.87e-10;
1259 I_off_n[3][90] = 7.29e-10;
1260 I_off_n[3][100] = 8.87e-10;
1261 }
1262 else if (ram_cell_tech_type == comm_dram)
1263 {
1264 //COMM-DRAM cell access transistor technology parameters
1265 curr_vdd_dram_cell = 1.0;
1266 Lphy[3] = 0.032;
1267 Lelec[3] = 0.0205;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors.
1268 curr_v_th_dram_access_transistor = 1;
1269 width_dram_access_transistor = 0.032;
1270 curr_I_on_dram_cell = 20e-6;
1271 curr_I_off_dram_cell_worst_case_length_temp = 1e-15;
1272 curr_Wmemcella_dram = width_dram_access_transistor;
1273 curr_Wmemcellpmos_dram = 0;
1274 curr_Wmemcellnmos_dram = 0;
1275 curr_area_cell_dram = 6*0.032*0.032;
1276 curr_asp_ratio_cell_dram = 1.5;
1277 curr_c_dram_cell = 30e-15;
1278
1279 //COMM-DRAM wordline transistor parameters
1280 curr_vpp = 2.6;
1281 t_ox[3] = 4e-3;
1282 v_th[3] = 1.0;
1283 c_ox[3] = 7.99e-15;
1284 mobility_eff[3] = 380.76 * (1e-2 * 1e6 * 1e-2 * 1e6);
1285 Vdsat[3] = 0.129;
1286 c_g_ideal[3] = 2.56e-16;
1287 c_fringe[3] = 0.053e-15;
1288 c_junc[3] = 1e-15;
1289 I_on_n[3] = 1024.5e-6;
1290 I_on_p[3] = I_on_n[3] / 2;
1291 nmos_effective_resistance_multiplier = 1.69;
1292 n_to_p_eff_curr_drv_ratio[3] = 1.95;
1293 gmp_to_gmn_multiplier[3] = 0.90;
1294 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
1295 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
1296 long_channel_leakage_reduction[3] = 1;
1297 I_off_n[3][0] = 3.63e-14;
1298 I_off_n[3][10] = 7.18e-14;
1299 I_off_n[3][20] = 1.36e-13;
1300 I_off_n[3][30] = 2.49e-13;
1301 I_off_n[3][40] = 4.41e-13;
1302 I_off_n[3][50] = 7.55e-13;
1303 I_off_n[3][60] = 1.26e-12;
1304 I_off_n[3][70] = 2.03e-12;
1305 I_off_n[3][80] = 3.19e-12;
1306 I_off_n[3][90] = 4.87e-12;
1307 I_off_n[3][100] = 7.16e-12;
1308 }
1309
1310 //SRAM cell properties
1311 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
1312 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
1313 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
1314 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
1315 curr_asp_ratio_cell_sram = 1.46;
1316 //CAM cell properties //TODO: data need to be revisited
1317 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um;
1318 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um;
1319 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um;
1320 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;
1321 curr_asp_ratio_cell_cam = 2.92;
1322 //Empirical undifferetiated core/FU coefficient
1323 curr_logic_scaling_co_eff = 0.7*0.7*0.7;
1324 curr_core_tx_density = 1.25/0.7;
1325 curr_sckt_co_eff = 1.1111;
1326 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2
1327 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb
1328 }
1329
1330 if(tech == 22){
1331 SENSE_AMP_D = .03e-9; // s
1332 SENSE_AMP_P = 2.16e-15; // J
1333 //For 2016, MPU/ASIC stagger-contacted M1 half-pitch is 22 nm (so this is 22 nm
1334 //technology i.e. FEATURESIZE = 0.022). Using the DG process numbers for HP.
1335 //22 nm HP
1336 vdd[0] = 0.8;
1337 Lphy[0] = 0.009;//Lphy is the physical gate-length.
1338 Lelec[0] = 0.00468;//Lelec is the electrical gate-length.
1339 t_ox[0] = 0.55e-3;//micron
1340 v_th[0] = 0.1395;//V
1341 c_ox[0] = 3.63e-14;//F/micron2
1342 mobility_eff[0] = 426.07 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs
1343 Vdsat[0] = 2.33e-2; //V/micron
1344 c_g_ideal[0] = 3.27e-16;//F/micron
1345 c_fringe[0] = 0.06e-15;//F/micron
1346 c_junc[0] = 0;//F/micron2
1347 I_on_n[0] = 2626.4e-6;//A/micron
1348 I_on_p[0] = I_on_n[0] / 2;//A/micron //This value for I_on_p is not really used.
1349 nmos_effective_resistance_multiplier = 1.45;
1350 n_to_p_eff_curr_drv_ratio[0] = 2; //Wpmos/Wnmos = 2 in 2007 MASTAR. Look in
1351 //"Dynamic" tab of Device workspace.
1352 gmp_to_gmn_multiplier[0] = 1.38; //Just using the 32nm SOI value.
1353 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron
1354 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron
1355 long_channel_leakage_reduction[0] = 1/3.274;
1356 I_off_n[0][0] = 1.52e-7/1.5*1.2;//From 22nm, leakage current are directly from ITRS report rather than MASTAR, since MASTAR has serious bugs there.
1357 I_off_n[0][10] = 1.55e-7/1.5*1.2;
1358 I_off_n[0][20] = 1.59e-7/1.5*1.2;
1359 I_off_n[0][30] = 1.68e-7/1.5*1.2;
1360 I_off_n[0][40] = 1.90e-7/1.5*1.2;
1361 I_off_n[0][50] = 2.69e-7/1.5*1.2;
1362 I_off_n[0][60] = 5.32e-7/1.5*1.2;
1363 I_off_n[0][70] = 1.02e-6/1.5*1.2;
1364 I_off_n[0][80] = 1.62e-6/1.5*1.2;
1365 I_off_n[0][90] = 2.73e-6/1.5*1.2;
1366 I_off_n[0][100] = 6.1e-6/1.5*1.2;
1367 //for 22nm DG HP
1368 I_g_on_n[0][0] = 1.81e-9;//A/micron
1369 I_g_on_n[0][10] = 1.81e-9;
1370 I_g_on_n[0][20] = 1.81e-9;
1371 I_g_on_n[0][30] = 1.81e-9;
1372 I_g_on_n[0][40] = 1.81e-9;
1373 I_g_on_n[0][50] = 1.81e-9;
1374 I_g_on_n[0][60] = 1.81e-9;
1375 I_g_on_n[0][70] = 1.81e-9;
1376 I_g_on_n[0][80] = 1.81e-9;
1377 I_g_on_n[0][90] = 1.81e-9;
1378 I_g_on_n[0][100] = 1.81e-9;
1379
1380 //22 nm LSTP DG
1381 vdd[1] = 0.8;
1382 Lphy[1] = 0.014;
1383 Lelec[1] = 0.008;//Lelec is the electrical gate-length.
1384 t_ox[1] = 1.1e-3;//micron
1385 v_th[1] = 0.40126;//V
1386 c_ox[1] = 2.30e-14;//F/micron2
1387 mobility_eff[1] = 738.09 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs
1388 Vdsat[1] = 6.64e-2; //V/micron
1389 c_g_ideal[1] = 3.22e-16;//F/micron
1390 c_fringe[1] = 0.08e-15;
1391 c_junc[1] = 0;//F/micron2
1392 I_on_n[1] = 727.6e-6;//A/micron
1393 I_on_p[1] = I_on_n[1] / 2;
1394 nmos_effective_resistance_multiplier = 1.99;
1395 n_to_p_eff_curr_drv_ratio[1] = 2;
1396 gmp_to_gmn_multiplier[1] = 0.99;
1397 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];//ohm-micron
1398 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];//ohm-micron
1399 long_channel_leakage_reduction[1] = 1/1.89;
1400 I_off_n[1][0] = 2.43e-11;
1401 I_off_n[1][10] = 4.85e-11;
1402 I_off_n[1][20] = 9.68e-11;
1403 I_off_n[1][30] = 1.94e-10;
1404 I_off_n[1][40] = 3.87e-10;
1405 I_off_n[1][50] = 7.73e-10;
1406 I_off_n[1][60] = 3.55e-10;
1407 I_off_n[1][70] = 3.09e-9;
1408 I_off_n[1][80] = 6.19e-9;
1409 I_off_n[1][90] = 1.24e-8;
1410 I_off_n[1][100]= 2.48e-8;
1411
1412 I_g_on_n[1][0] = 4.51e-10;//A/micron
1413 I_g_on_n[1][10] = 4.51e-10;
1414 I_g_on_n[1][20] = 4.51e-10;
1415 I_g_on_n[1][30] = 4.51e-10;
1416 I_g_on_n[1][40] = 4.51e-10;
1417 I_g_on_n[1][50] = 4.51e-10;
1418 I_g_on_n[1][60] = 4.51e-10;
1419 I_g_on_n[1][70] = 4.51e-10;
1420 I_g_on_n[1][80] = 4.51e-10;
1421 I_g_on_n[1][90] = 4.51e-10;
1422 I_g_on_n[1][100] = 4.51e-10;
1423
1424 //22 nm LOP
1425 vdd[2] = 0.6;
1426 Lphy[2] = 0.011;
1427 Lelec[2] = 0.00604;//Lelec is the electrical gate-length.
1428 t_ox[2] = 0.8e-3;//micron
1429 v_th[2] = 0.2315;//V
1430 c_ox[2] = 2.87e-14;//F/micron2
1431 mobility_eff[2] = 698.37 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs
1432 Vdsat[2] = 1.81e-2; //V/micron
1433 c_g_ideal[2] = 3.16e-16;//F/micron
1434 c_fringe[2] = 0.08e-15;
1435 c_junc[2] = 0;//F/micron2 This is Cj0 not Cjunc in MASTAR results->Dynamic Tab
1436 I_on_n[2] = 916.1e-6;//A/micron
1437 I_on_p[2] = I_on_n[2] / 2;
1438 nmos_effective_resistance_multiplier = 1.73;
1439 n_to_p_eff_curr_drv_ratio[2] = 2;
1440 gmp_to_gmn_multiplier[2] = 1.11;
1441 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];//ohm-micron
1442 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];//ohm-micron
1443 long_channel_leakage_reduction[2] = 1/2.38;
1444
1445 I_off_n[2][0] = 1.31e-8;
1446 I_off_n[2][10] = 2.60e-8;
1447 I_off_n[2][20] = 5.14e-8;
1448 I_off_n[2][30] = 1.02e-7;
1449 I_off_n[2][40] = 2.02e-7;
1450 I_off_n[2][50] = 3.99e-7;
1451 I_off_n[2][60] = 7.91e-7;
1452 I_off_n[2][70] = 1.09e-6;
1453 I_off_n[2][80] = 2.09e-6;
1454 I_off_n[2][90] = 4.04e-6;
1455 I_off_n[2][100]= 4.48e-6;
1456
1457 I_g_on_n[2][0] = 2.74e-9;//A/micron
1458 I_g_on_n[2][10] = 2.74e-9;
1459 I_g_on_n[2][20] = 2.74e-9;
1460 I_g_on_n[2][30] = 2.74e-9;
1461 I_g_on_n[2][40] = 2.74e-9;
1462 I_g_on_n[2][50] = 2.74e-9;
1463 I_g_on_n[2][60] = 2.74e-9;
1464 I_g_on_n[2][70] = 2.74e-9;
1465 I_g_on_n[2][80] = 2.74e-9;
1466 I_g_on_n[2][90] = 2.74e-9;
1467 I_g_on_n[2][100] = 2.74e-9;
1468
1469
1470
1471 if (ram_cell_tech_type == 3)
1472 {}
1473 else if (ram_cell_tech_type == 4)
1474 {
1475 //22 nm commodity DRAM cell access transistor technology parameters.
1476 //parameters
1477 curr_vdd_dram_cell = 0.9;//0.45;//This value has reduced greatly in 2007 ITRS for all technology nodes. In
1478 //2005 ITRS, the value was about twice the value in 2007 ITRS
1479 Lphy[3] = 0.022;//micron
1480 Lelec[3] = 0.0181;//micron.
1481 curr_v_th_dram_access_transistor = 1;//V
1482 width_dram_access_transistor = 0.022;//micron
1483 curr_I_on_dram_cell = 20e-6; //This is a typical value that I have always
1484 //kept constant. In reality this could perhaps be lower
1485 curr_I_off_dram_cell_worst_case_length_temp = 1e-15;//A
1486 curr_Wmemcella_dram = width_dram_access_transistor;
1487 curr_Wmemcellpmos_dram = 0;
1488 curr_Wmemcellnmos_dram = 0;
1489 curr_area_cell_dram = 6*0.022*0.022;//micron2.
1490 curr_asp_ratio_cell_dram = 0.667;
1491 curr_c_dram_cell = 30e-15;//This is a typical value that I have alwaus
1492 //kept constant.
1493
1494 //22 nm commodity DRAM wordline transistor parameters obtained using MASTAR.
1495 curr_vpp = 2.3;//vpp. V
1496 t_ox[3] = 3.5e-3;//micron
1497 v_th[3] = 1.0;//V
1498 c_ox[3] = 9.06e-15;//F/micron2
1499 mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6);//micron2 / Vs
1500 Vdsat[3] = 0.0972; //V/micron
1501 c_g_ideal[3] = 1.99e-16;//F/micron
1502 c_fringe[3] = 0.053e-15;//F/micron
1503 c_junc[3] = 1e-15;//F/micron2
1504 I_on_n[3] = 910.5e-6;//A/micron
1505 I_on_p[3] = I_on_n[3] / 2;//This value for I_on_p is not really used.
1506 nmos_effective_resistance_multiplier = 1.69;//Using the value from 32nm.
1507 //
1508 n_to_p_eff_curr_drv_ratio[3] = 1.95;//Using the value from 32nm
1509 gmp_to_gmn_multiplier[3] = 0.90;
1510 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];//ohm-micron
1511 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];//ohm-micron
1512 long_channel_leakage_reduction[3] = 1;
1513 I_off_n[3][0] = 1.1e-13; //A/micron
1514 I_off_n[3][10] = 2.11e-13;
1515 I_off_n[3][20] = 3.88e-13;
1516 I_off_n[3][30] = 6.9e-13;
1517 I_off_n[3][40] = 1.19e-12;
1518 I_off_n[3][50] = 1.98e-12;
1519 I_off_n[3][60] = 3.22e-12;
1520 I_off_n[3][70] = 5.09e-12;
1521 I_off_n[3][80] = 7.85e-12;
1522 I_off_n[3][90] = 1.18e-11;
1523 I_off_n[3][100] = 1.72e-11;
1524
1525 }
1526 else
1527 {
1528 //some error handler
1529 }
1530
1531 //SRAM cell properties
1532 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
1533 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
1534 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
1535 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
1536 curr_asp_ratio_cell_sram = 1.46;
1537 //CAM cell properties //TODO: data need to be revisited
1538 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um;
1539 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um;
1540 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um;
1541 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;
1542 curr_asp_ratio_cell_cam = 2.92;
1543 //Empirical undifferetiated core/FU coefficient
1544 curr_logic_scaling_co_eff = 0.7*0.7*0.7*0.7;
1545 curr_core_tx_density = 1.25/0.7/0.7;
1546 curr_sckt_co_eff = 1.1296;
1547 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2
1548 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb
1549 }
1550
1551 if(tech == 16){
1552 //For 2019, MPU/ASIC stagger-contacted M1 half-pitch is 16 nm (so this is 16 nm
1553 //technology i.e. FEATURESIZE = 0.016). Using the DG process numbers for HP.
1554 //16 nm HP
1555 vdd[0] = 0.7;
1556 Lphy[0] = 0.006;//Lphy is the physical gate-length.
1557 Lelec[0] = 0.00315;//Lelec is the electrical gate-length.
1558 t_ox[0] = 0.5e-3;//micron
1559 v_th[0] = 0.1489;//V
1560 c_ox[0] = 3.83e-14;//F/micron2 Cox_elec in MASTAR
1561 mobility_eff[0] = 476.15 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs
1562 Vdsat[0] = 1.42e-2; //V/micron calculated in spreadsheet
1563 c_g_ideal[0] = 2.30e-16;//F/micron
1564 c_fringe[0] = 0.06e-15;//F/micron MASTAR inputdynamic/3
1565 c_junc[0] = 0;//F/micron2 MASTAR result dynamic
1566 I_on_n[0] = 2768.4e-6;//A/micron
1567 I_on_p[0] = I_on_n[0] / 2;//A/micron //This value for I_on_p is not really used.
1568 nmos_effective_resistance_multiplier = 1.48;//nmos_effective_resistance_multiplier is the ratio of Ieff to Idsat where Ieff is the effective NMOS current and Idsat is the saturation current.
1569 n_to_p_eff_curr_drv_ratio[0] = 2; //Wpmos/Wnmos = 2 in 2007 MASTAR. Look in
1570 //"Dynamic" tab of Device workspace.
1571 gmp_to_gmn_multiplier[0] = 1.38; //Just using the 32nm SOI value.
1572 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron
1573 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron
1574 long_channel_leakage_reduction[0] = 1/2.655;
1575 I_off_n[0][0] = 1.52e-7/1.5*1.2*1.07;
1576 I_off_n[0][10] = 1.55e-7/1.5*1.2*1.07;
1577 I_off_n[0][20] = 1.59e-7/1.5*1.2*1.07;
1578 I_off_n[0][30] = 1.68e-7/1.5*1.2*1.07;
1579 I_off_n[0][40] = 1.90e-7/1.5*1.2*1.07;
1580 I_off_n[0][50] = 2.69e-7/1.5*1.2*1.07;
1581 I_off_n[0][60] = 5.32e-7/1.5*1.2*1.07;
1582 I_off_n[0][70] = 1.02e-6/1.5*1.2*1.07;
1583 I_off_n[0][80] = 1.62e-6/1.5*1.2*1.07;
1584 I_off_n[0][90] = 2.73e-6/1.5*1.2*1.07;
1585 I_off_n[0][100] = 6.1e-6/1.5*1.2*1.07;
1586 //for 16nm DG HP
1587 I_g_on_n[0][0] = 1.07e-9;//A/micron
1588 I_g_on_n[0][10] = 1.07e-9;
1589 I_g_on_n[0][20] = 1.07e-9;
1590 I_g_on_n[0][30] = 1.07e-9;
1591 I_g_on_n[0][40] = 1.07e-9;
1592 I_g_on_n[0][50] = 1.07e-9;
1593 I_g_on_n[0][60] = 1.07e-9;
1594 I_g_on_n[0][70] = 1.07e-9;
1595 I_g_on_n[0][80] = 1.07e-9;
1596 I_g_on_n[0][90] = 1.07e-9;
1597 I_g_on_n[0][100] = 1.07e-9;
1598
1599 // //16 nm LSTP DG
1600 // vdd[1] = 0.8;
1601 // Lphy[1] = 0.014;
1602 // Lelec[1] = 0.008;//Lelec is the electrical gate-length.
1603 // t_ox[1] = 1.1e-3;//micron
1604 // v_th[1] = 0.40126;//V
1605 // c_ox[1] = 2.30e-14;//F/micron2
1606 // mobility_eff[1] = 738.09 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs
1607 // Vdsat[1] = 6.64e-2; //V/micron
1608 // c_g_ideal[1] = 3.22e-16;//F/micron
1609 // c_fringe[1] = 0.008e-15;
1610 // c_junc[1] = 0;//F/micron2
1611 // I_on_n[1] = 727.6e-6;//A/micron
1612 // I_on_p[1] = I_on_n[1] / 2;
1613 // nmos_effective_resistance_multiplier = 1.99;
1614 // n_to_p_eff_curr_drv_ratio[1] = 2;
1615 // gmp_to_gmn_multiplier[1] = 0.99;
1616 // Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];//ohm-micron
1617 // Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];//ohm-micron
1618 // I_off_n[1][0] = 2.43e-11;
1619 // I_off_n[1][10] = 4.85e-11;
1620 // I_off_n[1][20] = 9.68e-11;
1621 // I_off_n[1][30] = 1.94e-10;
1622 // I_off_n[1][40] = 3.87e-10;
1623 // I_off_n[1][50] = 7.73e-10;
1624 // I_off_n[1][60] = 3.55e-10;
1625 // I_off_n[1][70] = 3.09e-9;
1626 // I_off_n[1][80] = 6.19e-9;
1627 // I_off_n[1][90] = 1.24e-8;
1628 // I_off_n[1][100]= 2.48e-8;
1629 //
1630 // // for 22nm LSTP HP
1631 // I_g_on_n[1][0] = 4.51e-10;//A/micron
1632 // I_g_on_n[1][10] = 4.51e-10;
1633 // I_g_on_n[1][20] = 4.51e-10;
1634 // I_g_on_n[1][30] = 4.51e-10;
1635 // I_g_on_n[1][40] = 4.51e-10;
1636 // I_g_on_n[1][50] = 4.51e-10;
1637 // I_g_on_n[1][60] = 4.51e-10;
1638 // I_g_on_n[1][70] = 4.51e-10;
1639 // I_g_on_n[1][80] = 4.51e-10;
1640 // I_g_on_n[1][90] = 4.51e-10;
1641 // I_g_on_n[1][100] = 4.51e-10;
1642
1643
1644 if (ram_cell_tech_type == 3)
1645 {}
1646 else if (ram_cell_tech_type == 4)
1647 {
1648 //22 nm commodity DRAM cell access transistor technology parameters.
1649 //parameters
1650 curr_vdd_dram_cell = 0.9;//0.45;//This value has reduced greatly in 2007 ITRS for all technology nodes. In
1651 //2005 ITRS, the value was about twice the value in 2007 ITRS
1652 Lphy[3] = 0.022;//micron
1653 Lelec[3] = 0.0181;//micron.
1654 curr_v_th_dram_access_transistor = 1;//V
1655 width_dram_access_transistor = 0.022;//micron
1656 curr_I_on_dram_cell = 20e-6; //This is a typical value that I have always
1657 //kept constant. In reality this could perhaps be lower
1658 curr_I_off_dram_cell_worst_case_length_temp = 1e-15;//A
1659 curr_Wmemcella_dram = width_dram_access_transistor;
1660 curr_Wmemcellpmos_dram = 0;
1661 curr_Wmemcellnmos_dram = 0;
1662 curr_area_cell_dram = 6*0.022*0.022;//micron2.
1663 curr_asp_ratio_cell_dram = 0.667;
1664 curr_c_dram_cell = 30e-15;//This is a typical value that I have alwaus
1665 //kept constant.
1666
1667 //22 nm commodity DRAM wordline transistor parameters obtained using MASTAR.
1668 curr_vpp = 2.3;//vpp. V
1669 t_ox[3] = 3.5e-3;//micron
1670 v_th[3] = 1.0;//V
1671 c_ox[3] = 9.06e-15;//F/micron2
1672 mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6);//micron2 / Vs
1673 Vdsat[3] = 0.0972; //V/micron
1674 c_g_ideal[3] = 1.99e-16;//F/micron
1675 c_fringe[3] = 0.053e-15;//F/micron
1676 c_junc[3] = 1e-15;//F/micron2
1677 I_on_n[3] = 910.5e-6;//A/micron
1678 I_on_p[3] = I_on_n[3] / 2;//This value for I_on_p is not really used.
1679 nmos_effective_resistance_multiplier = 1.69;//Using the value from 32nm.
1680 //
1681 n_to_p_eff_curr_drv_ratio[3] = 1.95;//Using the value from 32nm
1682 gmp_to_gmn_multiplier[3] = 0.90;
1683 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];//ohm-micron
1684 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];//ohm-micron
1685 long_channel_leakage_reduction[3] = 1;
1686 I_off_n[3][0] = 1.1e-13; //A/micron
1687 I_off_n[3][10] = 2.11e-13;
1688 I_off_n[3][20] = 3.88e-13;
1689 I_off_n[3][30] = 6.9e-13;
1690 I_off_n[3][40] = 1.19e-12;
1691 I_off_n[3][50] = 1.98e-12;
1692 I_off_n[3][60] = 3.22e-12;
1693 I_off_n[3][70] = 5.09e-12;
1694 I_off_n[3][80] = 7.85e-12;
1695 I_off_n[3][90] = 1.18e-11;
1696 I_off_n[3][100] = 1.72e-11;
1697
1698 }
1699 else
1700 {
1701 //some error handler
1702 }
1703
1704 //SRAM cell properties
1705 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
1706 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
1707 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
1708 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
1709 curr_asp_ratio_cell_sram = 1.46;
1710 //CAM cell properties //TODO: data need to be revisited
1711 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um;
1712 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um;
1713 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um;
1714 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;
1715 curr_asp_ratio_cell_cam = 2.92;
1716 //Empirical undifferetiated core/FU coefficient
1717 curr_logic_scaling_co_eff = 0.7*0.7*0.7*0.7*0.7;
1718 curr_core_tx_density = 1.25/0.7/0.7/0.7;
1719 curr_sckt_co_eff = 1.1296;
1720 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2
1721 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb
1722 }
1723
1724
1725 g_tp.peri_global.Vdd += curr_alpha * vdd[peri_global_tech_type];
1726 g_tp.peri_global.t_ox += curr_alpha * t_ox[peri_global_tech_type];
1727 g_tp.peri_global.Vth += curr_alpha * v_th[peri_global_tech_type];
1728 g_tp.peri_global.C_ox += curr_alpha * c_ox[peri_global_tech_type];
1729 g_tp.peri_global.C_g_ideal += curr_alpha * c_g_ideal[peri_global_tech_type];
1730 g_tp.peri_global.C_fringe += curr_alpha * c_fringe[peri_global_tech_type];
1731 g_tp.peri_global.C_junc += curr_alpha * c_junc[peri_global_tech_type];
1732 g_tp.peri_global.C_junc_sidewall = 0.25e-15; // F/micron
1733 g_tp.peri_global.l_phy += curr_alpha * Lphy[peri_global_tech_type];
1734 g_tp.peri_global.l_elec += curr_alpha * Lelec[peri_global_tech_type];
1735 g_tp.peri_global.I_on_n += curr_alpha * I_on_n[peri_global_tech_type];
1736 g_tp.peri_global.R_nch_on += curr_alpha * Rnchannelon[peri_global_tech_type];
1737 g_tp.peri_global.R_pch_on += curr_alpha * Rpchannelon[peri_global_tech_type];
1738 g_tp.peri_global.n_to_p_eff_curr_drv_ratio
1739 += curr_alpha * n_to_p_eff_curr_drv_ratio[peri_global_tech_type];
1740 g_tp.peri_global.long_channel_leakage_reduction
1741 += curr_alpha * long_channel_leakage_reduction[peri_global_tech_type];
1742 g_tp.peri_global.I_off_n += curr_alpha * I_off_n[peri_global_tech_type][g_ip->temp - 300];
1743 g_tp.peri_global.I_off_p += curr_alpha * I_off_n[peri_global_tech_type][g_ip->temp - 300];
1744 g_tp.peri_global.I_g_on_n += curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300];
1745 g_tp.peri_global.I_g_on_p += curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300];
1746 gmp_to_gmn_multiplier_periph_global += curr_alpha * gmp_to_gmn_multiplier[peri_global_tech_type];
1747
1748 g_tp.sram_cell.Vdd += curr_alpha * vdd[ram_cell_tech_type];
1749 g_tp.sram_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type];
1750 g_tp.sram_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type];
1751 g_tp.sram_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type];
1752 g_tp.sram_cell.Vth += curr_alpha * v_th[ram_cell_tech_type];
1753 g_tp.sram_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type];
1754 g_tp.sram_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type];
1755 g_tp.sram_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type];
1756 g_tp.sram_cell.C_junc_sidewall = 0.25e-15; // F/micron
1757 g_tp.sram_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type];
1758 g_tp.sram_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type];
1759 g_tp.sram_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type];
1760 g_tp.sram_cell.n_to_p_eff_curr_drv_ratio += curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type];
1761 g_tp.sram_cell.long_channel_leakage_reduction += curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type];
1762 g_tp.sram_cell.I_off_n += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300];
1763 g_tp.sram_cell.I_off_p += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300];
1764 g_tp.sram_cell.I_g_on_n += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300];
1765 g_tp.sram_cell.I_g_on_p += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300];
1766
1767 g_tp.dram_cell_Vdd += curr_alpha * curr_vdd_dram_cell;
1768 g_tp.dram_acc.Vth += curr_alpha * curr_v_th_dram_access_transistor;
1769 g_tp.dram_acc.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor];
1770 g_tp.dram_acc.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor];
1771 g_tp.dram_acc.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor];
1772 g_tp.dram_acc.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor];
1773 g_tp.dram_acc.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor];
1774 g_tp.dram_acc.C_junc_sidewall = 0.25e-15; // F/micron
1775 g_tp.dram_cell_I_on += curr_alpha * curr_I_on_dram_cell;
1776 g_tp.dram_cell_I_off_worst_case_len_temp += curr_alpha * curr_I_off_dram_cell_worst_case_length_temp;
1777 g_tp.dram_acc.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor];
1778 g_tp.dram_cell_C += curr_alpha * curr_c_dram_cell;
1779 g_tp.vpp += curr_alpha * curr_vpp;
1780 g_tp.dram_wl.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor];
1781 g_tp.dram_wl.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor];
1782 g_tp.dram_wl.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor];
1783 g_tp.dram_wl.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor];
1784 g_tp.dram_wl.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor];
1785 g_tp.dram_wl.C_junc_sidewall = 0.25e-15; // F/micron
1786 g_tp.dram_wl.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor];
1787 g_tp.dram_wl.R_nch_on += curr_alpha * Rnchannelon[dram_cell_tech_flavor];
1788 g_tp.dram_wl.R_pch_on += curr_alpha * Rpchannelon[dram_cell_tech_flavor];
1789 g_tp.dram_wl.n_to_p_eff_curr_drv_ratio += curr_alpha * n_to_p_eff_curr_drv_ratio[dram_cell_tech_flavor];
1790 g_tp.dram_wl.long_channel_leakage_reduction += curr_alpha * long_channel_leakage_reduction[dram_cell_tech_flavor];
1791 g_tp.dram_wl.I_off_n += curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300];
1792 g_tp.dram_wl.I_off_p += curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300];
1793
1794 g_tp.cam_cell.Vdd += curr_alpha * vdd[ram_cell_tech_type];
1795 g_tp.cam_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type];
1796 g_tp.cam_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type];
1797 g_tp.cam_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type];
1798 g_tp.cam_cell.Vth += curr_alpha * v_th[ram_cell_tech_type];
1799 g_tp.cam_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type];
1800 g_tp.cam_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type];
1801 g_tp.cam_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type];
1802 g_tp.cam_cell.C_junc_sidewall = 0.25e-15; // F/micron
1803 g_tp.cam_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type];
1804 g_tp.cam_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type];
1805 g_tp.cam_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type];
1806 g_tp.cam_cell.n_to_p_eff_curr_drv_ratio += curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type];
1807 g_tp.cam_cell.long_channel_leakage_reduction += curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type];
1808 g_tp.cam_cell.I_off_n += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300];
1809 g_tp.cam_cell.I_off_p += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300];
1810 g_tp.cam_cell.I_g_on_n += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300];
1811 g_tp.cam_cell.I_g_on_p += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300];
1812
1813 g_tp.dram.cell_a_w += curr_alpha * curr_Wmemcella_dram;
1814 g_tp.dram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_dram;
1815 g_tp.dram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_dram;
1816 area_cell_dram += curr_alpha * curr_area_cell_dram;
1817 asp_ratio_cell_dram += curr_alpha * curr_asp_ratio_cell_dram;
1818
1819 g_tp.sram.cell_a_w += curr_alpha * curr_Wmemcella_sram;
1820 g_tp.sram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_sram;
1821 g_tp.sram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_sram;
1822 area_cell_sram += curr_alpha * curr_area_cell_sram;
1823 asp_ratio_cell_sram += curr_alpha * curr_asp_ratio_cell_sram;
1824
1825 g_tp.cam.cell_a_w += curr_alpha * curr_Wmemcella_cam;//sheng
1826 g_tp.cam.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_cam;
1827 g_tp.cam.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_cam;
1828 area_cell_cam += curr_alpha * curr_area_cell_cam;
1829 asp_ratio_cell_cam += curr_alpha * curr_asp_ratio_cell_cam;
1830
1831 //Sense amplifier latch Gm calculation
1832 mobility_eff_periph_global += curr_alpha * mobility_eff[peri_global_tech_type];
1833 Vdsat_periph_global += curr_alpha * Vdsat[peri_global_tech_type];
1834
1835 //Empirical undifferetiated core/FU coefficient
1836 g_tp.scaling_factor.logic_scaling_co_eff += curr_alpha * curr_logic_scaling_co_eff;
1837 g_tp.scaling_factor.core_tx_density += curr_alpha * curr_core_tx_density;
1838 g_tp.chip_layout_overhead += curr_alpha * curr_chip_layout_overhead;
1839 g_tp.macro_layout_overhead += curr_alpha * curr_macro_layout_overhead;
1840 g_tp.sckt_co_eff += curr_alpha * curr_sckt_co_eff;
1841 }
1842
1843
1844 //Currently we are not modeling the resistance/capacitance of poly anywhere.
1845 //Continuous function (or date have been processed) does not need linear interpolation
1846 g_tp.w_comp_inv_p1 = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
1847 g_tp.w_comp_inv_n1 = 7.5 * g_ip->F_sz_um;//this was 6 micron for the 0.8 micron process
1848 g_tp.w_comp_inv_p2 = 25 * g_ip->F_sz_um;//this was 20 micron for the 0.8 micron process
1849 g_tp.w_comp_inv_n2 = 15 * g_ip->F_sz_um;//this was 12 micron for the 0.8 micron process
1850 g_tp.w_comp_inv_p3 = 50 * g_ip->F_sz_um;//this was 40 micron for the 0.8 micron process
1851 g_tp.w_comp_inv_n3 = 30 * g_ip->F_sz_um;//this was 24 micron for the 0.8 micron process
1852 g_tp.w_eval_inv_p = 100 * g_ip->F_sz_um;//this was 80 micron for the 0.8 micron process
1853 g_tp.w_eval_inv_n = 50 * g_ip->F_sz_um;//this was 40 micron for the 0.8 micron process
1854 g_tp.w_comp_n = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
1855 g_tp.w_comp_p = 37.5 * g_ip->F_sz_um;//this was 30 micron for the 0.8 micron process
1856
1857 g_tp.MIN_GAP_BET_P_AND_N_DIFFS = 5 * g_ip->F_sz_um;
1858 g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS = 1.5 * g_ip->F_sz_um;
1859 g_tp.HPOWERRAIL = 2 * g_ip->F_sz_um;
1860 g_tp.cell_h_def = 50 * g_ip->F_sz_um;
1861 g_tp.w_poly_contact = g_ip->F_sz_um;
1862 g_tp.spacing_poly_to_contact = g_ip->F_sz_um;
1863 g_tp.spacing_poly_to_poly = 1.5 * g_ip->F_sz_um;
1864 g_tp.ram_wl_stitching_overhead_ = 7.5 * g_ip->F_sz_um;
1865
1866 g_tp.min_w_nmos_ = 3 * g_ip->F_sz_um / 2;
1867 g_tp.max_w_nmos_ = 100 * g_ip->F_sz_um;
1868 g_tp.w_iso = 12.5*g_ip->F_sz_um;//was 10 micron for the 0.8 micron process
1869 g_tp.w_sense_n = 3.75*g_ip->F_sz_um; // sense amplifier N-trans; was 3 micron for the 0.8 micron process
1870 g_tp.w_sense_p = 7.5*g_ip->F_sz_um; // sense amplifier P-trans; was 6 micron for the 0.8 micron process
1871 g_tp.w_sense_en = 5*g_ip->F_sz_um; // Sense enable transistor of the sense amplifier; was 4 micron for the 0.8 micron process
1872 g_tp.w_nmos_b_mux = 6 * g_tp.min_w_nmos_;
1873 g_tp.w_nmos_sa_mux = 6 * g_tp.min_w_nmos_;
1874
1875 if (ram_cell_tech_type == comm_dram)
1876 {
1877 g_tp.max_w_nmos_dec = 8 * g_ip->F_sz_um;
1878 g_tp.h_dec = 8; // in the unit of memory cell height
1879 }
1880 else
1881 {
1882 g_tp.max_w_nmos_dec = g_tp.max_w_nmos_;
1883 g_tp.h_dec = 4; // in the unit of memory cell height
1884 }
1885
1886 g_tp.peri_global.C_overlap = 0.2 * g_tp.peri_global.C_g_ideal;
1887 g_tp.sram_cell.C_overlap = 0.2 * g_tp.sram_cell.C_g_ideal;
1888 g_tp.cam_cell.C_overlap = 0.2 * g_tp.cam_cell.C_g_ideal;
1889
1890 g_tp.dram_acc.C_overlap = 0.2 * g_tp.dram_acc.C_g_ideal;
1891 g_tp.dram_acc.R_nch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_n;
1892 //g_tp.dram_acc.R_pch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_p;
1893
1894 g_tp.dram_wl.C_overlap = 0.2 * g_tp.dram_wl.C_g_ideal;
1895
1896 double gmn_sense_amp_latch = (mobility_eff_periph_global / 2) * g_tp.peri_global.C_ox * (g_tp.w_sense_n / g_tp.peri_global.l_elec) * Vdsat_periph_global;
1897 double gmp_sense_amp_latch = gmp_to_gmn_multiplier_periph_global * gmn_sense_amp_latch;
1898 g_tp.gm_sense_amp_latch = gmn_sense_amp_latch + gmp_sense_amp_latch;
1899
1900 g_tp.dram.b_w = sqrt(area_cell_dram / (asp_ratio_cell_dram));
1901 g_tp.dram.b_h = asp_ratio_cell_dram * g_tp.dram.b_w;
1902 g_tp.sram.b_w = sqrt(area_cell_sram / (asp_ratio_cell_sram));
1903 g_tp.sram.b_h = asp_ratio_cell_sram * g_tp.sram.b_w;
1904 g_tp.cam.b_w = sqrt(area_cell_cam / (asp_ratio_cell_cam));//Sheng
1905 g_tp.cam.b_h = asp_ratio_cell_cam * g_tp.cam.b_w;
1906
1907 g_tp.dram.Vbitpre = g_tp.dram_cell_Vdd;
1908 g_tp.sram.Vbitpre = vdd[ram_cell_tech_type];
1909 g_tp.cam.Vbitpre = vdd[ram_cell_tech_type];//Sheng
1910 pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio();
1911 g_tp.w_pmos_bl_precharge = 6 * pmos_to_nmos_sizing_r * g_tp.min_w_nmos_;
1912 g_tp.w_pmos_bl_eq = pmos_to_nmos_sizing_r * g_tp.min_w_nmos_;
1913
1914
1915 double wire_pitch [NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES],
1916 wire_r_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES],
1917 wire_c_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES],
1918 horiz_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES],
1919 vert_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES],
1920 aspect_ratio[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES],
1921 miller_value[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES],
1922 ild_thickness[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES];
1923
1924 for (iter=0; iter<=1; ++iter)
1925 {
1926 // linear interpolation
1927 if (iter == 0)
1928 {
1929 tech = tech_lo;
1930 if (tech_lo == tech_hi)
1931 {
1932 curr_alpha = 1;
1933 }
1934 else
1935 {
1936 curr_alpha = (technology - tech_hi)/(tech_lo - tech_hi);
1937 }
1938 }
1939 else
1940 {
1941 tech = tech_hi;
1942 if (tech_lo == tech_hi)
1943 {
1944 break;
1945 }
1946 else
1947 {
1948 curr_alpha = (tech_lo - technology)/(tech_lo - tech_hi);
1949 }
1950 }
1951
1952 if (tech == 180)
1953 {
1954 //Aggressive projections
1955 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//micron
1956 aspect_ratio[0][0] = 2.0;
1957 wire_width = wire_pitch[0][0] / 2; //micron
1958 wire_thickness = aspect_ratio[0][0] * wire_width;//micron
1959 wire_spacing = wire_pitch[0][0] - wire_width;//micron
1960 barrier_thickness = 0.017;//micron
1961 dishing_thickness = 0;//micron
1962 alpha_scatter = 1;
1963 wire_r_per_micron[0][0] = wire_resistance(CU_RESISTIVITY, wire_width,
1964 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);//ohm/micron
1965 ild_thickness[0][0] = 0.75;//micron
1966 miller_value[0][0] = 1.5;
1967 horiz_dielectric_constant[0][0] = 2.709;
1968 vert_dielectric_constant[0][0] = 3.9;
1969 fringe_cap = 0.115e-15; //F/micron
1970 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
1971 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0],
1972 vert_dielectric_constant[0][0],
1973 fringe_cap);//F/micron.
1974
1975 wire_pitch[0][1] = 4 * g_ip->F_sz_um;
1976 wire_width = wire_pitch[0][1] / 2;
1977 aspect_ratio[0][1] = 2.4;
1978 wire_thickness = aspect_ratio[0][1] * wire_width;
1979 wire_spacing = wire_pitch[0][1] - wire_width;
1980 wire_r_per_micron[0][1] = wire_resistance(CU_RESISTIVITY, wire_width,
1981 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
1982 ild_thickness[0][1] = 0.75;//micron
1983 miller_value[0][1] = 1.5;
1984 horiz_dielectric_constant[0][1] = 2.709;
1985 vert_dielectric_constant[0][1] = 3.9;
1986 fringe_cap = 0.115e-15; //F/micron
1987 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
1988 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1],
1989 vert_dielectric_constant[0][1],
1990 fringe_cap);
1991
1992 wire_pitch[0][2] = 8 * g_ip->F_sz_um;
1993 aspect_ratio[0][2] = 2.2;
1994 wire_width = wire_pitch[0][2] / 2;
1995 wire_thickness = aspect_ratio[0][2] * wire_width;
1996 wire_spacing = wire_pitch[0][2] - wire_width;
1997 wire_r_per_micron[0][2] = wire_resistance(CU_RESISTIVITY, wire_width,
1998 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
1999 ild_thickness[0][2] = 1.5;
2000 miller_value[0][2] = 1.5;
2001 horiz_dielectric_constant[0][2] = 2.709;
2002 vert_dielectric_constant[0][2] = 3.9;
2003 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2004 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2],
2005 fringe_cap);
2006
2007 //Conservative projections
2008 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um;
2009 aspect_ratio[1][0]= 2.0;
2010 wire_width = wire_pitch[1][0] / 2;
2011 wire_thickness = aspect_ratio[1][0] * wire_width;
2012 wire_spacing = wire_pitch[1][0] - wire_width;
2013 barrier_thickness = 0.017;
2014 dishing_thickness = 0;
2015 alpha_scatter = 1;
2016 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width,
2017 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2018 ild_thickness[1][0] = 0.75;
2019 miller_value[1][0] = 1.5;
2020 horiz_dielectric_constant[1][0] = 3.038;
2021 vert_dielectric_constant[1][0] = 3.9;
2022 fringe_cap = 0.115e-15;
2023 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2024 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0],
2025 vert_dielectric_constant[1][0],
2026 fringe_cap);
2027
2028 wire_pitch[1][1] = 4 * g_ip->F_sz_um;
2029 wire_width = wire_pitch[1][1] / 2;
2030 aspect_ratio[1][1] = 2.0;
2031 wire_thickness = aspect_ratio[1][1] * wire_width;
2032 wire_spacing = wire_pitch[1][1] - wire_width;
2033 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width,
2034 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2035 ild_thickness[1][1] = 0.75;
2036 miller_value[1][1] = 1.5;
2037 horiz_dielectric_constant[1][1] = 3.038;
2038 vert_dielectric_constant[1][1] = 3.9;
2039 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2040 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1],
2041 vert_dielectric_constant[1][1],
2042 fringe_cap);
2043
2044 wire_pitch[1][2] = 8 * g_ip->F_sz_um;
2045 aspect_ratio[1][2] = 2.2;
2046 wire_width = wire_pitch[1][2] / 2;
2047 wire_thickness = aspect_ratio[1][2] * wire_width;
2048 wire_spacing = wire_pitch[1][2] - wire_width;
2049 dishing_thickness = 0.1 * wire_thickness;
2050 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width,
2051 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2052 ild_thickness[1][2] = 1.98;
2053 miller_value[1][2] = 1.5;
2054 horiz_dielectric_constant[1][2] = 3.038;
2055 vert_dielectric_constant[1][2] = 3.9;
2056 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2057 ild_thickness[1][2] , miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2],
2058 fringe_cap);
2059 //Nominal projections for commodity DRAM wordline/bitline
2060 wire_pitch[1][3] = 2 * 0.18;
2061 wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.18);
2062 wire_r_per_micron[1][3] = 12 / 0.18;
2063 }
2064 else if (tech == 90)
2065 {
2066 //Aggressive projections
2067 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//micron
2068 aspect_ratio[0][0] = 2.4;
2069 wire_width = wire_pitch[0][0] / 2; //micron
2070 wire_thickness = aspect_ratio[0][0] * wire_width;//micron
2071 wire_spacing = wire_pitch[0][0] - wire_width;//micron
2072 barrier_thickness = 0.01;//micron
2073 dishing_thickness = 0;//micron
2074 alpha_scatter = 1;
2075 wire_r_per_micron[0][0] = wire_resistance(CU_RESISTIVITY, wire_width,
2076 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);//ohm/micron
2077 ild_thickness[0][0] = 0.48;//micron
2078 miller_value[0][0] = 1.5;
2079 horiz_dielectric_constant[0][0] = 2.709;
2080 vert_dielectric_constant[0][0] = 3.9;
2081 fringe_cap = 0.115e-15; //F/micron
2082 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2083 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0],
2084 vert_dielectric_constant[0][0],
2085 fringe_cap);//F/micron.
2086
2087 wire_pitch[0][1] = 4 * g_ip->F_sz_um;
2088 wire_width = wire_pitch[0][1] / 2;
2089 aspect_ratio[0][1] = 2.4;
2090 wire_thickness = aspect_ratio[0][1] * wire_width;
2091 wire_spacing = wire_pitch[0][1] - wire_width;
2092 wire_r_per_micron[0][1] = wire_resistance(CU_RESISTIVITY, wire_width,
2093 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2094 ild_thickness[0][1] = 0.48;//micron
2095 miller_value[0][1] = 1.5;
2096 horiz_dielectric_constant[0][1] = 2.709;
2097 vert_dielectric_constant[0][1] = 3.9;
2098 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2099 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1],
2100 vert_dielectric_constant[0][1],
2101 fringe_cap);
2102
2103 wire_pitch[0][2] = 8 * g_ip->F_sz_um;
2104 aspect_ratio[0][2] = 2.7;
2105 wire_width = wire_pitch[0][2] / 2;
2106 wire_thickness = aspect_ratio[0][2] * wire_width;
2107 wire_spacing = wire_pitch[0][2] - wire_width;
2108 wire_r_per_micron[0][2] = wire_resistance(CU_RESISTIVITY, wire_width,
2109 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2110 ild_thickness[0][2] = 0.96;
2111 miller_value[0][2] = 1.5;
2112 horiz_dielectric_constant[0][2] = 2.709;
2113 vert_dielectric_constant[0][2] = 3.9;
2114 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2115 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2],
2116 fringe_cap);
2117
2118 //Conservative projections
2119 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um;
2120 aspect_ratio[1][0] = 2.0;
2121 wire_width = wire_pitch[1][0] / 2;
2122 wire_thickness = aspect_ratio[1][0] * wire_width;
2123 wire_spacing = wire_pitch[1][0] - wire_width;
2124 barrier_thickness = 0.008;
2125 dishing_thickness = 0;
2126 alpha_scatter = 1;
2127 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width,
2128 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2129 ild_thickness[1][0] = 0.48;
2130 miller_value[1][0] = 1.5;
2131 horiz_dielectric_constant[1][0] = 3.038;
2132 vert_dielectric_constant[1][0] = 3.9;
2133 fringe_cap = 0.115e-15;
2134 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2135 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0],
2136 vert_dielectric_constant[1][0],
2137 fringe_cap);
2138
2139 wire_pitch[1][1] = 4 * g_ip->F_sz_um;
2140 wire_width = wire_pitch[1][1] / 2;
2141 aspect_ratio[1][1] = 2.0;
2142 wire_thickness = aspect_ratio[1][1] * wire_width;
2143 wire_spacing = wire_pitch[1][1] - wire_width;
2144 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width,
2145 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2146 ild_thickness[1][1] = 0.48;
2147 miller_value[1][1] = 1.5;
2148 horiz_dielectric_constant[1][1] = 3.038;
2149 vert_dielectric_constant[1][1] = 3.9;
2150 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2151 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1],
2152 vert_dielectric_constant[1][1],
2153 fringe_cap);
2154
2155 wire_pitch[1][2] = 8 * g_ip->F_sz_um;
2156 aspect_ratio[1][2] = 2.2;
2157 wire_width = wire_pitch[1][2] / 2;
2158 wire_thickness = aspect_ratio[1][2] * wire_width;
2159 wire_spacing = wire_pitch[1][2] - wire_width;
2160 dishing_thickness = 0.1 * wire_thickness;
2161 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width,
2162 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2163 ild_thickness[1][2] = 1.1;
2164 miller_value[1][2] = 1.5;
2165 horiz_dielectric_constant[1][2] = 3.038;
2166 vert_dielectric_constant[1][2] = 3.9;
2167 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2168 ild_thickness[1][2] , miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2],
2169 fringe_cap);
2170 //Nominal projections for commodity DRAM wordline/bitline
2171 wire_pitch[1][3] = 2 * 0.09;
2172 wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.09);
2173 wire_r_per_micron[1][3] = 12 / 0.09;
2174 }
2175 else if (tech == 65)
2176 {
2177 //Aggressive projections
2178 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;
2179 aspect_ratio[0][0] = 2.7;
2180 wire_width = wire_pitch[0][0] / 2;
2181 wire_thickness = aspect_ratio[0][0] * wire_width;
2182 wire_spacing = wire_pitch[0][0] - wire_width;
2183 barrier_thickness = 0;
2184 dishing_thickness = 0;
2185 alpha_scatter = 1;
2186 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2187 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2188 ild_thickness[0][0] = 0.405;
2189 miller_value[0][0] = 1.5;
2190 horiz_dielectric_constant[0][0] = 2.303;
2191 vert_dielectric_constant[0][0] = 3.9;
2192 fringe_cap = 0.115e-15;
2193 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2194 ild_thickness[0][0] , miller_value[0][0] , horiz_dielectric_constant[0][0] , vert_dielectric_constant[0][0] ,
2195 fringe_cap);
2196
2197 wire_pitch[0][1] = 4 * g_ip->F_sz_um;
2198 wire_width = wire_pitch[0][1] / 2;
2199 aspect_ratio[0][1] = 2.7;
2200 wire_thickness = aspect_ratio[0][1] * wire_width;
2201 wire_spacing = wire_pitch[0][1] - wire_width;
2202 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2203 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2204 ild_thickness[0][1] = 0.405;
2205 miller_value[0][1] = 1.5;
2206 horiz_dielectric_constant[0][1] = 2.303;
2207 vert_dielectric_constant[0][1] = 3.9;
2208 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2209 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1],
2210 vert_dielectric_constant[0][1],
2211 fringe_cap);
2212
2213 wire_pitch[0][2] = 8 * g_ip->F_sz_um;
2214 aspect_ratio[0][2] = 2.8;
2215 wire_width = wire_pitch[0][2] / 2;
2216 wire_thickness = aspect_ratio[0][2] * wire_width;
2217 wire_spacing = wire_pitch[0][2] - wire_width;
2218 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2219 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2220 ild_thickness[0][2] = 0.81;
2221 miller_value[0][2] = 1.5;
2222 horiz_dielectric_constant[0][2] = 2.303;
2223 vert_dielectric_constant[0][2] = 3.9;
2224 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2225 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2],
2226 fringe_cap);
2227
2228 //Conservative projections
2229 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um;
2230 aspect_ratio[1][0] = 2.0;
2231 wire_width = wire_pitch[1][0] / 2;
2232 wire_thickness = aspect_ratio[1][0] * wire_width;
2233 wire_spacing = wire_pitch[1][0] - wire_width;
2234 barrier_thickness = 0.006;
2235 dishing_thickness = 0;
2236 alpha_scatter = 1;
2237 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width,
2238 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2239 ild_thickness[1][0] = 0.405;
2240 miller_value[1][0] = 1.5;
2241 horiz_dielectric_constant[1][0] = 2.734;
2242 vert_dielectric_constant[1][0] = 3.9;
2243 fringe_cap = 0.115e-15;
2244 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2245 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0],
2246 fringe_cap);
2247
2248 wire_pitch[1][1] = 4 * g_ip->F_sz_um;
2249 wire_width = wire_pitch[1][1] / 2;
2250 aspect_ratio[1][1] = 2.0;
2251 wire_thickness = aspect_ratio[1][1] * wire_width;
2252 wire_spacing = wire_pitch[1][1] - wire_width;
2253 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width,
2254 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2255 ild_thickness[1][1] = 0.405;
2256 miller_value[1][1] = 1.5;
2257 horiz_dielectric_constant[1][1] = 2.734;
2258 vert_dielectric_constant[1][1] = 3.9;
2259 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2260 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1],
2261 fringe_cap);
2262
2263 wire_pitch[1][2] = 8 * g_ip->F_sz_um;
2264 aspect_ratio[1][2] = 2.2;
2265 wire_width = wire_pitch[1][2] / 2;
2266 wire_thickness = aspect_ratio[1][2] * wire_width;
2267 wire_spacing = wire_pitch[1][2] - wire_width;
2268 dishing_thickness = 0.1 * wire_thickness;
2269 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width,
2270 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2271 ild_thickness[1][2] = 0.77;
2272 miller_value[1][2] = 1.5;
2273 horiz_dielectric_constant[1][2] = 2.734;
2274 vert_dielectric_constant[1][2] = 3.9;
2275 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2276 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2],
2277 fringe_cap);
2278 //Nominal projections for commodity DRAM wordline/bitline
2279 wire_pitch[1][3] = 2 * 0.065;
2280 wire_c_per_micron[1][3] = 52.5e-15 / (256 * 2 * 0.065);
2281 wire_r_per_micron[1][3] = 12 / 0.065;
2282 }
2283 else if (tech == 45)
2284 {
2285 //Aggressive projections.
2286 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;
2287 aspect_ratio[0][0] = 3.0;
2288 wire_width = wire_pitch[0][0] / 2;
2289 wire_thickness = aspect_ratio[0][0] * wire_width;
2290 wire_spacing = wire_pitch[0][0] - wire_width;
2291 barrier_thickness = 0;
2292 dishing_thickness = 0;
2293 alpha_scatter = 1;
2294 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2295 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2296 ild_thickness[0][0] = 0.315;
2297 miller_value[0][0] = 1.5;
2298 horiz_dielectric_constant[0][0] = 1.958;
2299 vert_dielectric_constant[0][0] = 3.9;
2300 fringe_cap = 0.115e-15;
2301 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2302 ild_thickness[0][0] , miller_value[0][0] , horiz_dielectric_constant[0][0] , vert_dielectric_constant[0][0] ,
2303 fringe_cap);
2304
2305 wire_pitch[0][1] = 4 * g_ip->F_sz_um;
2306 wire_width = wire_pitch[0][1] / 2;
2307 aspect_ratio[0][1] = 3.0;
2308 wire_thickness = aspect_ratio[0][1] * wire_width;
2309 wire_spacing = wire_pitch[0][1] - wire_width;
2310 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2311 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2312 ild_thickness[0][1] = 0.315;
2313 miller_value[0][1] = 1.5;
2314 horiz_dielectric_constant[0][1] = 1.958;
2315 vert_dielectric_constant[0][1] = 3.9;
2316 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2317 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1],
2318 fringe_cap);
2319
2320 wire_pitch[0][2] = 8 * g_ip->F_sz_um;
2321 aspect_ratio[0][2] = 3.0;
2322 wire_width = wire_pitch[0][2] / 2;
2323 wire_thickness = aspect_ratio[0][2] * wire_width;
2324 wire_spacing = wire_pitch[0][2] - wire_width;
2325 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2326 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2327 ild_thickness[0][2] = 0.63;
2328 miller_value[0][2] = 1.5;
2329 horiz_dielectric_constant[0][2] = 1.958;
2330 vert_dielectric_constant[0][2] = 3.9;
2331 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2332 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2],
2333 fringe_cap);
2334
2335 //Conservative projections
2336 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um;
2337 aspect_ratio[1][0] = 2.0;
2338 wire_width = wire_pitch[1][0] / 2;
2339 wire_thickness = aspect_ratio[1][0] * wire_width;
2340 wire_spacing = wire_pitch[1][0] - wire_width;
2341 barrier_thickness = 0.004;
2342 dishing_thickness = 0;
2343 alpha_scatter = 1;
2344 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width,
2345 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2346 ild_thickness[1][0] = 0.315;
2347 miller_value[1][0] = 1.5;
2348 horiz_dielectric_constant[1][0] = 2.46;
2349 vert_dielectric_constant[1][0] = 3.9;
2350 fringe_cap = 0.115e-15;
2351 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2352 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0],
2353 fringe_cap);
2354
2355 wire_pitch[1][1] = 4 * g_ip->F_sz_um;
2356 wire_width = wire_pitch[1][1] / 2;
2357 aspect_ratio[1][1] = 2.0;
2358 wire_thickness = aspect_ratio[1][1] * wire_width;
2359 wire_spacing = wire_pitch[1][1] - wire_width;
2360 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width,
2361 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2362 ild_thickness[1][1] = 0.315;
2363 miller_value[1][1] = 1.5;
2364 horiz_dielectric_constant[1][1] = 2.46;
2365 vert_dielectric_constant[1][1] = 3.9;
2366 fringe_cap = 0.115e-15;
2367 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2368 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1],
2369 fringe_cap);
2370
2371 wire_pitch[1][2] = 8 * g_ip->F_sz_um;
2372 aspect_ratio[1][2] = 2.2;
2373 wire_width = wire_pitch[1][2] / 2;
2374 wire_thickness = aspect_ratio[1][2] * wire_width;
2375 wire_spacing = wire_pitch[1][2] - wire_width;
2376 dishing_thickness = 0.1 * wire_thickness;
2377 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width,
2378 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2379 ild_thickness[1][2] = 0.55;
2380 miller_value[1][2] = 1.5;
2381 horiz_dielectric_constant[1][2] = 2.46;
2382 vert_dielectric_constant[1][2] = 3.9;
2383 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2384 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2],
2385 fringe_cap);
2386 //Nominal projections for commodity DRAM wordline/bitline
2387 wire_pitch[1][3] = 2 * 0.045;
2388 wire_c_per_micron[1][3] = 37.5e-15 / (256 * 2 * 0.045);
2389 wire_r_per_micron[1][3] = 12 / 0.045;
2390 }
2391 else if (tech == 32)
2392 {
2393 //Aggressive projections.
2394 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;
2395 aspect_ratio[0][0] = 3.0;
2396 wire_width = wire_pitch[0][0] / 2;
2397 wire_thickness = aspect_ratio[0][0] * wire_width;
2398 wire_spacing = wire_pitch[0][0] - wire_width;
2399 barrier_thickness = 0;
2400 dishing_thickness = 0;
2401 alpha_scatter = 1;
2402 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2403 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2404 ild_thickness[0][0] = 0.21;
2405 miller_value[0][0] = 1.5;
2406 horiz_dielectric_constant[0][0] = 1.664;
2407 vert_dielectric_constant[0][0] = 3.9;
2408 fringe_cap = 0.115e-15;
2409 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2410 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], vert_dielectric_constant[0][0],
2411 fringe_cap);
2412
2413 wire_pitch[0][1] = 4 * g_ip->F_sz_um;
2414 wire_width = wire_pitch[0][1] / 2;
2415 aspect_ratio[0][1] = 3.0;
2416 wire_thickness = aspect_ratio[0][1] * wire_width;
2417 wire_spacing = wire_pitch[0][1] - wire_width;
2418 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2419 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2420 ild_thickness[0][1] = 0.21;
2421 miller_value[0][1] = 1.5;
2422 horiz_dielectric_constant[0][1] = 1.664;
2423 vert_dielectric_constant[0][1] = 3.9;
2424 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2425 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1],
2426 fringe_cap);
2427
2428 wire_pitch[0][2] = 8 * g_ip->F_sz_um;
2429 aspect_ratio[0][2] = 3.0;
2430 wire_width = wire_pitch[0][2] / 2;
2431 wire_thickness = aspect_ratio[0][2] * wire_width;
2432 wire_spacing = wire_pitch[0][2] - wire_width;
2433 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2434 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2435 ild_thickness[0][2] = 0.42;
2436 miller_value[0][2] = 1.5;
2437 horiz_dielectric_constant[0][2] = 1.664;
2438 vert_dielectric_constant[0][2] = 3.9;
2439 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2440 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2],
2441 fringe_cap);
2442
2443 //Conservative projections
2444 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um;
2445 aspect_ratio[1][0] = 2.0;
2446 wire_width = wire_pitch[1][0] / 2;
2447 wire_thickness = aspect_ratio[1][0] * wire_width;
2448 wire_spacing = wire_pitch[1][0] - wire_width;
2449 barrier_thickness = 0.003;
2450 dishing_thickness = 0;
2451 alpha_scatter = 1;
2452 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width,
2453 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2454 ild_thickness[1][0] = 0.21;
2455 miller_value[1][0] = 1.5;
2456 horiz_dielectric_constant[1][0] = 2.214;
2457 vert_dielectric_constant[1][0] = 3.9;
2458 fringe_cap = 0.115e-15;
2459 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2460 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0],
2461 fringe_cap);
2462
2463 wire_pitch[1][1] = 4 * g_ip->F_sz_um;
2464 aspect_ratio[1][1] = 2.0;
2465 wire_width = wire_pitch[1][1] / 2;
2466 wire_thickness = aspect_ratio[1][1] * wire_width;
2467 wire_spacing = wire_pitch[1][1] - wire_width;
2468 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width,
2469 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2470 ild_thickness[1][1] = 0.21;
2471 miller_value[1][1] = 1.5;
2472 horiz_dielectric_constant[1][1] = 2.214;
2473 vert_dielectric_constant[1][1] = 3.9;
2474 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2475 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1],
2476 fringe_cap);
2477
2478 wire_pitch[1][2] = 8 * g_ip->F_sz_um;
2479 aspect_ratio[1][2] = 2.2;
2480 wire_width = wire_pitch[1][2] / 2;
2481 wire_thickness = aspect_ratio[1][2] * wire_width;
2482 wire_spacing = wire_pitch[1][2] - wire_width;
2483 dishing_thickness = 0.1 * wire_thickness;
2484 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width,
2485 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2486 ild_thickness[1][2] = 0.385;
2487 miller_value[1][2] = 1.5;
2488 horiz_dielectric_constant[1][2] = 2.214;
2489 vert_dielectric_constant[1][2] = 3.9;
2490 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2491 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2],
2492 fringe_cap);
2493 //Nominal projections for commodity DRAM wordline/bitline
2494 wire_pitch[1][3] = 2 * 0.032;//micron
2495 wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.032);//F/micron
2496 wire_r_per_micron[1][3] = 12 / 0.032;//ohm/micron
2497 }
2498 else if (tech == 22)
2499 {
2500 //Aggressive projections.
2501 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//local
2502 aspect_ratio[0][0] = 3.0;
2503 wire_width = wire_pitch[0][0] / 2;
2504 wire_thickness = aspect_ratio[0][0] * wire_width;
2505 wire_spacing = wire_pitch[0][0] - wire_width;
2506 barrier_thickness = 0;
2507 dishing_thickness = 0;
2508 alpha_scatter = 1;
2509 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2510 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2511 ild_thickness[0][0] = 0.15;
2512 miller_value[0][0] = 1.5;
2513 horiz_dielectric_constant[0][0] = 1.414;
2514 vert_dielectric_constant[0][0] = 3.9;
2515 fringe_cap = 0.115e-15;
2516 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2517 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], vert_dielectric_constant[0][0],
2518 fringe_cap);
2519
2520 wire_pitch[0][1] = 4 * g_ip->F_sz_um;//semi-global
2521 wire_width = wire_pitch[0][1] / 2;
2522 aspect_ratio[0][1] = 3.0;
2523 wire_thickness = aspect_ratio[0][1] * wire_width;
2524 wire_spacing = wire_pitch[0][1] - wire_width;
2525 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2526 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2527 ild_thickness[0][1] = 0.15;
2528 miller_value[0][1] = 1.5;
2529 horiz_dielectric_constant[0][1] = 1.414;
2530 vert_dielectric_constant[0][1] = 3.9;
2531 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2532 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1],
2533 fringe_cap);
2534
2535 wire_pitch[0][2] = 8 * g_ip->F_sz_um;//global
2536 aspect_ratio[0][2] = 3.0;
2537 wire_width = wire_pitch[0][2] / 2;
2538 wire_thickness = aspect_ratio[0][2] * wire_width;
2539 wire_spacing = wire_pitch[0][2] - wire_width;
2540 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2541 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2542 ild_thickness[0][2] = 0.3;
2543 miller_value[0][2] = 1.5;
2544 horiz_dielectric_constant[0][2] = 1.414;
2545 vert_dielectric_constant[0][2] = 3.9;
2546 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2547 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2],
2548 fringe_cap);
2549
2550 // //*************************
2551 // wire_pitch[0][4] = 16 * g_ip.F_sz_um;//global
2552 // aspect_ratio = 3.0;
2553 // wire_width = wire_pitch[0][4] / 2;
2554 // wire_thickness = aspect_ratio * wire_width;
2555 // wire_spacing = wire_pitch[0][4] - wire_width;
2556 // wire_r_per_micron[0][4] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2557 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2558 // ild_thickness = 0.3;
2559 // wire_c_per_micron[0][4] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2560 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2561 // fringe_cap);
2562 //
2563 // wire_pitch[0][5] = 24 * g_ip.F_sz_um;//global
2564 // aspect_ratio = 3.0;
2565 // wire_width = wire_pitch[0][5] / 2;
2566 // wire_thickness = aspect_ratio * wire_width;
2567 // wire_spacing = wire_pitch[0][5] - wire_width;
2568 // wire_r_per_micron[0][5] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2569 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2570 // ild_thickness = 0.3;
2571 // wire_c_per_micron[0][5] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2572 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2573 // fringe_cap);
2574 //
2575 // wire_pitch[0][6] = 32 * g_ip.F_sz_um;//global
2576 // aspect_ratio = 3.0;
2577 // wire_width = wire_pitch[0][6] / 2;
2578 // wire_thickness = aspect_ratio * wire_width;
2579 // wire_spacing = wire_pitch[0][6] - wire_width;
2580 // wire_r_per_micron[0][6] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2581 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2582 // ild_thickness = 0.3;
2583 // wire_c_per_micron[0][6] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2584 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2585 // fringe_cap);
2586 //*************************
2587
2588 //Conservative projections
2589 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um;
2590 aspect_ratio[1][0] = 2.0;
2591 wire_width = wire_pitch[1][0] / 2;
2592 wire_thickness = aspect_ratio[1][0] * wire_width;
2593 wire_spacing = wire_pitch[1][0] - wire_width;
2594 barrier_thickness = 0.003;
2595 dishing_thickness = 0;
2596 alpha_scatter = 1.05;
2597 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width,
2598 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2599 ild_thickness[1][0] = 0.15;
2600 miller_value[1][0] = 1.5;
2601 horiz_dielectric_constant[1][0] = 2.104;
2602 vert_dielectric_constant[1][0] = 3.9;
2603 fringe_cap = 0.115e-15;
2604 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2605 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0],
2606 fringe_cap);
2607
2608 wire_pitch[1][1] = 4 * g_ip->F_sz_um;
2609 wire_width = wire_pitch[1][1] / 2;
2610 aspect_ratio[1][1] = 2.0;
2611 wire_thickness = aspect_ratio[1][1] * wire_width;
2612 wire_spacing = wire_pitch[1][1] - wire_width;
2613 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width,
2614 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2615 ild_thickness[1][1] = 0.15;
2616 miller_value[1][1] = 1.5;
2617 horiz_dielectric_constant[1][1] = 2.104;
2618 vert_dielectric_constant[1][1] = 3.9;
2619 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2620 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1],
2621 fringe_cap);
2622
2623 wire_pitch[1][2] = 8 * g_ip->F_sz_um;
2624 aspect_ratio[1][2] = 2.2;
2625 wire_width = wire_pitch[1][2] / 2;
2626 wire_thickness = aspect_ratio[1][2] * wire_width;
2627 wire_spacing = wire_pitch[1][2] - wire_width;
2628 dishing_thickness = 0.1 * wire_thickness;
2629 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width,
2630 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2631 ild_thickness[1][2] = 0.275;
2632 miller_value[1][2] = 1.5;
2633 horiz_dielectric_constant[1][2] = 2.104;
2634 vert_dielectric_constant[1][2] = 3.9;
2635 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2636 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2],
2637 fringe_cap);
2638 //Nominal projections for commodity DRAM wordline/bitline
2639 wire_pitch[1][3] = 2 * 0.022;//micron
2640 wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.022);//F/micron
2641 wire_r_per_micron[1][3] = 12 / 0.022;//ohm/micron
2642
2643 //******************
2644 // wire_pitch[1][4] = 16 * g_ip.F_sz_um;
2645 // aspect_ratio = 2.2;
2646 // wire_width = wire_pitch[1][4] / 2;
2647 // wire_thickness = aspect_ratio * wire_width;
2648 // wire_spacing = wire_pitch[1][4] - wire_width;
2649 // dishing_thickness = 0.1 * wire_thickness;
2650 // wire_r_per_micron[1][4] = wire_resistance(CU_RESISTIVITY, wire_width,
2651 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2652 // ild_thickness = 0.275;
2653 // wire_c_per_micron[1][4] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2654 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2655 // fringe_cap);
2656 //
2657 // wire_pitch[1][5] = 24 * g_ip.F_sz_um;
2658 // aspect_ratio = 2.2;
2659 // wire_width = wire_pitch[1][5] / 2;
2660 // wire_thickness = aspect_ratio * wire_width;
2661 // wire_spacing = wire_pitch[1][5] - wire_width;
2662 // dishing_thickness = 0.1 * wire_thickness;
2663 // wire_r_per_micron[1][5] = wire_resistance(CU_RESISTIVITY, wire_width,
2664 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2665 // ild_thickness = 0.275;
2666 // wire_c_per_micron[1][5] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2667 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2668 // fringe_cap);
2669 //
2670 // wire_pitch[1][6] = 32 * g_ip.F_sz_um;
2671 // aspect_ratio = 2.2;
2672 // wire_width = wire_pitch[1][6] / 2;
2673 // wire_thickness = aspect_ratio * wire_width;
2674 // wire_spacing = wire_pitch[1][6] - wire_width;
2675 // dishing_thickness = 0.1 * wire_thickness;
2676 // wire_r_per_micron[1][6] = wire_resistance(CU_RESISTIVITY, wire_width,
2677 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2678 // ild_thickness = 0.275;
2679 // wire_c_per_micron[1][6] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2680 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2681 // fringe_cap);
2682 }
2683
2684 else if (tech == 16)
2685 {
2686 //Aggressive projections.
2687 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//local
2688 aspect_ratio[0][0] = 3.0;
2689 wire_width = wire_pitch[0][0] / 2;
2690 wire_thickness = aspect_ratio[0][0] * wire_width;
2691 wire_spacing = wire_pitch[0][0] - wire_width;
2692 barrier_thickness = 0;
2693 dishing_thickness = 0;
2694 alpha_scatter = 1;
2695 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2696 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2697 ild_thickness[0][0] = 0.108;
2698 miller_value[0][0] = 1.5;
2699 horiz_dielectric_constant[0][0] = 1.202;
2700 vert_dielectric_constant[0][0] = 3.9;
2701 fringe_cap = 0.115e-15;
2702 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2703 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], vert_dielectric_constant[0][0],
2704 fringe_cap);
2705
2706 wire_pitch[0][1] = 4 * g_ip->F_sz_um;//semi-global
2707 aspect_ratio[0][1] = 3.0;
2708 wire_width = wire_pitch[0][1] / 2;
2709 wire_thickness = aspect_ratio[0][1] * wire_width;
2710 wire_spacing = wire_pitch[0][1] - wire_width;
2711 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2712 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2713 ild_thickness[0][1] = 0.108;
2714 miller_value[0][1] = 1.5;
2715 horiz_dielectric_constant[0][1] = 1.202;
2716 vert_dielectric_constant[0][1] = 3.9;
2717 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2718 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1],
2719 fringe_cap);
2720
2721 wire_pitch[0][2] = 8 * g_ip->F_sz_um;//global
2722 aspect_ratio[0][2] = 3.0;
2723 wire_width = wire_pitch[0][2] / 2;
2724 wire_thickness = aspect_ratio[0][2] * wire_width;
2725 wire_spacing = wire_pitch[0][2] - wire_width;
2726 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2727 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2728 ild_thickness[0][2] = 0.216;
2729 miller_value[0][2] = 1.5;
2730 horiz_dielectric_constant[0][2] = 1.202;
2731 vert_dielectric_constant[0][2] = 3.9;
2732 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2733 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2],
2734 fringe_cap);
2735
2736 // //*************************
2737 // wire_pitch[0][4] = 16 * g_ip.F_sz_um;//global
2738 // aspect_ratio = 3.0;
2739 // wire_width = wire_pitch[0][4] / 2;
2740 // wire_thickness = aspect_ratio * wire_width;
2741 // wire_spacing = wire_pitch[0][4] - wire_width;
2742 // wire_r_per_micron[0][4] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2743 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2744 // ild_thickness = 0.3;
2745 // wire_c_per_micron[0][4] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2746 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2747 // fringe_cap);
2748 //
2749 // wire_pitch[0][5] = 24 * g_ip.F_sz_um;//global
2750 // aspect_ratio = 3.0;
2751 // wire_width = wire_pitch[0][5] / 2;
2752 // wire_thickness = aspect_ratio * wire_width;
2753 // wire_spacing = wire_pitch[0][5] - wire_width;
2754 // wire_r_per_micron[0][5] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2755 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2756 // ild_thickness = 0.3;
2757 // wire_c_per_micron[0][5] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2758 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2759 // fringe_cap);
2760 //
2761 // wire_pitch[0][6] = 32 * g_ip.F_sz_um;//global
2762 // aspect_ratio = 3.0;
2763 // wire_width = wire_pitch[0][6] / 2;
2764 // wire_thickness = aspect_ratio * wire_width;
2765 // wire_spacing = wire_pitch[0][6] - wire_width;
2766 // wire_r_per_micron[0][6] = wire_resistance(BULK_CU_RESISTIVITY, wire_width,
2767 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2768 // ild_thickness = 0.3;
2769 // wire_c_per_micron[0][6] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2770 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2771 // fringe_cap);
2772 //*************************
2773
2774 //Conservative projections
2775 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um;
2776 aspect_ratio[1][0] = 2.0;
2777 wire_width = wire_pitch[1][0] / 2;
2778 wire_thickness = aspect_ratio[1][0] * wire_width;
2779 wire_spacing = wire_pitch[1][0] - wire_width;
2780 barrier_thickness = 0.002;
2781 dishing_thickness = 0;
2782 alpha_scatter = 1.05;
2783 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width,
2784 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2785 ild_thickness[1][0] = 0.108;
2786 miller_value[1][0] = 1.5;
2787 horiz_dielectric_constant[1][0] = 1.998;
2788 vert_dielectric_constant[1][0] = 3.9;
2789 fringe_cap = 0.115e-15;
2790 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2791 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0],
2792 fringe_cap);
2793
2794 wire_pitch[1][1] = 4 * g_ip->F_sz_um;
2795 wire_width = wire_pitch[1][1] / 2;
2796 aspect_ratio[1][1] = 2.0;
2797 wire_thickness = aspect_ratio[1][1] * wire_width;
2798 wire_spacing = wire_pitch[1][1] - wire_width;
2799 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width,
2800 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2801 ild_thickness[1][1] = 0.108;
2802 miller_value[1][1] = 1.5;
2803 horiz_dielectric_constant[1][1] = 1.998;
2804 vert_dielectric_constant[1][1] = 3.9;
2805 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2806 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1],
2807 fringe_cap);
2808
2809 wire_pitch[1][2] = 8 * g_ip->F_sz_um;
2810 aspect_ratio[1][2] = 2.2;
2811 wire_width = wire_pitch[1][2] / 2;
2812 wire_thickness = aspect_ratio[1][2] * wire_width;
2813 wire_spacing = wire_pitch[1][2] - wire_width;
2814 dishing_thickness = 0.1 * wire_thickness;
2815 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width,
2816 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2817 ild_thickness[1][2] = 0.198;
2818 miller_value[1][2] = 1.5;
2819 horiz_dielectric_constant[1][2] = 1.998;
2820 vert_dielectric_constant[1][2] = 3.9;
2821 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2822 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2],
2823 fringe_cap);
2824 //Nominal projections for commodity DRAM wordline/bitline
2825 wire_pitch[1][3] = 2 * 0.016;//micron
2826 wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.016);//F/micron
2827 wire_r_per_micron[1][3] = 12 / 0.016;//ohm/micron
2828
2829 //******************
2830 // wire_pitch[1][4] = 16 * g_ip.F_sz_um;
2831 // aspect_ratio = 2.2;
2832 // wire_width = wire_pitch[1][4] / 2;
2833 // wire_thickness = aspect_ratio * wire_width;
2834 // wire_spacing = wire_pitch[1][4] - wire_width;
2835 // dishing_thickness = 0.1 * wire_thickness;
2836 // wire_r_per_micron[1][4] = wire_resistance(CU_RESISTIVITY, wire_width,
2837 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2838 // ild_thickness = 0.275;
2839 // wire_c_per_micron[1][4] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2840 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2841 // fringe_cap);
2842 //
2843 // wire_pitch[1][5] = 24 * g_ip.F_sz_um;
2844 // aspect_ratio = 2.2;
2845 // wire_width = wire_pitch[1][5] / 2;
2846 // wire_thickness = aspect_ratio * wire_width;
2847 // wire_spacing = wire_pitch[1][5] - wire_width;
2848 // dishing_thickness = 0.1 * wire_thickness;
2849 // wire_r_per_micron[1][5] = wire_resistance(CU_RESISTIVITY, wire_width,
2850 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2851 // ild_thickness = 0.275;
2852 // wire_c_per_micron[1][5] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2853 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2854 // fringe_cap);
2855 //
2856 // wire_pitch[1][6] = 32 * g_ip.F_sz_um;
2857 // aspect_ratio = 2.2;
2858 // wire_width = wire_pitch[1][6] / 2;
2859 // wire_thickness = aspect_ratio * wire_width;
2860 // wire_spacing = wire_pitch[1][6] - wire_width;
2861 // dishing_thickness = 0.1 * wire_thickness;
2862 // wire_r_per_micron[1][6] = wire_resistance(CU_RESISTIVITY, wire_width,
2863 // wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);
2864 // ild_thickness = 0.275;
2865 // wire_c_per_micron[1][6] = wire_capacitance(wire_width, wire_thickness, wire_spacing,
2866 // ild_thickness, miller_value, horiz_dielectric_constant, vert_dielectric_constant,
2867 // fringe_cap);
2868 }
2869 g_tp.wire_local.pitch += curr_alpha * wire_pitch[g_ip->ic_proj_type][(ram_cell_tech_type == comm_dram)?3:0];
2870 g_tp.wire_local.R_per_um += curr_alpha * wire_r_per_micron[g_ip->ic_proj_type][(ram_cell_tech_type == comm_dram)?3:0];
2871 g_tp.wire_local.C_per_um += curr_alpha * wire_c_per_micron[g_ip->ic_proj_type][(ram_cell_tech_type == comm_dram)?3:0];
2872 g_tp.wire_local.aspect_ratio += curr_alpha * aspect_ratio[g_ip->ic_proj_type][(ram_cell_tech_type == comm_dram)?3:0];
2873 g_tp.wire_local.ild_thickness += curr_alpha * ild_thickness[g_ip->ic_proj_type][(ram_cell_tech_type == comm_dram)?3:0];
2874 g_tp.wire_local.miller_value += curr_alpha * miller_value[g_ip->ic_proj_type][(ram_cell_tech_type == comm_dram)?3:0];
2875 g_tp.wire_local.horiz_dielectric_constant += curr_alpha* horiz_dielectric_constant[g_ip->ic_proj_type][(ram_cell_tech_type == comm_dram)?3:0];
2876 g_tp.wire_local.vert_dielectric_constant += curr_alpha* vert_dielectric_constant [g_ip->ic_proj_type][(ram_cell_tech_type == comm_dram)?3:0];
2877
2878 g_tp.wire_inside_mat.pitch += curr_alpha * wire_pitch[g_ip->ic_proj_type][g_ip->wire_is_mat_type];
2879 g_tp.wire_inside_mat.R_per_um += curr_alpha* wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type];
2880 g_tp.wire_inside_mat.C_per_um += curr_alpha* wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type];
2881 g_tp.wire_inside_mat.aspect_ratio += curr_alpha * aspect_ratio[g_ip->ic_proj_type][g_ip->wire_is_mat_type];
2882 g_tp.wire_inside_mat.ild_thickness += curr_alpha * ild_thickness[g_ip->ic_proj_type][g_ip->wire_is_mat_type];
2883 g_tp.wire_inside_mat.miller_value += curr_alpha * miller_value[g_ip->ic_proj_type][g_ip->wire_is_mat_type];
2884 g_tp.wire_inside_mat.horiz_dielectric_constant += curr_alpha* horiz_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_is_mat_type];
2885 g_tp.wire_inside_mat.vert_dielectric_constant += curr_alpha* vert_dielectric_constant [g_ip->ic_proj_type][g_ip->wire_is_mat_type];
2886
2887 g_tp.wire_outside_mat.pitch += curr_alpha * wire_pitch[g_ip->ic_proj_type][g_ip->wire_os_mat_type];
2888 g_tp.wire_outside_mat.R_per_um += curr_alpha*wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type];
2889 g_tp.wire_outside_mat.C_per_um += curr_alpha*wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type];
2890 g_tp.wire_outside_mat.aspect_ratio += curr_alpha * aspect_ratio[g_ip->ic_proj_type][g_ip->wire_os_mat_type];
2891 g_tp.wire_outside_mat.ild_thickness += curr_alpha * ild_thickness[g_ip->ic_proj_type][g_ip->wire_os_mat_type];
2892 g_tp.wire_outside_mat.miller_value += curr_alpha * miller_value[g_ip->ic_proj_type][g_ip->wire_os_mat_type];
2893 g_tp.wire_outside_mat.horiz_dielectric_constant += curr_alpha* horiz_dielectric_constant[g_ip->ic_proj_type][g_ip->wire_os_mat_type];
2894 g_tp.wire_outside_mat.vert_dielectric_constant += curr_alpha* vert_dielectric_constant [g_ip->ic_proj_type][g_ip->wire_os_mat_type];
2895
2896 g_tp.unit_len_wire_del = g_tp.wire_inside_mat.R_per_um * g_tp.wire_inside_mat.C_per_um / 2;
2897
2898 g_tp.sense_delay += curr_alpha *SENSE_AMP_D;
2899 g_tp.sense_dy_power += curr_alpha *SENSE_AMP_P;
2900 // g_tp.horiz_dielectric_constant += horiz_dielectric_constant;
2901 // g_tp.vert_dielectric_constant += vert_dielectric_constant;
2902 // g_tp.aspect_ratio += aspect_ratio;
2903 // g_tp.miller_value += miller_value;
2904 // g_tp.ild_thickness += ild_thickness;
2905
2906 }
2907 g_tp.fringe_cap = fringe_cap;
2908
2909 double rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1);
2910 double p_to_n_sizing_r = pmos_to_nmos_sz_ratio();
2911 double c_load = gate_C(g_tp.min_w_nmos_ * (1 + p_to_n_sizing_r), 0.0);
2912 double tf = rd * c_load;
2913 g_tp.kinv = horowitz(0, tf, 0.5, 0.5, RISE);
2914 double KLOAD = 1;
2915 c_load = KLOAD * (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) +
2916 drain_C_(g_tp.min_w_nmos_ * p_to_n_sizing_r, PCH, 1, 1, g_tp.cell_h_def) +
2917 gate_C(g_tp.min_w_nmos_ * 4 * (1 + p_to_n_sizing_r), 0.0));
2918 tf = rd * c_load;
2919 g_tp.FO4 = horowitz(0, tf, 0.5, 0.5, RISE);
2920 }
2921