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45 #ifndef EXT_SST_EXTMASTER_HH
46 #define EXT_SST_EXTMASTER_HH
51 #include <core/component.h>
52 #include <elements/memHierarchy/memEvent.h>
54 #include <sim/sim_object.hh>
55 #include <mem/packet.hh>
56 #include <mem/request.hh>
57 #include <mem/external_master.hh>
61 using MemHierarchy::MemEvent;
65 namespace MemHierarchy {
73 class ExtMaster : public ExternalMaster::Port {
75 enum Phase { CONSTRUCTION, INIT, RUN };
78 const ExternalMaster& port;
81 gem5Component *const gem5;
82 const std::string name;
83 std::list<PacketPtr> sendQ;
84 bool blocked() { return !sendQ.empty(); }
86 MemHierarchy::MemNIC * nic;
88 struct SenderState : public Packet::SenderState
91 SenderState(MemEvent* e) : event(e) {}
94 std::set<AddrRange> ranges;
97 bool recvTimingResp(PacketPtr);
100 ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&);
101 void init(unsigned phase);
107 // receive Requests from SST bound for a gem5 slave;
108 // this module is "external" from gem5's perspective, thus ExternalMaster.
109 void handleEvent(SST::Event*);
112 virtual void recvRangeChange();