1 // Copyright (c) 2015 ARM Limited
2 // All rights reserved.
4 // The license below extends only to copyright in the software and shall
5 // not be construed as granting a license to any other intellectual
6 // property including but not limited to intellectual property relating
7 // to a hardware implementation of the functionality of the software
8 // licensed hereunder. You may use the software subject to the license
9 // terms below provided that you ensure that this notice is replicated
10 // unmodified and in its entirety in all distributions of the software,
11 // modified or unmodified, in source code or in binary form.
13 // Redistribution and use in source and binary forms, with or without
14 // modification, are permitted provided that the following conditions are
15 // met: redistributions of source code must retain the above copyright
16 // notice, this list of conditions and the following disclaimer;
17 // redistributions in binary form must reproduce the above copyright
18 // notice, this list of conditions and the following disclaimer in the
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20 // neither the name of the copyright holders nor the names of its
21 // contributors may be used to endorse or promote products derived from
22 // this software without specific prior written permission.
24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 // Copyright 2009-2014 Sandia Coporation. Under the terms
37 // of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
38 // Government retains certain rights in this software.
40 // Copyright (c) 2009-2014, Sandia Corporation
41 // All rights reserved.
43 // For license information, see the LICENSE file in the current directory.
47 #include <sst_config.h>
48 #include <sst/core/serialization.h>
50 #include <sst/core/params.h>
51 #include <sst/core/output.h>
52 #include <sst/core/link.h>
54 #ifdef fatal // gem5 sets this
59 using namespace SST::gem5
;
60 using namespace SST::MemHierarchy
;
62 ExtSlave::ExtSlave(gem5Component
*g5c
, Output
&out
,
63 ::ExternalSlave
& port
, std::string
&name
) :
65 comp(g5c
), out(out
), simPhase(CONSTRUCTION
), initPackets(NULL
),
66 link(comp
->configureLink(name
, new Event::Handler
<ExtSlave
>(this,
67 &ExtSlave::handleEvent
)))
70 out
.fatal(CALL_INFO
, 1, "Failed to configure link %s\n", name
.c_str());
74 void ExtSlave::init(unsigned phase
)
78 while (!initPackets
->empty()) {
79 link
->sendInitData(initPackets
->front());
80 initPackets
->pop_front();
88 ExtSlave::recvFunctional(PacketPtr pkt
)
90 if (simPhase
== CONSTRUCTION
) {
91 if (initPackets
== NULL
) {
92 initPackets
= new std::list
<MemEvent
*>;
94 ::MemCmd::Command pktCmd
= (::MemCmd::Command
)pkt
->cmd
.toInt();
95 assert(pktCmd
== ::MemCmd::WriteReq
|| pktCmd
== ::MemCmd::Writeback
);
96 Addr a
= pkt
->getAddr();
97 MemEvent
* ev
= new MemEvent(comp
, a
, a
, GetX
);
98 ev
->setPayload(pkt
->getSize(), pkt
->getPtr
<uint8_t>());
99 initPackets
->push_back(ev
);
101 panic("Functional accesses not allowed after construction phase");
106 ExtSlave::recvTimingReq(PacketPtr pkt
)
109 switch ((::MemCmd::Command
)pkt
->cmd
.toInt()) {
110 case ::MemCmd::HardPFReq
:
111 case ::MemCmd::SoftPFReq
:
112 case ::MemCmd::LoadLockedReq
:
113 case ::MemCmd::ReadExReq
:
114 case ::MemCmd::ReadReq
: cmd
= GetS
; break;
115 case ::MemCmd::StoreCondReq
:
116 case ::MemCmd::WriteReq
: cmd
= GetX
; break;
118 out
.fatal(CALL_INFO
, 1, "Don't know how to convert gem5 packet "
119 "command %s to SST\n", pkt
->cmd
.toString().c_str());
122 auto ev
= new MemEvent(comp
, pkt
->getAddr(), pkt
->getAddr(), cmd
);
123 ev
->setPayload(pkt
->getSize(), pkt
->getPtr
<uint8_t>());
124 if ((::MemCmd::Command
)pkt
->cmd
.toInt() == ::MemCmd::LoadLockedReq
)
126 else if ((::MemCmd::Command
)pkt
->cmd
.toInt() == ::MemCmd::StoreCondReq
)
127 ev
->setStoreConditional();
129 if (pkt
->req
->isLocked()) ev
->setFlag(MemEvent::F_LOCKED
);
130 if (pkt
->req
->isUncacheable()) ev
->setFlag(MemEvent::F_NONCACHEABLE
);
131 if (pkt
->req
->hasContextId()) ev
->setGroupId(pkt
->req
->contextId());
132 // Prefetches not working with SST; it maybe be dropping them, treating them
133 // as not deserving of responses, or something else -- not sure yet.
134 // ev->setPrefetchFlag(pkt->req->isPrefetch());
136 if (simPhase
== INIT
) {
137 link
->sendInitData(ev
);
141 if (pkt
->needsResponse()) {
142 PacketMap
[ev
->getID()] = pkt
;
151 ExtSlave::handleEvent(Event
* ev
)
153 MemEvent
* event
= dynamic_cast<MemEvent
*>(ev
);
155 out
.fatal(CALL_INFO
, 1, "ExtSlave handleEvent received non-MemEvent\n");
159 Event::id_type id
= event
->getID();
161 PacketMap_t::iterator mi
= PacketMap
.find(id
);
162 if (mi
!= PacketMap
.end()) { // replying to prior request
163 PacketPtr pkt
= mi
->second
;
166 pkt
->makeResponse(); // Convert to a response packet
167 pkt
->setData(event
->getPayload().data());
169 // Resolve the success of Store Conditionals
170 if (pkt
->isLLSC() && pkt
->isWrite()) {
171 pkt
->req
->setExtraData(event
->isAtomic());
174 // Clear out bus delay notifications
175 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
177 if (blocked() || !sendTimingResp(pkt
)) {
178 respQ
.push_back(pkt
);
180 } else { // we can handle unexpected invalidates, but nothing else.
181 Command cmd
= event
->getCmd();
184 // make Req/Pkt for Snoop/no response needed
185 // presently no consideration for masterId, packet type, flags...
186 RequestPtr req
= new Request(event
->getAddr(), event
->getSize(), 0, 0);
187 auto pkt
= new Packet(req
, ::MemCmd::InvalidationReq
);
189 // Clear out bus delay notifications
190 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
192 sendTimingSnoopReq(pkt
);
198 ExtSlave::recvRespRetry()
200 while (blocked() && sendTimingResp(respQ
.front())) {