ext/sst/README

   1 This directory contains a connector that allows gem5 to be used as a
   2 component in SST (Structural Simulation Toolkit, sst-simulator.org). More
   3 specifically, it creates a .so that wraps the libgem5_*.so library. At a
   4 high level, this allows memory traffic to pass between the two simulators.
   5 SST Links are roughly analogous to gem5 Ports, although Links do not have
   6 a notion of master and slave. This distinction is important to gem5, so
   7 when connecting a gem5 CPU to an SST cache, an ExternalSlave must be used,
   8 and similarly when connecting the memory side of SST cache to a gem5 port
   9 (for memory <-> I/O), an ExternalMaster must be used.
  10
  11 The connector handles the administrative aspects of gem5
  12 (initialization, simulation, shutdown) as well as translating
  13 SST's MemEvents into gem5 Packets and vice-versa.
  14
  15 Step-by-step instructions:
  16
  17 0. install SST and its dependencies
  18
  19 Note: the Makefile assumes you installed from an SVN checkout, not a release.
  20 If you install a release, modify SST_VERSION at the top of the Makefile.
  21
  22 0b. set/append to the PKG_CONFIG_PATH variable the path where SST installed
  23     its pkgconfig, if not in a system-wide location.
  24
  25 Then from gem5 root:
  26
  27 1. build gem5 library:
  28 % scons build/ARM/libgem5_opt.so
  29
  30 Note: if you would rather use a fast, debug, etc. variant instead,
  31 modify GEM5_LIB at the top of the Makefile.
  32
  33 2. build gem5 SST component:
  34 % make -C ext/sst
  35
  36 3. run SST like so:
  37 % sst --add-lib-path <path to ./ext/sst> <config script, e.g. ext/sst/*.py>
  38
  39 ===========
  40
  41 Note: if you want to use an arch other than ARM (not tested/supported),
  42 tweak the Makefile to get includes from that build directory instead.
  43
  44 ===========
  45
  46 This directory provides:
  47 1. an SST "Component" for gem5;
  48 2. a class that implements gem5's "ExternalMaster" interface to connect with
  49    SST "Link"s exchanging "memEvents"
  50    (sst/elements/memHierarchy stuff - caches, memories, etc.)
  51    This lets gem5 receive packets from SST, as in
  52    an SST LL$ (a master external to gem5) <-> I/O devices.
  53 3. a class that implements gem5's "ExternalSlave" interface to connect with
  54    SST "Link"s exchanging "memEvents" once again with the packet flow reversed:
  55    gem5 CPU <-> SST L1 cache (a slave external to gem5)
  56 4. an example configuration that uses both as follows:
  57    gem5 CPUs
  58        ^
  59        | [ExternalSlave]
  60        v
  61    SST cache hierarchy <-> SST memory
  62        ^
  63        | [ExternalMaster]
  64        v
  65    gem5 I/O devices (terminal, disk, etc.)