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  17 From: Staf Verhaegen <staf@fibraservi.eu>
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  19 Date: Thu, 26 Mar 2020 21:08:04 +0100
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  32 Subject: Re: [libre-riscv-dev] cache SRAM organisation
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  60
  61 Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 15:15 [+0000]:
  62 > On Thursday, March 26, 2020, Staf Verhaegen <staf@fibraservi.eu> wrote:
  63 > > I can understand you do this to implement functional units withconfigur=
  64 able pipeline length but I would strongly discourage to pipelineregister fi=
  65 les after each other .
  66 >=20
  67 >=20
  68 > "pipeline register files after each other"? apologies i am not clear what=
  69 you mean, here.  do you mean "don't do write-thru on the Regfile"?
  70
  71 No I meant for example connecting the output of one port of an asynchronous=
  72  RAM to for example the address input of another port of an asynchronous RA=
  73 M.
  74
  75 greets,
  76 Staf.
  77
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