fetch1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity fetch1 is
   9     generic(
  10         RESET_ADDRESS     : std_logic_vector(63 downto 0) := (others => '0');
  11         ALT_RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
  12         );
  13     port(
  14         clk           : in std_ulogic;
  15         rst           : in std_ulogic;
  16
  17         -- Control inputs:
  18         stall_in      : in std_ulogic;
  19         flush_in      : in std_ulogic;
  20         stop_in       : in std_ulogic;
  21         alt_reset_in  : in std_ulogic;
  22
  23         -- redirect from execution unit
  24         e_in          : in Execute1ToFetch1Type;
  25
  26         -- Request to icache
  27         i_out         : out Fetch1ToIcacheType
  28         );
  29 end entity fetch1;
  30
  31 architecture behaviour of fetch1 is
  32     type stop_state_t is (RUNNING, STOPPED, RESTARTING);
  33     type reg_internal_t is record
  34         stop_state: stop_state_t;
  35     end record;
  36     signal r, r_next : Fetch1ToIcacheType;
  37     signal r_int, r_next_int : reg_internal_t;
  38 begin
  39
  40     regs : process(clk)
  41     begin
  42         if rising_edge(clk) then
  43             if r /= r_next then
  44                 report "fetch1 rst:" & std_ulogic'image(rst) &
  45                     " R:" & std_ulogic'image(e_in.redirect) &
  46                     " S:" & std_ulogic'image(stall_in) &
  47                     " T:" & std_ulogic'image(stop_in) &
  48                     " nia:" & to_hstring(r_next.nia) &
  49                     " SM:" & std_ulogic'image(r_next.stop_mark);
  50             end if;
  51             r <= r_next;
  52             r_int <= r_next_int;
  53         end if;
  54     end process;
  55
  56     comb : process(all)
  57         variable v : Fetch1ToIcacheType;
  58         variable v_int : reg_internal_t;
  59         variable increment : boolean;
  60     begin
  61         v := r;
  62         v_int := r_int;
  63
  64         if rst = '1' then
  65             if alt_reset_in = '1' then
  66                 v.nia :=  ALT_RESET_ADDRESS;
  67             else
  68                 v.nia :=  RESET_ADDRESS;
  69             end if;
  70             v_int.stop_state := RUNNING;
  71         elsif e_in.redirect = '1' then
  72             v.nia := e_in.redirect_nia;
  73         elsif stall_in = '0' then
  74
  75             -- For debug stop/step to work properly we need a little bit of
  76             -- trickery here. If we just stop incrementing and send stop marks
  77             -- when stop_in is set, then we'll increment on the cycle it clears
  78             -- and end up never executing the instruction we were stopped on.
  79             --
  80             -- Avoid this along with the opposite issue when stepping (stop is
  81             -- cleared for only one cycle) is handled by the state machine below
  82             --
  83             -- By default, increment addresses
  84             increment := true;
  85             case v_int.stop_state is
  86             when RUNNING =>
  87                 -- If we are running and stop_in is set, then stop incrementing,
  88                 -- we are now stopped.
  89                 if stop_in = '1' then
  90                     increment := false;
  91                     v_int.stop_state := STOPPED;
  92                 end if;
  93             when STOPPED =>
  94                 -- When stopped, never increment. If stop is cleared, go to state
  95                 -- "restarting" but still don't increment that cycle. stop_in is
  96                 -- now 0 so we'll send the NIA down without a stop mark.
  97                 increment := false;
  98                 if stop_in = '0' then
  99                     v_int.stop_state := RESTARTING;
 100                 end if;
 101             when RESTARTING =>
 102                 -- We have just sent the NIA down, we can start incrementing again.
 103                 -- If stop_in is still not set, go back to running normally.
 104                 -- If stop_in is set again (that was a one-cycle "step"), go
 105                 -- back to "stopped" state which means we'll stop incrementing
 106                 -- on the next cycle. This ensures we increment the PC once after
 107                 -- sending one instruction without a stop mark. Since stop_in is
 108                 -- now set, the new PC will be sent with a stop mark and thus not
 109                 -- executed.
 110                 if stop_in = '0' then
 111                     v_int.stop_state := RUNNING;
 112                 else
 113                     v_int.stop_state := STOPPED;
 114                 end if;
 115             end case;
 116
 117             if increment then
 118                 v.nia := std_logic_vector(unsigned(v.nia) + 4);
 119             end if;
 120         end if;
 121
 122         v.req := not rst;
 123         v.stop_mark := stop_in;
 124
 125         r_next <= v;
 126         r_next_int <= v_int;
 127
 128         -- Update outputs to the icache
 129         i_out <= r;
 130
 131     end process;
 132
 133 end architecture behaviour;