2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
10 RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
17 stall_in : in std_ulogic;
18 flush_in : in std_ulogic;
20 -- redirect from execution unit
21 e_in : in Execute1ToFetch1Type;
24 f_out : out Fetch1ToFetch2Type
28 architecture behaviour of fetch1 is
29 type reg_internal_type is record
30 nia_next : std_ulogic_vector(63 downto 0);
32 signal r_int, rin_int : reg_internal_type;
33 signal r, rin : Fetch1ToFetch2Type;
37 if rising_edge(clk) then
44 variable v : Fetch1ToFetch2Type;
45 variable v_int : reg_internal_type;
50 if stall_in = '0' then
51 v.nia := r_int.nia_next;
52 v_int.nia_next := std_logic_vector(unsigned(r_int.nia_next) + 4);
55 if e_in.redirect = '1' then
56 v.nia := e_in.redirect_nia;
57 v_int.nia_next := std_logic_vector(unsigned(e_in.redirect_nia) + 4);
61 v.nia := RESET_ADDRESS;
62 v_int.nia_next := std_logic_vector(unsigned(RESET_ADDRESS) + 4);
72 report "fetch1 R:" & std_ulogic'image(e_in.redirect) & " v.nia:" & to_hstring(v.nia) & " f_out.nia:" & to_hstring(f_out.nia);
75 end architecture behaviour;